dc/dcn20/dcn20_hubp.h

0001 /*
0002  * Copyright 2012-17 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_MEM_INPUT_DCN20_H__
0027 #define __DC_MEM_INPUT_DCN20_H__
0028
0029 #include "../dcn10/dcn10_hubp.h"
0030
0031 #define TO_DCN20_HUBP(hubp)\
0032     container_of(hubp, struct dcn20_hubp, base)
0033
0034 #define HUBP_REG_LIST_DCN2_COMMON(id)\
0035     HUBP_REG_LIST_DCN(id),\
0036     HUBP_REG_LIST_DCN_VM(id),\
0037     SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
0038     SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
0039     SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
0040     SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
0041     SRI(CURSOR_SETTINGS, HUBPREQ, id), \
0042     SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
0043     SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
0044     SRI(CURSOR_SIZE, CURSOR0_, id), \
0045     SRI(CURSOR_CONTROL, CURSOR0_, id), \
0046     SRI(CURSOR_POSITION, CURSOR0_, id), \
0047     SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
0048     SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \
0049     SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \
0050     SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \
0051     SRI(DMDATA_CNTL, CURSOR0_, id), \
0052     SRI(DMDATA_SW_CNTL, CURSOR0_, id), \
0053     SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \
0054     SRI(DMDATA_SW_DATA, CURSOR0_, id), \
0055     SRI(DMDATA_STATUS, CURSOR0_, id),\
0056     SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\
0057     SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\
0058     SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\
0059     SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\
0060     SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\
0061     SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
0062     SRI(VMID_SETTINGS_0, HUBPREQ, id)
0063
0064 #define HUBP_REG_LIST_DCN20(id)\
0065     HUBP_REG_LIST_DCN2_COMMON(id),\
0066     SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
0067     SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
0068
0069 #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\
0070     HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
0071     HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
0072     HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
0073     HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
0074     HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
0075     HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
0076     HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
0077     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
0078     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
0079     HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
0080     HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
0081     HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
0082     HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
0083     HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
0084     HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
0085     HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
0086     HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
0087     HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
0088     HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
0089     HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
0090     HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
0091     HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
0092     HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
0093     HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
0094     HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
0095     HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
0096     HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
0097     HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
0098     HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
0099     HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
0100     HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
0101     HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
0102     HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
0103     HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
0104     HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
0105     HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
0106     HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
0107     HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
0108     HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
0109     HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
0110     HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
0111     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
0112     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
0113     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
0114     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
0115     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
0116     HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
0117
0118 /*DCN2.x and DCN1.x*/
0119 #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
0120     HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\
0121     HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
0122     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
0123     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
0124
0125 /*DCN2.0 specific*/
0126 #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
0127     HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
0128     HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
0129     HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
0130     HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
0131
0132 /*DCN2.x */
0133 #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
0134     HUBP_COMMON_REG_VARIABLE_LIST; \
0135     uint32_t DMDATA_ADDRESS_HIGH; \
0136     uint32_t DMDATA_ADDRESS_LOW; \
0137     uint32_t DMDATA_CNTL; \
0138     uint32_t DMDATA_SW_CNTL; \
0139     uint32_t DMDATA_QOS_CNTL; \
0140     uint32_t DMDATA_SW_DATA; \
0141     uint32_t DMDATA_STATUS;\
0142     uint32_t DCSURF_FLIP_CONTROL2;\
0143     uint32_t FLIP_PARAMETERS_0;\
0144     uint32_t FLIP_PARAMETERS_1;\
0145     uint32_t FLIP_PARAMETERS_2;\
0146     uint32_t DCN_CUR1_TTU_CNTL0;\
0147     uint32_t DCN_CUR1_TTU_CNTL1;\
0148     uint32_t VMID_SETTINGS_0
0149
0150
0151 #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
0152     DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
0153     uint32_t FLIP_PARAMETERS_3;\
0154     uint32_t FLIP_PARAMETERS_4;\
0155     uint32_t FLIP_PARAMETERS_5;\
0156     uint32_t FLIP_PARAMETERS_6;\
0157     uint32_t VBLANK_PARAMETERS_5;\
0158     uint32_t VBLANK_PARAMETERS_6
0159
0160 #define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \
0161     DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
0162     uint32_t DCN_DMDATA_VM_CNTL
0163
0164 #define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \
0165     DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\
0166     uint32_t DCHUBP_MALL_CONFIG;\
0167     uint32_t DCHUBP_VMPG_CONFIG;\
0168     uint32_t UCLK_PSTATE_FORCE
0169
0170 #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
0171     DCN_HUBP_REG_FIELD_BASE_LIST(type); \
0172     type DMDATA_ADDRESS_HIGH;\
0173     type DMDATA_MODE;\
0174     type DMDATA_UPDATED;\
0175     type DMDATA_REPEAT;\
0176     type DMDATA_SIZE;\
0177     type DMDATA_SW_UPDATED;\
0178     type DMDATA_SW_REPEAT;\
0179     type DMDATA_SW_SIZE;\
0180     type DMDATA_QOS_MODE;\
0181     type DMDATA_QOS_LEVEL;\
0182     type DMDATA_DL_DELTA;\
0183     type DMDATA_DONE;\
0184     type DST_Y_PER_VM_FLIP;\
0185     type DST_Y_PER_ROW_FLIP;\
0186     type REFCYC_PER_PTE_GROUP_FLIP_L;\
0187     type REFCYC_PER_META_CHUNK_FLIP_L;\
0188     type HUBP_VREADY_AT_OR_AFTER_VSYNC;\
0189     type HUBP_DISABLE_STOP_DATA_DURING_VM;\
0190     type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\
0191     type SURFACE_GSL_ENABLE;\
0192     type SURFACE_TRIPLE_BUFFER_ENABLE;\
0193     type VMID
0194
0195 #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
0196     DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
0197     type REFCYC_PER_VM_GROUP_FLIP;\
0198     type REFCYC_PER_VM_REQ_FLIP;\
0199     type REFCYC_PER_VM_GROUP_VBLANK;\
0200     type REFCYC_PER_VM_REQ_VBLANK;\
0201     type REFCYC_PER_PTE_GROUP_FLIP_C; \
0202     type REFCYC_PER_META_CHUNK_FLIP_C; \
0203     type VM_GROUP_SIZE
0204
0205 #define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
0206     DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
0207     type PRIMARY_SURFACE_DCC_IND_BLK;\
0208     type SECONDARY_SURFACE_DCC_IND_BLK;\
0209     type PRIMARY_SURFACE_DCC_IND_BLK_C;\
0210     type SECONDARY_SURFACE_DCC_IND_BLK_C;\
0211     type ALPHA_PLANE_EN;\
0212     type REFCYC_PER_VM_DMDATA;\
0213     type DMDATA_VM_FAULT_STATUS;\
0214     type DMDATA_VM_FAULT_STATUS_CLEAR; \
0215     type DMDATA_VM_UNDERFLOW_STATUS;\
0216     type DMDATA_VM_LATE_STATUS;\
0217     type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \
0218     type DMDATA_VM_DONE; \
0219     type CROSSBAR_SRC_Y_G; \
0220     type CROSSBAR_SRC_ALPHA; \
0221     type PACK_3TO2_ELEMENT_DISABLE; \
0222     type ROW_TTU_MODE; \
0223     type NUM_PKRS
0224
0225 #define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \
0226     DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\
0227     type HUBP_UNBOUNDED_REQ_MODE;\
0228     type CURSOR_REQ_MODE;\
0229     type HUBP_SOFT_RESET
0230
0231 #define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \
0232     DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\
0233     type USE_MALL_SEL; \
0234     type USE_MALL_FOR_CURSOR;\
0235     type VMPG_SIZE; \
0236     type PTE_BUFFER_MODE; \
0237     type BIGK_FRAGMENT_SIZE; \
0238     type FORCE_ONE_ROW_FOR_FRAME; \
0239     type DATA_UCLK_PSTATE_FORCE_EN; \
0240     type DATA_UCLK_PSTATE_FORCE_VALUE; \
0241     type CURSOR_UCLK_PSTATE_FORCE_EN; \
0242     type CURSOR_UCLK_PSTATE_FORCE_VALUE
0243
0244 struct dcn_hubp2_registers {
0245     DCN32_HUBP_REG_COMMON_VARIABLE_LIST;
0246 };
0247
0248 struct dcn_hubp2_shift {
0249     DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
0250 };
0251
0252 struct dcn_hubp2_mask {
0253     DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
0254 };
0255
0256 struct dcn20_hubp {
0257     struct hubp base;
0258     struct dcn_hubp_state state;
0259     const struct dcn_hubp2_registers *hubp_regs;
0260     const struct dcn_hubp2_shift *hubp_shift;
0261     const struct dcn_hubp2_mask *hubp_mask;
0262 };
0263
0264 bool hubp2_construct(
0265         struct dcn20_hubp *hubp2,
0266         struct dc_context *ctx,
0267         uint32_t inst,
0268         const struct dcn_hubp2_registers *hubp_regs,
0269         const struct dcn_hubp2_shift *hubp_shift,
0270         const struct dcn_hubp2_mask *hubp_mask);
0271
0272 void hubp2_setup_interdependent(
0273         struct hubp *hubp,
0274         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0275         struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
0276
0277 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
0278         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
0279
0280 void hubp2_cursor_set_attributes(
0281         struct hubp *hubp,
0282         const struct dc_cursor_attributes *attr);
0283
0284 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
0285         struct vm_system_aperture_param *apt);
0286
0287 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
0288         unsigned int cursor_width,
0289         enum dc_cursor_color_format cursor_mode);
0290
0291 void hubp2_dmdata_set_attributes(
0292         struct hubp *hubp,
0293         const struct dc_dmdata_attributes *attr);
0294
0295 void hubp2_dmdata_load(
0296         struct hubp *hubp,
0297         uint32_t dmdata_sw_size,
0298         const uint32_t *dmdata_sw_data);
0299
0300 bool hubp2_dmdata_status_done(struct hubp *hubp);
0301
0302 void hubp2_enable_triplebuffer(
0303         struct hubp *hubp,
0304         bool enable);
0305
0306 bool hubp2_is_triplebuffer_enabled(
0307         struct hubp *hubp);
0308
0309 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable);
0310
0311 void hubp2_program_deadline(
0312         struct hubp *hubp,
0313         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0314         struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
0315
0316 bool hubp2_program_surface_flip_and_addr(
0317     struct hubp *hubp,
0318     const struct dc_plane_address *address,
0319     bool flip_immediate);
0320
0321 void hubp2_dcc_control(struct hubp *hubp, bool enable,
0322         enum hubp_ind_block_size independent_64b_blks);
0323
0324 void hubp2_program_size(
0325     struct hubp *hubp,
0326     enum surface_pixel_format format,
0327     const struct plane_size *plane_size,
0328     struct dc_plane_dcc_param *dcc);
0329
0330 void hubp2_program_rotation(
0331     struct hubp *hubp,
0332     enum dc_rotation_angle rotation,
0333     bool horizontal_mirror);
0334
0335 void hubp2_program_pixel_format(
0336     struct hubp *hubp,
0337     enum surface_pixel_format format);
0338
0339 void hubp2_program_surface_config(
0340     struct hubp *hubp,
0341     enum surface_pixel_format format,
0342     union dc_tiling_info *tiling_info,
0343     struct plane_size *plane_size,
0344     enum dc_rotation_angle rotation,
0345     struct dc_plane_dcc_param *dcc,
0346     bool horizontal_mirror,
0347     unsigned int compat_level);
0348
0349 bool hubp2_is_flip_pending(struct hubp *hubp);
0350
0351 void hubp2_set_blank(struct hubp *hubp, bool blank);
0352 void hubp2_set_blank_regs(struct hubp *hubp, bool blank);
0353
0354 void hubp2_cursor_set_position(
0355         struct hubp *hubp,
0356         const struct dc_cursor_position *pos,
0357         const struct dc_cursor_mi_param *param);
0358
0359 void hubp2_clk_cntl(struct hubp *hubp, bool enable);
0360
0361 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
0362
0363 void hubp2_clear_underflow(struct hubp *hubp);
0364
0365 void hubp2_read_state_common(struct hubp *hubp);
0366
0367 void hubp2_read_state(struct hubp *hubp);
0368
0369 #endif /* __DC_MEM_INPUT_DCN20_H__ */
0370
0371