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0001 /*
0002  * Copyright 2012-2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dcn20_hubp.h"
0027 
0028 #include "dm_services.h"
0029 #include "dce_calcs.h"
0030 #include "reg_helper.h"
0031 #include "basics/conversion.h"
0032 
0033 #define DC_LOGGER_INIT(logger)
0034 
0035 #define REG(reg)\
0036     hubp2->hubp_regs->reg
0037 
0038 #define CTX \
0039     hubp2->base.ctx
0040 
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
0044 
0045 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
0046         struct vm_system_aperture_param *apt)
0047 {
0048     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0049 
0050     PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
0051     PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
0052     PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
0053 
0054     // The format of default addr is 48:12 of the 48 bit addr
0055     mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
0056 
0057     // The format of high/low are 48:18 of the 48 bit addr
0058     mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
0059     mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
0060 
0061     REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0062         DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
0063         DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
0064 
0065     REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
0066             DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
0067 
0068     REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
0069             MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
0070 
0071     REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
0072             MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
0073 
0074     REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
0075             ENABLE_L1_TLB, 1,
0076             SYSTEM_ACCESS_MODE, 0x3);
0077 }
0078 
0079 void hubp2_program_deadline(
0080         struct hubp *hubp,
0081         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0082         struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
0083 {
0084     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0085 
0086     /* DLG - Per hubp */
0087     REG_SET_2(BLANK_OFFSET_0, 0,
0088         REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
0089         DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
0090 
0091     REG_SET(BLANK_OFFSET_1, 0,
0092         MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
0093 
0094     REG_SET(DST_DIMENSIONS, 0,
0095         REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
0096 
0097     REG_SET_2(DST_AFTER_SCALER, 0,
0098         REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
0099         DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
0100 
0101     REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
0102         REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
0103 
0104     /* DLG - Per luma/chroma */
0105     REG_SET(VBLANK_PARAMETERS_1, 0,
0106         REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
0107 
0108     if (REG(NOM_PARAMETERS_0))
0109         REG_SET(NOM_PARAMETERS_0, 0,
0110             DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
0111 
0112     if (REG(NOM_PARAMETERS_1))
0113         REG_SET(NOM_PARAMETERS_1, 0,
0114             REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
0115 
0116     REG_SET(NOM_PARAMETERS_4, 0,
0117         DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
0118 
0119     REG_SET(NOM_PARAMETERS_5, 0,
0120         REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
0121 
0122     REG_SET_2(PER_LINE_DELIVERY, 0,
0123         REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
0124         REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
0125 
0126     REG_SET(VBLANK_PARAMETERS_2, 0,
0127         REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
0128 
0129     if (REG(NOM_PARAMETERS_2))
0130         REG_SET(NOM_PARAMETERS_2, 0,
0131             DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
0132 
0133     if (REG(NOM_PARAMETERS_3))
0134         REG_SET(NOM_PARAMETERS_3, 0,
0135             REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
0136 
0137     REG_SET(NOM_PARAMETERS_6, 0,
0138         DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
0139 
0140     REG_SET(NOM_PARAMETERS_7, 0,
0141         REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
0142 
0143     /* TTU - per hubp */
0144     REG_SET_2(DCN_TTU_QOS_WM, 0,
0145         QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
0146         QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
0147 
0148     /* TTU - per luma/chroma */
0149     /* Assumed surf0 is luma and 1 is chroma */
0150 
0151     REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
0152         REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
0153         QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
0154         QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
0155 
0156     REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
0157         REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
0158         QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
0159         QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
0160 
0161     REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
0162         REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
0163         QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
0164         QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
0165 
0166     REG_SET(FLIP_PARAMETERS_1, 0,
0167         REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
0168 }
0169 
0170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
0171         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
0172 {
0173     uint32_t value = 0;
0174     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0175     /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
0176     REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
0177     /*
0178     if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
0179     <= OTG_V_BLANK_END
0180         Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
0181     else
0182         Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
0183     */
0184     if (pipe_dest->htotal != 0) {
0185         if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
0186             + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
0187             value = 1;
0188         } else
0189             value = 0;
0190     }
0191 
0192     REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
0193 }
0194 
0195 static void hubp2_program_requestor(struct hubp *hubp,
0196                     struct _vcs_dpi_display_rq_regs_st *rq_regs)
0197 {
0198     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0199 
0200     REG_UPDATE(HUBPRET_CONTROL,
0201             DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
0202     REG_SET_4(DCN_EXPANSION_MODE, 0,
0203             DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
0204             PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
0205             MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
0206             CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
0207     REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
0208         CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
0209         MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
0210         META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
0211         MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
0212         DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
0213         MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
0214         SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
0215         PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
0216     REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
0217         CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
0218         MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
0219         META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
0220         MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
0221         DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
0222         MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
0223         SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
0224         PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
0225 }
0226 
0227 static void hubp2_setup(
0228         struct hubp *hubp,
0229         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0230         struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
0231         struct _vcs_dpi_display_rq_regs_st *rq_regs,
0232         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
0233 {
0234     /* otg is locked when this func is called. Register are double buffered.
0235      * disable the requestors is not needed
0236      */
0237 
0238     hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
0239     hubp2_program_requestor(hubp, rq_regs);
0240     hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
0241 
0242 }
0243 
0244 void hubp2_setup_interdependent(
0245         struct hubp *hubp,
0246         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0247         struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
0248 {
0249     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0250 
0251     REG_SET_2(PREFETCH_SETTINGS, 0,
0252             DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
0253             VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
0254 
0255     REG_SET(PREFETCH_SETTINGS_C, 0,
0256             VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
0257 
0258     REG_SET_2(VBLANK_PARAMETERS_0, 0,
0259         DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
0260         DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
0261 
0262     REG_SET_2(FLIP_PARAMETERS_0, 0,
0263         DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
0264         DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
0265 
0266     REG_SET(VBLANK_PARAMETERS_3, 0,
0267         REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
0268 
0269     REG_SET(VBLANK_PARAMETERS_4, 0,
0270         REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
0271 
0272     REG_SET(FLIP_PARAMETERS_2, 0,
0273         REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
0274 
0275     REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
0276         REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
0277         REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
0278 
0279     REG_SET(DCN_SURF0_TTU_CNTL1, 0,
0280         REFCYC_PER_REQ_DELIVERY_PRE,
0281         ttu_attr->refcyc_per_req_delivery_pre_l);
0282     REG_SET(DCN_SURF1_TTU_CNTL1, 0,
0283         REFCYC_PER_REQ_DELIVERY_PRE,
0284         ttu_attr->refcyc_per_req_delivery_pre_c);
0285     REG_SET(DCN_CUR0_TTU_CNTL1, 0,
0286         REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
0287     REG_SET(DCN_CUR1_TTU_CNTL1, 0,
0288         REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
0289 
0290     REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
0291         MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
0292         QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
0293 }
0294 
0295 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
0296  *  NUM_BANKS
0297  *  NUM_SE
0298  *  NUM_RB_PER_SE
0299  *  RB_ALIGNED
0300  * Other things can be defaulted, since they never change:
0301  *  PIPE_ALIGNED = 0
0302  *  META_LINEAR = 0
0303  * In GFX10, only these apply:
0304  *  PIPE_INTERLEAVE
0305  *  NUM_PIPES
0306  *  MAX_COMPRESSED_FRAGS
0307  *  SW_MODE
0308  */
0309 static void hubp2_program_tiling(
0310     struct dcn20_hubp *hubp2,
0311     const union dc_tiling_info *info,
0312     const enum surface_pixel_format pixel_format)
0313 {
0314     REG_UPDATE_3(DCSURF_ADDR_CONFIG,
0315             NUM_PIPES, log_2(info->gfx9.num_pipes),
0316             PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
0317             MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
0318 
0319     REG_UPDATE_4(DCSURF_TILING_CONFIG,
0320             SW_MODE, info->gfx9.swizzle,
0321             META_LINEAR, 0,
0322             RB_ALIGNED, 0,
0323             PIPE_ALIGNED, 0);
0324 }
0325 
0326 void hubp2_program_size(
0327     struct hubp *hubp,
0328     enum surface_pixel_format format,
0329     const struct plane_size *plane_size,
0330     struct dc_plane_dcc_param *dcc)
0331 {
0332     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0333     uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
0334     bool use_pitch_c = false;
0335 
0336     /* Program data and meta surface pitch (calculation from addrlib)
0337      * 444 or 420 luma
0338      */
0339     use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
0340         && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
0341     use_pitch_c = use_pitch_c
0342         || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
0343     if (use_pitch_c) {
0344         ASSERT(plane_size->chroma_pitch != 0);
0345         /* Chroma pitch zero can cause system hang! */
0346 
0347         pitch = plane_size->surface_pitch - 1;
0348         meta_pitch = dcc->meta_pitch - 1;
0349         pitch_c = plane_size->chroma_pitch - 1;
0350         meta_pitch_c = dcc->meta_pitch_c - 1;
0351     } else {
0352         pitch = plane_size->surface_pitch - 1;
0353         meta_pitch = dcc->meta_pitch - 1;
0354         pitch_c = 0;
0355         meta_pitch_c = 0;
0356     }
0357 
0358     if (!dcc->enable) {
0359         meta_pitch = 0;
0360         meta_pitch_c = 0;
0361     }
0362 
0363     REG_UPDATE_2(DCSURF_SURFACE_PITCH,
0364             PITCH, pitch, META_PITCH, meta_pitch);
0365 
0366     use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
0367     use_pitch_c = use_pitch_c
0368         || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
0369     if (use_pitch_c)
0370         REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
0371             PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
0372 }
0373 
0374 void hubp2_program_rotation(
0375     struct hubp *hubp,
0376     enum dc_rotation_angle rotation,
0377     bool horizontal_mirror)
0378 {
0379     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0380     uint32_t mirror;
0381 
0382 
0383     if (horizontal_mirror)
0384         mirror = 1;
0385     else
0386         mirror = 0;
0387 
0388     /* Program rotation angle and horz mirror - no mirror */
0389     if (rotation == ROTATION_ANGLE_0)
0390         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0391                 ROTATION_ANGLE, 0,
0392                 H_MIRROR_EN, mirror);
0393     else if (rotation == ROTATION_ANGLE_90)
0394         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0395                 ROTATION_ANGLE, 1,
0396                 H_MIRROR_EN, mirror);
0397     else if (rotation == ROTATION_ANGLE_180)
0398         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0399                 ROTATION_ANGLE, 2,
0400                 H_MIRROR_EN, mirror);
0401     else if (rotation == ROTATION_ANGLE_270)
0402         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0403                 ROTATION_ANGLE, 3,
0404                 H_MIRROR_EN, mirror);
0405 }
0406 
0407 void hubp2_dcc_control(struct hubp *hubp, bool enable,
0408         enum hubp_ind_block_size independent_64b_blks)
0409 {
0410     uint32_t dcc_en = enable ? 1 : 0;
0411     uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
0412     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0413 
0414     REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
0415             PRIMARY_SURFACE_DCC_EN, dcc_en,
0416             PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
0417             SECONDARY_SURFACE_DCC_EN, dcc_en,
0418             SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
0419 }
0420 
0421 void hubp2_program_pixel_format(
0422     struct hubp *hubp,
0423     enum surface_pixel_format format)
0424 {
0425     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0426     uint32_t red_bar = 3;
0427     uint32_t blue_bar = 2;
0428 
0429     /* swap for ABGR format */
0430     if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
0431             || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
0432             || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
0433             || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
0434             || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
0435         red_bar = 2;
0436         blue_bar = 3;
0437     }
0438 
0439     REG_UPDATE_2(HUBPRET_CONTROL,
0440             CROSSBAR_SRC_CB_B, blue_bar,
0441             CROSSBAR_SRC_CR_R, red_bar);
0442 
0443     /* Mapping is same as ipp programming (cnvc) */
0444 
0445     switch (format) {
0446     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0447         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0448                 SURFACE_PIXEL_FORMAT, 1);
0449         break;
0450     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0451         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0452                 SURFACE_PIXEL_FORMAT, 3);
0453         break;
0454     case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
0455     case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
0456         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0457                 SURFACE_PIXEL_FORMAT, 8);
0458         break;
0459     case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
0460     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
0461     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
0462         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0463                 SURFACE_PIXEL_FORMAT, 10);
0464         break;
0465     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0466     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
0467         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0468                 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
0469         break;
0470     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0471     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
0472         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0473                 SURFACE_PIXEL_FORMAT, 24);
0474         break;
0475 
0476     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0477         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0478                 SURFACE_PIXEL_FORMAT, 65);
0479         break;
0480     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0481         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0482                 SURFACE_PIXEL_FORMAT, 64);
0483         break;
0484     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0485         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0486                 SURFACE_PIXEL_FORMAT, 67);
0487         break;
0488     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0489         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0490                 SURFACE_PIXEL_FORMAT, 66);
0491         break;
0492     case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
0493         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0494                 SURFACE_PIXEL_FORMAT, 12);
0495         break;
0496     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
0497         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0498                 SURFACE_PIXEL_FORMAT, 112);
0499         break;
0500     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
0501         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0502                 SURFACE_PIXEL_FORMAT, 113);
0503         break;
0504     case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
0505         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0506                 SURFACE_PIXEL_FORMAT, 114);
0507         break;
0508     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
0509         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0510                 SURFACE_PIXEL_FORMAT, 118);
0511         break;
0512     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
0513         REG_UPDATE(DCSURF_SURFACE_CONFIG,
0514                 SURFACE_PIXEL_FORMAT, 119);
0515         break;
0516     case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
0517         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0518                 SURFACE_PIXEL_FORMAT, 116,
0519                 ALPHA_PLANE_EN, 0);
0520         break;
0521     case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
0522         REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
0523                 SURFACE_PIXEL_FORMAT, 116,
0524                 ALPHA_PLANE_EN, 1);
0525         break;
0526     default:
0527         BREAK_TO_DEBUGGER();
0528         break;
0529     }
0530 
0531     /* don't see the need of program the xbar in DCN 1.0 */
0532 }
0533 
0534 void hubp2_program_surface_config(
0535     struct hubp *hubp,
0536     enum surface_pixel_format format,
0537     union dc_tiling_info *tiling_info,
0538     struct plane_size *plane_size,
0539     enum dc_rotation_angle rotation,
0540     struct dc_plane_dcc_param *dcc,
0541     bool horizontal_mirror,
0542     unsigned int compat_level)
0543 {
0544     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0545 
0546     hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
0547     hubp2_program_tiling(hubp2, tiling_info, format);
0548     hubp2_program_size(hubp, format, plane_size, dcc);
0549     hubp2_program_rotation(hubp, rotation, horizontal_mirror);
0550     hubp2_program_pixel_format(hubp, format);
0551 }
0552 
0553 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
0554     unsigned int cursor_width,
0555     enum dc_cursor_color_format cursor_mode)
0556 {
0557     enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
0558 
0559     if (cursor_mode == CURSOR_MODE_MONO)
0560         line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
0561     else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
0562          cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
0563          cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
0564         if (cursor_width >= 1   && cursor_width <= 32)
0565             line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
0566         else if (cursor_width >= 33  && cursor_width <= 64)
0567             line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
0568         else if (cursor_width >= 65  && cursor_width <= 128)
0569             line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
0570         else if (cursor_width >= 129 && cursor_width <= 256)
0571             line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
0572     } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
0573            cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
0574         if (cursor_width >= 1   && cursor_width <= 16)
0575             line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
0576         else if (cursor_width >= 17  && cursor_width <= 32)
0577             line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
0578         else if (cursor_width >= 33  && cursor_width <= 64)
0579             line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
0580         else if (cursor_width >= 65 && cursor_width <= 128)
0581             line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
0582         else if (cursor_width >= 129 && cursor_width <= 256)
0583             line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
0584     }
0585 
0586     return line_per_chunk;
0587 }
0588 
0589 void hubp2_cursor_set_attributes(
0590         struct hubp *hubp,
0591         const struct dc_cursor_attributes *attr)
0592 {
0593     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0594     enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
0595     enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
0596             attr->width, attr->color_format);
0597 
0598     hubp->curs_attr = *attr;
0599 
0600     REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
0601             CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
0602     REG_UPDATE(CURSOR_SURFACE_ADDRESS,
0603             CURSOR_SURFACE_ADDRESS, attr->address.low_part);
0604 
0605     REG_UPDATE_2(CURSOR_SIZE,
0606             CURSOR_WIDTH, attr->width,
0607             CURSOR_HEIGHT, attr->height);
0608 
0609     REG_UPDATE_4(CURSOR_CONTROL,
0610             CURSOR_MODE, attr->color_format,
0611             CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
0612             CURSOR_PITCH, hw_pitch,
0613             CURSOR_LINES_PER_CHUNK, lpc);
0614 
0615     REG_SET_2(CURSOR_SETTINGS, 0,
0616             /* no shift of the cursor HDL schedule */
0617             CURSOR0_DST_Y_OFFSET, 0,
0618              /* used to shift the cursor chunk request deadline */
0619             CURSOR0_CHUNK_HDL_ADJUST, 3);
0620 }
0621 
0622 void hubp2_dmdata_set_attributes(
0623         struct hubp *hubp,
0624         const struct dc_dmdata_attributes *attr)
0625 {
0626     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0627 
0628     if (attr->dmdata_mode == DMDATA_HW_MODE) {
0629         /* set to HW mode */
0630         REG_UPDATE(DMDATA_CNTL,
0631                 DMDATA_MODE, 1);
0632 
0633         /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
0634         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
0635 
0636         /* toggle DMDATA_UPDATED and set repeat and size */
0637         REG_UPDATE(DMDATA_CNTL,
0638                 DMDATA_UPDATED, 0);
0639         REG_UPDATE_3(DMDATA_CNTL,
0640                 DMDATA_UPDATED, 1,
0641                 DMDATA_REPEAT, attr->dmdata_repeat,
0642                 DMDATA_SIZE, attr->dmdata_size);
0643 
0644         /* set DMDATA address */
0645         REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
0646         REG_UPDATE(DMDATA_ADDRESS_HIGH,
0647                 DMDATA_ADDRESS_HIGH, attr->address.high_part);
0648 
0649         REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
0650 
0651     } else {
0652         /* set to SW mode before loading data */
0653         REG_SET(DMDATA_CNTL, 0,
0654                 DMDATA_MODE, 0);
0655         /* toggle DMDATA_SW_UPDATED to start loading sequence */
0656         REG_UPDATE(DMDATA_SW_CNTL,
0657                 DMDATA_SW_UPDATED, 0);
0658         REG_UPDATE_3(DMDATA_SW_CNTL,
0659                 DMDATA_SW_UPDATED, 1,
0660                 DMDATA_SW_REPEAT, attr->dmdata_repeat,
0661                 DMDATA_SW_SIZE, attr->dmdata_size);
0662         /* load data into hubp dmdata buffer */
0663         hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
0664     }
0665 
0666     /* Note that DL_DELTA must be programmed if we want to use TTU mode */
0667     REG_SET_3(DMDATA_QOS_CNTL, 0,
0668             DMDATA_QOS_MODE, attr->dmdata_qos_mode,
0669             DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
0670             DMDATA_DL_DELTA, attr->dmdata_dl_delta);
0671 }
0672 
0673 void hubp2_dmdata_load(
0674         struct hubp *hubp,
0675         uint32_t dmdata_sw_size,
0676         const uint32_t *dmdata_sw_data)
0677 {
0678     int i;
0679     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0680 
0681     /* load dmdata into HUBP buffer in SW mode */
0682     for (i = 0; i < dmdata_sw_size / 4; i++)
0683         REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
0684 }
0685 
0686 bool hubp2_dmdata_status_done(struct hubp *hubp)
0687 {
0688     uint32_t status;
0689     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0690 
0691     REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
0692     return (status == 1);
0693 }
0694 
0695 bool hubp2_program_surface_flip_and_addr(
0696     struct hubp *hubp,
0697     const struct dc_plane_address *address,
0698     bool flip_immediate)
0699 {
0700     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0701 
0702     //program flip type
0703     REG_UPDATE(DCSURF_FLIP_CONTROL,
0704             SURFACE_FLIP_TYPE, flip_immediate);
0705 
0706     // Program VMID reg
0707     REG_UPDATE(VMID_SETTINGS_0,
0708             VMID, address->vmid);
0709 
0710 
0711     /* HW automatically latch rest of address register on write to
0712      * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
0713      *
0714      * program high first and then the low addr, order matters!
0715      */
0716     switch (address->type) {
0717     case PLN_ADDR_TYPE_GRAPHICS:
0718         /* DCN1.0 does not support const color
0719          * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
0720          * base on address->grph.dcc_const_color
0721          * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
0722          * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
0723          */
0724 
0725         if (address->grph.addr.quad_part == 0)
0726             break;
0727 
0728         REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
0729                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0730                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
0731 
0732         if (address->grph.meta_addr.quad_part != 0) {
0733             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0734                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0735                     address->grph.meta_addr.high_part);
0736 
0737             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0738                     PRIMARY_META_SURFACE_ADDRESS,
0739                     address->grph.meta_addr.low_part);
0740         }
0741 
0742         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0743                 PRIMARY_SURFACE_ADDRESS_HIGH,
0744                 address->grph.addr.high_part);
0745 
0746         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0747                 PRIMARY_SURFACE_ADDRESS,
0748                 address->grph.addr.low_part);
0749         break;
0750     case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
0751         if (address->video_progressive.luma_addr.quad_part == 0
0752                 || address->video_progressive.chroma_addr.quad_part == 0)
0753             break;
0754 
0755         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
0756                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0757                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
0758                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
0759                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
0760 
0761         if (address->video_progressive.luma_meta_addr.quad_part != 0) {
0762             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
0763                     PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
0764                     address->video_progressive.chroma_meta_addr.high_part);
0765 
0766             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
0767                     PRIMARY_META_SURFACE_ADDRESS_C,
0768                     address->video_progressive.chroma_meta_addr.low_part);
0769 
0770             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0771                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0772                     address->video_progressive.luma_meta_addr.high_part);
0773 
0774             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0775                     PRIMARY_META_SURFACE_ADDRESS,
0776                     address->video_progressive.luma_meta_addr.low_part);
0777         }
0778 
0779         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
0780                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
0781                 address->video_progressive.chroma_addr.high_part);
0782 
0783         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
0784                 PRIMARY_SURFACE_ADDRESS_C,
0785                 address->video_progressive.chroma_addr.low_part);
0786 
0787         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0788                 PRIMARY_SURFACE_ADDRESS_HIGH,
0789                 address->video_progressive.luma_addr.high_part);
0790 
0791         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0792                 PRIMARY_SURFACE_ADDRESS,
0793                 address->video_progressive.luma_addr.low_part);
0794         break;
0795     case PLN_ADDR_TYPE_GRPH_STEREO:
0796         if (address->grph_stereo.left_addr.quad_part == 0)
0797             break;
0798         if (address->grph_stereo.right_addr.quad_part == 0)
0799             break;
0800 
0801         REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
0802                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
0803                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
0804                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
0805                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
0806                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
0807                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
0808                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
0809                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
0810 
0811         if (address->grph_stereo.right_meta_addr.quad_part != 0) {
0812 
0813             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
0814                     SECONDARY_META_SURFACE_ADDRESS_HIGH,
0815                     address->grph_stereo.right_meta_addr.high_part);
0816 
0817             REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
0818                     SECONDARY_META_SURFACE_ADDRESS,
0819                     address->grph_stereo.right_meta_addr.low_part);
0820         }
0821         if (address->grph_stereo.left_meta_addr.quad_part != 0) {
0822 
0823             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
0824                     PRIMARY_META_SURFACE_ADDRESS_HIGH,
0825                     address->grph_stereo.left_meta_addr.high_part);
0826 
0827             REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
0828                     PRIMARY_META_SURFACE_ADDRESS,
0829                     address->grph_stereo.left_meta_addr.low_part);
0830         }
0831 
0832         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
0833                 SECONDARY_SURFACE_ADDRESS_HIGH,
0834                 address->grph_stereo.right_addr.high_part);
0835 
0836         REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
0837                 SECONDARY_SURFACE_ADDRESS,
0838                 address->grph_stereo.right_addr.low_part);
0839 
0840         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
0841                 PRIMARY_SURFACE_ADDRESS_HIGH,
0842                 address->grph_stereo.left_addr.high_part);
0843 
0844         REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
0845                 PRIMARY_SURFACE_ADDRESS,
0846                 address->grph_stereo.left_addr.low_part);
0847         break;
0848     default:
0849         BREAK_TO_DEBUGGER();
0850         break;
0851     }
0852 
0853     hubp->request_address = *address;
0854 
0855     return true;
0856 }
0857 
0858 void hubp2_enable_triplebuffer(
0859     struct hubp *hubp,
0860     bool enable)
0861 {
0862     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0863     uint32_t triple_buffer_en = 0;
0864     bool tri_buffer_en;
0865 
0866     REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
0867     tri_buffer_en = (triple_buffer_en == 1);
0868     if (tri_buffer_en != enable) {
0869         REG_UPDATE(DCSURF_FLIP_CONTROL2,
0870             SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
0871     }
0872 }
0873 
0874 bool hubp2_is_triplebuffer_enabled(
0875     struct hubp *hubp)
0876 {
0877     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0878     uint32_t triple_buffer_en = 0;
0879 
0880     REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
0881 
0882     return (bool)triple_buffer_en;
0883 }
0884 
0885 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
0886 {
0887     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0888 
0889     REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
0890 }
0891 
0892 bool hubp2_is_flip_pending(struct hubp *hubp)
0893 {
0894     uint32_t flip_pending = 0;
0895     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0896     struct dc_plane_address earliest_inuse_address;
0897 
0898     if (hubp && hubp->power_gated)
0899         return false;
0900 
0901     REG_GET(DCSURF_FLIP_CONTROL,
0902             SURFACE_FLIP_PENDING, &flip_pending);
0903 
0904     REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
0905             SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
0906 
0907     REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
0908             SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
0909 
0910     if (flip_pending)
0911         return true;
0912 
0913     if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
0914         return true;
0915 
0916     return false;
0917 }
0918 
0919 void hubp2_set_blank(struct hubp *hubp, bool blank)
0920 {
0921     hubp2_set_blank_regs(hubp, blank);
0922 
0923     if (blank) {
0924         hubp->mpcc_id = 0xf;
0925         hubp->opp_id = OPP_ID_INVALID;
0926     }
0927 }
0928 
0929 void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
0930 {
0931     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0932     uint32_t blank_en = blank ? 1 : 0;
0933 
0934     if (blank) {
0935         uint32_t reg_val = REG_READ(DCHUBP_CNTL);
0936 
0937         if (reg_val) {
0938             /* init sequence workaround: in case HUBP is
0939              * power gated, this wait would timeout.
0940              *
0941              * we just wrote reg_val to non-0, if it stay 0
0942              * it means HUBP is gated
0943              */
0944             REG_WAIT(DCHUBP_CNTL,
0945                     HUBP_NO_OUTSTANDING_REQ, 1,
0946                     1, 100000);
0947         }
0948     }
0949 
0950     REG_UPDATE_2(DCHUBP_CNTL,
0951             HUBP_BLANK_EN, blank_en,
0952             HUBP_TTU_DISABLE, 0);
0953 }
0954 
0955 void hubp2_cursor_set_position(
0956         struct hubp *hubp,
0957         const struct dc_cursor_position *pos,
0958         const struct dc_cursor_mi_param *param)
0959 {
0960     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
0961     int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
0962     int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
0963     int x_hotspot = pos->x_hotspot;
0964     int y_hotspot = pos->y_hotspot;
0965     int cursor_height = (int)hubp->curs_attr.height;
0966     int cursor_width = (int)hubp->curs_attr.width;
0967     uint32_t dst_x_offset;
0968     uint32_t cur_en = pos->enable ? 1 : 0;
0969 
0970     hubp->curs_pos = *pos;
0971 
0972     /*
0973      * Guard aganst cursor_set_position() from being called with invalid
0974      * attributes
0975      *
0976      * TODO: Look at combining cursor_set_position() and
0977      * cursor_set_attributes() into cursor_update()
0978      */
0979     if (hubp->curs_attr.address.quad_part == 0)
0980         return;
0981 
0982     // Rotated cursor width/height and hotspots tweaks for offset calculation
0983     if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
0984         swap(cursor_height, cursor_width);
0985         if (param->rotation == ROTATION_ANGLE_90) {
0986             src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
0987             src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
0988         }
0989     } else if (param->rotation == ROTATION_ANGLE_180) {
0990         src_x_offset = pos->x - param->viewport.x;
0991         src_y_offset = pos->y - param->viewport.y;
0992     }
0993 
0994     if (param->mirror) {
0995         x_hotspot = param->viewport.width - x_hotspot;
0996         src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
0997     }
0998 
0999     dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1000     dst_x_offset *= param->ref_clk_khz;
1001     dst_x_offset /= param->pixel_clk_khz;
1002 
1003     ASSERT(param->h_scale_ratio.value);
1004 
1005     if (param->h_scale_ratio.value)
1006         dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1007                 dc_fixpt_from_int(dst_x_offset),
1008                 param->h_scale_ratio));
1009 
1010     if (src_x_offset >= (int)param->viewport.width)
1011         cur_en = 0;  /* not visible beyond right edge*/
1012 
1013     if (src_x_offset + cursor_width <= 0)
1014         cur_en = 0;  /* not visible beyond left edge*/
1015 
1016     if (src_y_offset >= (int)param->viewport.height)
1017         cur_en = 0;  /* not visible beyond bottom edge*/
1018 
1019     if (src_y_offset + cursor_height <= 0)
1020         cur_en = 0;  /* not visible beyond top edge*/
1021 
1022     if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1023         hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1024 
1025     REG_UPDATE(CURSOR_CONTROL,
1026             CURSOR_ENABLE, cur_en);
1027 
1028     REG_SET_2(CURSOR_POSITION, 0,
1029             CURSOR_X_POSITION, pos->x,
1030             CURSOR_Y_POSITION, pos->y);
1031 
1032     REG_SET_2(CURSOR_HOT_SPOT, 0,
1033             CURSOR_HOT_SPOT_X, x_hotspot,
1034             CURSOR_HOT_SPOT_Y, y_hotspot);
1035 
1036     REG_SET(CURSOR_DST_OFFSET, 0,
1037             CURSOR_DST_X_OFFSET, dst_x_offset);
1038     /* TODO Handle surface pixel formats other than 4:4:4 */
1039 }
1040 
1041 void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1042 {
1043     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1044     uint32_t clk_enable = enable ? 1 : 0;
1045 
1046     REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1047 }
1048 
1049 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1050 {
1051     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1052 
1053     REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1054 }
1055 
1056 void hubp2_clear_underflow(struct hubp *hubp)
1057 {
1058     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1059 
1060     REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1061 }
1062 
1063 void hubp2_read_state_common(struct hubp *hubp)
1064 {
1065     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1066     struct dcn_hubp_state *s = &hubp2->state;
1067     struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1068     struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1069     struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1070 
1071     /* Requester */
1072     REG_GET(HUBPRET_CONTROL,
1073             DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1074     REG_GET_4(DCN_EXPANSION_MODE,
1075             DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1076             PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1077             MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1078             CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1079 
1080     REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
1081             MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
1082 
1083     REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
1084             MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
1085 
1086     /* DLG - Per hubp */
1087     REG_GET_2(BLANK_OFFSET_0,
1088         REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1089         DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1090 
1091     REG_GET(BLANK_OFFSET_1,
1092         MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1093 
1094     REG_GET(DST_DIMENSIONS,
1095         REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1096 
1097     REG_GET_2(DST_AFTER_SCALER,
1098         REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1099         DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1100 
1101     if (REG(PREFETCH_SETTINS))
1102         REG_GET_2(PREFETCH_SETTINS,
1103             DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1104             VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1105     else
1106         REG_GET_2(PREFETCH_SETTINGS,
1107             DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1108             VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1109 
1110     REG_GET_2(VBLANK_PARAMETERS_0,
1111         DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1112         DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1113 
1114     REG_GET(REF_FREQ_TO_PIX_FREQ,
1115         REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1116 
1117     /* DLG - Per luma/chroma */
1118     REG_GET(VBLANK_PARAMETERS_1,
1119         REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1120 
1121     REG_GET(VBLANK_PARAMETERS_3,
1122         REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1123 
1124     if (REG(NOM_PARAMETERS_0))
1125         REG_GET(NOM_PARAMETERS_0,
1126             DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1127 
1128     if (REG(NOM_PARAMETERS_1))
1129         REG_GET(NOM_PARAMETERS_1,
1130             REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1131 
1132     REG_GET(NOM_PARAMETERS_4,
1133         DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1134 
1135     REG_GET(NOM_PARAMETERS_5,
1136         REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1137 
1138     REG_GET_2(PER_LINE_DELIVERY_PRE,
1139         REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1140         REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1141 
1142     REG_GET_2(PER_LINE_DELIVERY,
1143         REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1144         REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1145 
1146     if (REG(PREFETCH_SETTINS_C))
1147         REG_GET(PREFETCH_SETTINS_C,
1148             VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1149     else
1150         REG_GET(PREFETCH_SETTINGS_C,
1151             VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1152 
1153     REG_GET(VBLANK_PARAMETERS_2,
1154         REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1155 
1156     REG_GET(VBLANK_PARAMETERS_4,
1157         REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1158 
1159     if (REG(NOM_PARAMETERS_2))
1160         REG_GET(NOM_PARAMETERS_2,
1161             DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1162 
1163     if (REG(NOM_PARAMETERS_3))
1164         REG_GET(NOM_PARAMETERS_3,
1165             REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1166 
1167     REG_GET(NOM_PARAMETERS_6,
1168         DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1169 
1170     REG_GET(NOM_PARAMETERS_7,
1171         REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1172 
1173     /* TTU - per hubp */
1174     REG_GET_2(DCN_TTU_QOS_WM,
1175         QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1176         QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1177 
1178     REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1179         MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1180         QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1181 
1182     /* TTU - per luma/chroma */
1183     /* Assumed surf0 is luma and 1 is chroma */
1184 
1185     REG_GET_3(DCN_SURF0_TTU_CNTL0,
1186         REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1187         QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1188         QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1189 
1190     REG_GET(DCN_SURF0_TTU_CNTL1,
1191         REFCYC_PER_REQ_DELIVERY_PRE,
1192         &ttu_attr->refcyc_per_req_delivery_pre_l);
1193 
1194     REG_GET_3(DCN_SURF1_TTU_CNTL0,
1195         REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1196         QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1197         QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1198 
1199     REG_GET(DCN_SURF1_TTU_CNTL1,
1200         REFCYC_PER_REQ_DELIVERY_PRE,
1201         &ttu_attr->refcyc_per_req_delivery_pre_c);
1202 
1203     /* Rest of hubp */
1204     REG_GET(DCSURF_SURFACE_CONFIG,
1205             SURFACE_PIXEL_FORMAT, &s->pixel_format);
1206 
1207     REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1208             SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1209 
1210     REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1211             SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1212 
1213     REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1214             PRI_VIEWPORT_WIDTH, &s->viewport_width,
1215             PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1216 
1217     REG_GET_2(DCSURF_SURFACE_CONFIG,
1218             ROTATION_ANGLE, &s->rotation_angle,
1219             H_MIRROR_EN, &s->h_mirror_en);
1220 
1221     REG_GET(DCSURF_TILING_CONFIG,
1222             SW_MODE, &s->sw_mode);
1223 
1224     REG_GET(DCSURF_SURFACE_CONTROL,
1225             PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1226 
1227     REG_GET_3(DCHUBP_CNTL,
1228             HUBP_BLANK_EN, &s->blank_en,
1229             HUBP_TTU_DISABLE, &s->ttu_disable,
1230             HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1231 
1232     REG_GET(HUBP_CLK_CNTL,
1233             HUBP_CLOCK_ENABLE, &s->clock_en);
1234 
1235     REG_GET(DCN_GLOBAL_TTU_CNTL,
1236             MIN_TTU_VBLANK, &s->min_ttu_vblank);
1237 
1238     REG_GET_2(DCN_TTU_QOS_WM,
1239             QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1240             QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1241 
1242     REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1243             PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1244 
1245     REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1246             PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1247 
1248     REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1249             PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1250 
1251     REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1252             PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1253 }
1254 
1255 void hubp2_read_state(struct hubp *hubp)
1256 {
1257     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1258     struct dcn_hubp_state *s = &hubp2->state;
1259     struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1260 
1261     hubp2_read_state_common(hubp);
1262 
1263     REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1264         CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1265         MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1266         META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1267         MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1268         DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1269         MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1270         SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1271         PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1272 
1273     REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1274         CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1275         MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1276         META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1277         MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1278         DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1279         MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1280         SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1281         PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1282 
1283 }
1284 
1285 static void hubp2_validate_dml_output(struct hubp *hubp,
1286         struct dc_context *ctx,
1287         struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1288         struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1289         struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1290 {
1291     struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1292     struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1293     struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1294     struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1295     DC_LOGGER_INIT(ctx->logger);
1296     DC_LOG_DEBUG("DML Validation | Running Validation");
1297 
1298     /* Requestor Regs */
1299     REG_GET(HUBPRET_CONTROL,
1300         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1301     REG_GET_4(DCN_EXPANSION_MODE,
1302         DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1303         PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1304         MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1305         CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1306     REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1307         CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1308         MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1309         META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1310         MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1311         DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1312         MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1313         SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1314         PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1315     REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1316         CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1317         MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1318         META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1319         MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1320         DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1321         MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1322         SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1323         PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1324 
1325     if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1326         DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1327                 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1328     if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1329         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1330                 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1331     if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1332         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1333                 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1334     if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1335         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1336                 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1337     if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1338         DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1339                 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1340 
1341     if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1342         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
1343                 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1344     if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1345         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1346                 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1347     if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1348         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1349                 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1350     if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1351         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1352                 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1353     if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1354         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1355                 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1356     if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1357         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1358                 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1359     if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1360         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
1361                 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1362     if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1363         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
1364                 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1365 
1366     if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1367         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1368                 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1369     if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1370         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1371                 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1372     if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1373         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1374                 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1375     if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1376         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1377                 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1378     if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1379         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1380                 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1381     if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1382         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1383                 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1384     if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1385         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
1386                 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1387     if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1388         DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
1389                 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1390 
1391     /* DLG - Per hubp */
1392     REG_GET_2(BLANK_OFFSET_0,
1393         REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1394         DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1395     REG_GET(BLANK_OFFSET_1,
1396         MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1397     REG_GET(DST_DIMENSIONS,
1398         REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1399     REG_GET_2(DST_AFTER_SCALER,
1400         REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1401         DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1402     REG_GET(REF_FREQ_TO_PIX_FREQ,
1403         REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1404 
1405     if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1406         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
1407                 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1408     if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1409         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
1410                 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1411     if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1412         DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
1413                 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1414     if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1415         DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
1416                 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1417     if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1418         DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
1419                 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1420     if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1421         DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
1422                 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1423     if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1424         DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
1425                 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1426 
1427     /* DLG - Per luma/chroma */
1428     REG_GET(VBLANK_PARAMETERS_1,
1429         REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1430     if (REG(NOM_PARAMETERS_0))
1431         REG_GET(NOM_PARAMETERS_0,
1432             DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1433     if (REG(NOM_PARAMETERS_1))
1434         REG_GET(NOM_PARAMETERS_1,
1435             REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1436     REG_GET(NOM_PARAMETERS_4,
1437         DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1438     REG_GET(NOM_PARAMETERS_5,
1439         REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1440     REG_GET_2(PER_LINE_DELIVERY,
1441         REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1442         REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1443     REG_GET_2(PER_LINE_DELIVERY_PRE,
1444         REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1445         REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1446     REG_GET(VBLANK_PARAMETERS_2,
1447         REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1448     if (REG(NOM_PARAMETERS_2))
1449         REG_GET(NOM_PARAMETERS_2,
1450             DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1451     if (REG(NOM_PARAMETERS_3))
1452         REG_GET(NOM_PARAMETERS_3,
1453             REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1454     REG_GET(NOM_PARAMETERS_6,
1455         DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1456     REG_GET(NOM_PARAMETERS_7,
1457         REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1458     REG_GET(VBLANK_PARAMETERS_3,
1459             REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1460     REG_GET(VBLANK_PARAMETERS_4,
1461             REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1462 
1463     if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1464         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
1465                 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1466     if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1467         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
1468                 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1469     if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1470         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
1471                 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1472     if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1473         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
1474                 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1475     if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1476         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
1477                 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1478     if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1479         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
1480                 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1481     if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1482         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
1483                 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1484     if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1485         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
1486                 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1487     if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1488         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
1489                 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1490     if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1491         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
1492                 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1493     if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1494         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
1495                 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1496     if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1497         DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
1498                 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1499     if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1500         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
1501                 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1502     if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1503         DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
1504                 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1505     if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1506         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
1507                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1508     if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1509         DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
1510                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1511 
1512     /* TTU - per hubp */
1513     REG_GET_2(DCN_TTU_QOS_WM,
1514         QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1515         QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1516 
1517     if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1518         DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
1519                 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1520     if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1521         DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
1522                 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1523 
1524     /* TTU - per luma/chroma */
1525     /* Assumed surf0 is luma and 1 is chroma */
1526     REG_GET_3(DCN_SURF0_TTU_CNTL0,
1527         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1528         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1529         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1530     REG_GET_3(DCN_SURF1_TTU_CNTL0,
1531         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1532         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1533         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1534     REG_GET_3(DCN_CUR0_TTU_CNTL0,
1535         REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1536         QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1537         QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1538     REG_GET(FLIP_PARAMETERS_1,
1539         REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1540     REG_GET(DCN_CUR0_TTU_CNTL1,
1541             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1542     REG_GET(DCN_CUR1_TTU_CNTL1,
1543             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1544     REG_GET(DCN_SURF0_TTU_CNTL1,
1545             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1546     REG_GET(DCN_SURF1_TTU_CNTL1,
1547             REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1548 
1549     if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1550         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1551                 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1552     if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1553         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1554                 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1555     if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1556         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1557                 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1558     if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1559         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1560                 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1561     if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1562         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1563                 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1564     if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1565         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1566                 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1567     if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1568         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1569                 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1570     if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1571         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1572                 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1573     if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1574         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1575                 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1576     if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1577         DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
1578                 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1579     if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1580         DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1581                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1582     if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1583         DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1584                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1585     if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1586         DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1587                 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1588     if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1589         DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1590                 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1591 }
1592 
1593 static struct hubp_funcs dcn20_hubp_funcs = {
1594     .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1595     .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1596     .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1597     .hubp_program_surface_config = hubp2_program_surface_config,
1598     .hubp_is_flip_pending = hubp2_is_flip_pending,
1599     .hubp_setup = hubp2_setup,
1600     .hubp_setup_interdependent = hubp2_setup_interdependent,
1601     .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1602     .set_blank = hubp2_set_blank,
1603     .set_blank_regs = hubp2_set_blank_regs,
1604     .dcc_control = hubp2_dcc_control,
1605     .mem_program_viewport = min_set_viewport,
1606     .set_cursor_attributes  = hubp2_cursor_set_attributes,
1607     .set_cursor_position    = hubp2_cursor_set_position,
1608     .hubp_clk_cntl = hubp2_clk_cntl,
1609     .hubp_vtg_sel = hubp2_vtg_sel,
1610     .dmdata_set_attributes = hubp2_dmdata_set_attributes,
1611     .dmdata_load = hubp2_dmdata_load,
1612     .dmdata_status_done = hubp2_dmdata_status_done,
1613     .hubp_read_state = hubp2_read_state,
1614     .hubp_clear_underflow = hubp2_clear_underflow,
1615     .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1616     .hubp_init = hubp1_init,
1617     .validate_dml_output = hubp2_validate_dml_output,
1618     .hubp_in_blank = hubp1_in_blank,
1619     .hubp_soft_reset = hubp1_soft_reset,
1620     .hubp_set_flip_int = hubp1_set_flip_int,
1621 };
1622 
1623 
1624 bool hubp2_construct(
1625     struct dcn20_hubp *hubp2,
1626     struct dc_context *ctx,
1627     uint32_t inst,
1628     const struct dcn_hubp2_registers *hubp_regs,
1629     const struct dcn_hubp2_shift *hubp_shift,
1630     const struct dcn_hubp2_mask *hubp_mask)
1631 {
1632     hubp2->base.funcs = &dcn20_hubp_funcs;
1633     hubp2->base.ctx = ctx;
1634     hubp2->hubp_regs = hubp_regs;
1635     hubp2->hubp_shift = hubp_shift;
1636     hubp2->hubp_mask = hubp_mask;
1637     hubp2->base.inst = inst;
1638     hubp2->base.opp_id = OPP_ID_INVALID;
1639     hubp2->base.mpcc_id = 0xf;
1640 
1641     return true;
1642 }
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