dc/dcn20/dcn20_dwb.h

0001 /* Copyright 2012-17 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 #ifndef __DC_DWBC_DCN20_H__
0025 #define __DC_DWBC_DCN20_H__
0026
0027 #define TO_DCN20_DWBC(dwbc_base) \
0028     container_of(dwbc_base, struct dcn20_dwbc, base)
0029
0030 /* DCN */
0031 #define BASE_INNER(seg) \
0032     DCE_BASE__INST0_SEG ## seg
0033
0034 #define BASE(seg) \
0035     BASE_INNER(seg)
0036
0037 #define SR(reg_name)\
0038         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
0039                     mm ## reg_name
0040
0041 #define SRI(reg_name, block, id)\
0042     .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0043                     mm ## block ## id ## _ ## reg_name
0044
0045 #define SRI2(reg_name, block, id)\
0046     .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
0047                     mm ## reg_name
0048
0049 #define SRII(reg_name, block, id)\
0050     .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0051                     mm ## block ## id ## _ ## reg_name
0052
0053 #define SF(reg_name, field_name, post_fix)\
0054     .field_name = reg_name ## __ ## field_name ## post_fix
0055
0056
0057 #define DWBC_COMMON_REG_LIST_DCN2_0(inst) \
0058     SRI2(WB_ENABLE, CNV, inst),\
0059     SRI2(WB_EC_CONFIG, CNV, inst),\
0060     SRI2(CNV_MODE, CNV, inst),\
0061     SRI2(CNV_WINDOW_START, CNV, inst),\
0062     SRI2(CNV_WINDOW_SIZE, CNV, inst),\
0063     SRI2(CNV_UPDATE, CNV, inst),\
0064     SRI2(CNV_SOURCE_SIZE, CNV, inst),\
0065     SRI2(CNV_TEST_CNTL, CNV, inst),\
0066     SRI2(CNV_TEST_CRC_RED, CNV, inst),\
0067     SRI2(CNV_TEST_CRC_GREEN, CNV, inst),\
0068     SRI2(CNV_TEST_CRC_BLUE, CNV, inst),\
0069     SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
0070     SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
0071     SRI2(WBSCL_MODE, WBSCL, inst),\
0072     SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
0073     SRI2(WBSCL_DEST_SIZE, WBSCL, inst),\
0074     SRI2(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL, inst),\
0075     SRI2(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL, inst),\
0076     SRI2(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL, inst),\
0077     SRI2(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL, inst),\
0078     SRI2(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL, inst),\
0079     SRI2(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL, inst),\
0080     SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\
0081     SRI2(WBSCL_OVERFLOW_STATUS, WBSCL, inst),\
0082     SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
0083     SRI2(WBSCL_TEST_CNTL, WBSCL, inst),\
0084     SRI2(WBSCL_TEST_CRC_RED, WBSCL, inst),\
0085     SRI2(WBSCL_TEST_CRC_GREEN, WBSCL, inst),\
0086     SRI2(WBSCL_TEST_CRC_BLUE, WBSCL, inst),\
0087     SRI2(WBSCL_BACKPRESSURE_CNT_EN, WBSCL, inst),\
0088     SRI2(WB_MCIF_BACKPRESSURE_CNT, WBSCL, inst),\
0089     SRI2(WBSCL_CLAMP_Y_RGB, WBSCL, inst),\
0090     SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\
0091     SRI2(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL, inst),\
0092     SRI2(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL, inst),\
0093     SRI2(WBSCL_DEBUG, WBSCL, inst),\
0094     SRI2(WBSCL_TEST_DEBUG_INDEX, WBSCL, inst),\
0095     SRI2(WBSCL_TEST_DEBUG_DATA, WBSCL, inst),\
0096     SRI2(WB_DEBUG_CTRL, CNV, inst),\
0097     SRI2(WB_DBG_MODE, CNV, inst),\
0098     SRI2(WB_HW_DEBUG, CNV, inst),\
0099     SRI2(CNV_TEST_DEBUG_INDEX, CNV, inst),\
0100     SRI2(CNV_TEST_DEBUG_DATA, CNV, inst),\
0101     SRI2(WB_SOFT_RESET, CNV, inst),\
0102     SRI2(WB_WARM_UP_MODE_CTL1, CNV, inst),\
0103     SRI2(WB_WARM_UP_MODE_CTL2, CNV, inst)
0104
0105 #define DWBC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
0106     SF(WB_ENABLE, WB_ENABLE, mask_sh),\
0107     SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
0108     SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
0109     SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
0110     SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
0111     SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
0112     SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
0113     SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
0114     SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
0115     SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
0116     SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
0117     SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
0118     SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
0119     SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
0120     SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
0121     SF(CNV_MODE, CNV_FRAME_CAPTURE_RATE, mask_sh),\
0122     SF(CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
0123     SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
0124     SF(CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
0125     SF(CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
0126     SF(CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
0127     SF(CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
0128     SF(CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
0129     SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
0130     SF(CNV_MODE, CNV_FRAME_CAPTURE_EN_CURRENT, mask_sh),\
0131     SF(CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
0132     SF(CNV_WINDOW_START, CNV_WINDOW_START_X, mask_sh),\
0133     SF(CNV_WINDOW_START, CNV_WINDOW_START_Y, mask_sh),\
0134     SF(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, mask_sh),\
0135     SF(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, mask_sh),\
0136     SF(CNV_UPDATE, CNV_UPDATE_PENDING, mask_sh),\
0137     SF(CNV_UPDATE, CNV_UPDATE_TAKEN, mask_sh),\
0138     SF(CNV_UPDATE, CNV_UPDATE_LOCK, mask_sh),\
0139     SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
0140     SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
0141     SF(CNV_TEST_CNTL, CNV_TEST_CRC_EN, mask_sh),\
0142     SF(CNV_TEST_CNTL, CNV_TEST_CRC_CONT_EN, mask_sh),\
0143     SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_RED_MASK, mask_sh),\
0144     SF(CNV_TEST_CRC_RED, CNV_TEST_CRC_SIG_RED, mask_sh),\
0145     SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_GREEN_MASK, mask_sh),\
0146     SF(CNV_TEST_CRC_GREEN, CNV_TEST_CRC_SIG_GREEN, mask_sh),\
0147     SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_BLUE_MASK, mask_sh),\
0148     SF(CNV_TEST_CRC_BLUE, CNV_TEST_CRC_SIG_BLUE, mask_sh),\
0149     SF(WB_DEBUG_CTRL, WB_DEBUG_EN, mask_sh),\
0150     SF(WB_DEBUG_CTRL, WB_DEBUG_SEL, mask_sh),\
0151     SF(WB_DBG_MODE, WB_DBG_MODE_EN, mask_sh),\
0152     SF(WB_DBG_MODE, WB_DBG_DIN_FMT, mask_sh),\
0153     SF(WB_DBG_MODE, WB_DBG_36MODE, mask_sh),\
0154     SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
0155     SF(WB_DBG_MODE, WB_DBG_PXLRATE_ERROR, mask_sh),\
0156     SF(WB_DBG_MODE, WB_DBG_SOURCE_WIDTH, mask_sh),\
0157     SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
0158     SF(WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
0159     SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_INDEX, mask_sh),\
0160     SF(CNV_TEST_DEBUG_INDEX, CNV_TEST_DEBUG_WRITE_EN, mask_sh),\
0161     SF(CNV_TEST_DEBUG_DATA, CNV_TEST_DEBUG_DATA, mask_sh),\
0162     SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
0163     SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
0164     SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
0165     SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
0166     SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
0167     SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
0168     SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
0169     SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
0170     SF(WBSCL_MODE, WBSCL_OUT_BIT_DEPTH, mask_sh),\
0171     SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
0172     SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
0173     SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
0174     SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
0175     SF(WBSCL_DEST_SIZE, WBSCL_DEST_HEIGHT, mask_sh),\
0176     SF(WBSCL_DEST_SIZE, WBSCL_DEST_WIDTH, mask_sh),\
0177     SF(WBSCL_HORZ_FILTER_SCALE_RATIO, WBSCL_H_SCALE_RATIO, mask_sh),\
0178     SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_FRAC_Y_RGB, mask_sh),\
0179     SF(WBSCL_HORZ_FILTER_INIT_Y_RGB, WBSCL_H_INIT_INT_Y_RGB, mask_sh),\
0180     SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, mask_sh),\
0181     SF(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_INT_CBCR, mask_sh),\
0182     SF(WBSCL_VERT_FILTER_SCALE_RATIO, WBSCL_V_SCALE_RATIO, mask_sh),\
0183     SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_FRAC_Y_RGB, mask_sh),\
0184     SF(WBSCL_VERT_FILTER_INIT_Y_RGB, WBSCL_V_INIT_INT_Y_RGB, mask_sh),\
0185     SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_FRAC_CBCR, mask_sh),\
0186     SF(WBSCL_VERT_FILTER_INIT_CBCR, WBSCL_V_INIT_INT_CBCR, mask_sh),\
0187     SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\
0188     SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\
0189     SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_FLAG, mask_sh),\
0190     SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_ACK, mask_sh),\
0191     SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_MASK, mask_sh),\
0192     SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_STATUS, mask_sh),\
0193     SF(WBSCL_OVERFLOW_STATUS, WBSCL_DATA_OVERFLOW_INT_TYPE, mask_sh),\
0194     SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
0195     SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
0196     SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
0197     SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
0198     SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
0199     SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_EN, mask_sh),\
0200     SF(WBSCL_TEST_CNTL, WBSCL_TEST_CRC_CONT_EN, mask_sh),\
0201     SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_RED_MASK, mask_sh),\
0202     SF(WBSCL_TEST_CRC_RED, WBSCL_TEST_CRC_SIG_RED, mask_sh),\
0203     SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_GREEN_MASK, mask_sh),\
0204     SF(WBSCL_TEST_CRC_GREEN, WBSCL_TEST_CRC_SIG_GREEN, mask_sh),\
0205     SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_BLUE_MASK, mask_sh),\
0206     SF(WBSCL_TEST_CRC_BLUE, WBSCL_TEST_CRC_SIG_BLUE, mask_sh),\
0207     SF(WBSCL_BACKPRESSURE_CNT_EN, WBSCL_BACKPRESSURE_CNT_EN, mask_sh),\
0208     SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_Y_MAX_BACKPRESSURE, mask_sh),\
0209     SF(WB_MCIF_BACKPRESSURE_CNT, WB_MCIF_C_MAX_BACKPRESSURE, mask_sh),\
0210     SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_UPPER_Y_RGB, mask_sh),\
0211     SF(WBSCL_CLAMP_Y_RGB, WBSCL_CLAMP_LOWER_Y_RGB, mask_sh),\
0212     SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\
0213     SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\
0214     SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_OUTSIDE_PIX_STRATEGY, mask_sh),\
0215     SF(WBSCL_OUTSIDE_PIX_STRATEGY, WBSCL_BLACK_COLOR_G_Y, mask_sh),\
0216     SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_B_CB, mask_sh),\
0217     SF(WBSCL_OUTSIDE_PIX_STRATEGY_CBCR, WBSCL_BLACK_COLOR_R_CR, mask_sh),\
0218     SF(WBSCL_DEBUG, WBSCL_DEBUG, mask_sh),\
0219     SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_INDEX, mask_sh),\
0220     SF(WBSCL_TEST_DEBUG_INDEX, WBSCL_TEST_DEBUG_WRITE_EN, mask_sh),\
0221     SF(WBSCL_TEST_DEBUG_DATA, WBSCL_TEST_DEBUG_DATA, mask_sh),\
0222     SF(WB_WARM_UP_MODE_CTL1, WIDTH_WARMUP, mask_sh),\
0223     SF(WB_WARM_UP_MODE_CTL1, HEIGHT_WARMUP, mask_sh),\
0224     SF(WB_WARM_UP_MODE_CTL1, GMC_WARM_UP_ENABLE, mask_sh),\
0225     SF(WB_WARM_UP_MODE_CTL2, DATA_VALUE_WARMUP, mask_sh),\
0226     SF(WB_WARM_UP_MODE_CTL2, MODE_WARMUP, mask_sh),\
0227     SF(WB_WARM_UP_MODE_CTL2, DATA_DEPTH_WARMUP, mask_sh)
0228
0229 #define DWBC_REG_FIELD_LIST_DCN2_0(type) \
0230     type WB_ENABLE;\
0231     type DISPCLK_R_WB_GATE_DIS;\
0232     type DISPCLK_G_WB_GATE_DIS;\
0233     type DISPCLK_G_WBSCL_GATE_DIS;\
0234     type WB_TEST_CLK_SEL;\
0235     type WB_LB_LS_DIS;\
0236     type WB_LB_SD_DIS;\
0237     type WB_LUT_LS_DIS;\
0238     type WBSCL_LB_MEM_PWR_MODE_SEL;\
0239     type WBSCL_LB_MEM_PWR_DIS;\
0240     type WBSCL_LB_MEM_PWR_FORCE;\
0241     type WBSCL_LB_MEM_PWR_STATE;\
0242     type WB_RAM_PW_SAVE_MODE;\
0243     type WBSCL_LUT_MEM_PWR_STATE;\
0244     type CNV_OUT_BPC;\
0245     type CNV_FRAME_CAPTURE_RATE;\
0246     type CNV_WINDOW_CROP_EN;\
0247     type CNV_STEREO_TYPE;\
0248     type CNV_INTERLACED_MODE;\
0249     type CNV_EYE_SELECTION;\
0250     type CNV_STEREO_POLARITY;\
0251     type CNV_INTERLACED_FIELD_ORDER;\
0252     type CNV_STEREO_SPLIT;\
0253     type CNV_NEW_CONTENT;\
0254     type CNV_FRAME_CAPTURE_EN_CURRENT;\
0255     type CNV_FRAME_CAPTURE_EN;\
0256     type CNV_WINDOW_START_X;\
0257     type CNV_WINDOW_START_Y;\
0258     type CNV_WINDOW_WIDTH;\
0259     type CNV_WINDOW_HEIGHT;\
0260     type CNV_UPDATE_PENDING;\
0261     type CNV_UPDATE_TAKEN;\
0262     type CNV_UPDATE_LOCK;\
0263     type CNV_SOURCE_WIDTH;\
0264     type CNV_SOURCE_HEIGHT;\
0265     type CNV_TEST_CRC_EN;\
0266     type CNV_TEST_CRC_CONT_EN;\
0267     type CNV_TEST_CRC_RED_MASK;\
0268     type CNV_TEST_CRC_SIG_RED;\
0269     type CNV_TEST_CRC_GREEN_MASK;\
0270     type CNV_TEST_CRC_SIG_GREEN;\
0271     type CNV_TEST_CRC_BLUE_MASK;\
0272     type CNV_TEST_CRC_SIG_BLUE;\
0273     type WB_DEBUG_EN;\
0274     type WB_DEBUG_SEL;\
0275     type WB_DBG_MODE_EN;\
0276     type WB_DBG_DIN_FMT;\
0277     type WB_DBG_36MODE;\
0278     type WB_DBG_CMAP;\
0279     type WB_DBG_PXLRATE_ERROR;\
0280     type WB_DBG_SOURCE_WIDTH;\
0281     type WB_HW_DEBUG;\
0282     type CNV_TEST_DEBUG_INDEX;\
0283     type CNV_TEST_DEBUG_WRITE_EN;\
0284     type CNV_TEST_DEBUG_DATA;\
0285     type WB_SOFT_RESET;\
0286     type WBSCL_COEF_RAM_TAP_PAIR_IDX;\
0287     type WBSCL_COEF_RAM_PHASE;\
0288     type WBSCL_COEF_RAM_FILTER_TYPE;\
0289     type WBSCL_COEF_RAM_SEL;\
0290     type WBSCL_COEF_RAM_SEL_CURRENT;\
0291     type WBSCL_COEF_RAM_RD_SEL;\
0292     type WBSCL_COEF_RAM_EVEN_TAP_COEF;\
0293     type WBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\
0294     type WBSCL_COEF_RAM_ODD_TAP_COEF;\
0295     type WBSCL_COEF_RAM_ODD_TAP_COEF_EN;\
0296     type WBSCL_MODE;\
0297     type WBSCL_OUT_BIT_DEPTH;\
0298     type WBSCL_V_NUM_OF_TAPS_Y_RGB;\
0299     type WBSCL_V_NUM_OF_TAPS_CBCR;\
0300     type WBSCL_H_NUM_OF_TAPS_Y_RGB;\
0301     type WBSCL_H_NUM_OF_TAPS_CBCR;\
0302     type WBSCL_DEST_HEIGHT;\
0303     type WBSCL_DEST_WIDTH;\
0304     type WBSCL_H_SCALE_RATIO;\
0305     type WBSCL_H_INIT_FRAC_Y_RGB;\
0306     type WBSCL_H_INIT_INT_Y_RGB;\
0307     type WBSCL_H_INIT_FRAC_CBCR;\
0308     type WBSCL_H_INIT_INT_CBCR;\
0309     type WBSCL_V_SCALE_RATIO;\
0310     type WBSCL_V_INIT_FRAC_Y_RGB;\
0311     type WBSCL_V_INIT_INT_Y_RGB;\
0312     type WBSCL_V_INIT_FRAC_CBCR;\
0313     type WBSCL_V_INIT_INT_CBCR;\
0314     type WBSCL_ROUND_OFFSET_Y_RGB;\
0315     type WBSCL_ROUND_OFFSET_CBCR;\
0316     type WBSCL_DATA_OVERFLOW_FLAG;\
0317     type WBSCL_DATA_OVERFLOW_ACK;\
0318     type WBSCL_DATA_OVERFLOW_MASK;\
0319     type WBSCL_DATA_OVERFLOW_INT_STATUS;\
0320     type WBSCL_DATA_OVERFLOW_INT_TYPE;\
0321     type WBSCL_HOST_CONFLICT_FLAG;\
0322     type WBSCL_HOST_CONFLICT_ACK;\
0323     type WBSCL_HOST_CONFLICT_MASK;\
0324     type WBSCL_HOST_CONFLICT_INT_STATUS;\
0325     type WBSCL_HOST_CONFLICT_INT_TYPE;\
0326     type WBSCL_TEST_CRC_EN;\
0327     type WBSCL_TEST_CRC_CONT_EN;\
0328     type WBSCL_TEST_CRC_RED_MASK;\
0329     type WBSCL_TEST_CRC_SIG_RED;\
0330     type WBSCL_TEST_CRC_GREEN_MASK;\
0331     type WBSCL_TEST_CRC_SIG_GREEN;\
0332     type WBSCL_TEST_CRC_BLUE_MASK;\
0333     type WBSCL_TEST_CRC_SIG_BLUE;\
0334     type WBSCL_BACKPRESSURE_CNT_EN;\
0335     type WB_MCIF_Y_MAX_BACKPRESSURE;\
0336     type WB_MCIF_C_MAX_BACKPRESSURE;\
0337     type WBSCL_CLAMP_UPPER_Y_RGB;\
0338     type WBSCL_CLAMP_LOWER_Y_RGB;\
0339     type WBSCL_CLAMP_UPPER_CBCR;\
0340     type WBSCL_CLAMP_LOWER_CBCR;\
0341     type WBSCL_OUTSIDE_PIX_STRATEGY;\
0342     type WBSCL_BLACK_COLOR_G_Y;\
0343     type WBSCL_BLACK_COLOR_B_CB;\
0344     type WBSCL_BLACK_COLOR_R_CR;\
0345     type WBSCL_DEBUG;\
0346     type WBSCL_TEST_DEBUG_INDEX;\
0347     type WBSCL_TEST_DEBUG_WRITE_EN;\
0348     type WBSCL_TEST_DEBUG_DATA;\
0349     type WIDTH_WARMUP;\
0350     type HEIGHT_WARMUP;\
0351     type GMC_WARM_UP_ENABLE;\
0352     type DATA_VALUE_WARMUP;\
0353     type MODE_WARMUP;\
0354     type DATA_DEPTH_WARMUP; \
0355
0356 struct dcn20_dwbc_registers {
0357     /* DCN2.0 */
0358     uint32_t WB_ENABLE;
0359     uint32_t WB_EC_CONFIG;
0360     uint32_t CNV_MODE;
0361     uint32_t CNV_WINDOW_START;
0362     uint32_t CNV_WINDOW_SIZE;
0363     uint32_t CNV_UPDATE;
0364     uint32_t CNV_SOURCE_SIZE;
0365     uint32_t CNV_TEST_CNTL;
0366     uint32_t CNV_TEST_CRC_RED;
0367     uint32_t CNV_TEST_CRC_GREEN;
0368     uint32_t CNV_TEST_CRC_BLUE;
0369     uint32_t WB_DEBUG_CTRL;
0370     uint32_t WB_DBG_MODE;
0371     uint32_t WB_HW_DEBUG;
0372     uint32_t CNV_TEST_DEBUG_INDEX;
0373     uint32_t CNV_TEST_DEBUG_DATA;
0374     uint32_t WB_SOFT_RESET;
0375     uint32_t WBSCL_COEF_RAM_SELECT;
0376     uint32_t WBSCL_COEF_RAM_TAP_DATA;
0377     uint32_t WBSCL_MODE;
0378     uint32_t WBSCL_TAP_CONTROL;
0379     uint32_t WBSCL_DEST_SIZE;
0380     uint32_t WBSCL_HORZ_FILTER_SCALE_RATIO;
0381     uint32_t WBSCL_HORZ_FILTER_INIT_Y_RGB;
0382     uint32_t WBSCL_HORZ_FILTER_INIT_CBCR;
0383     uint32_t WBSCL_VERT_FILTER_SCALE_RATIO;
0384     uint32_t WBSCL_VERT_FILTER_INIT_Y_RGB;
0385     uint32_t WBSCL_VERT_FILTER_INIT_CBCR;
0386     uint32_t WBSCL_ROUND_OFFSET;
0387     uint32_t WBSCL_OVERFLOW_STATUS;
0388     uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;
0389     uint32_t WBSCL_TEST_CNTL;
0390     uint32_t WBSCL_TEST_CRC_RED;
0391     uint32_t WBSCL_TEST_CRC_GREEN;
0392     uint32_t WBSCL_TEST_CRC_BLUE;
0393     uint32_t WBSCL_BACKPRESSURE_CNT_EN;
0394     uint32_t WB_MCIF_BACKPRESSURE_CNT;
0395     uint32_t WBSCL_CLAMP_Y_RGB;
0396     uint32_t WBSCL_CLAMP_CBCR;
0397     uint32_t WBSCL_OUTSIDE_PIX_STRATEGY;
0398     uint32_t WBSCL_OUTSIDE_PIX_STRATEGY_CBCR;
0399     uint32_t WBSCL_DEBUG;
0400     uint32_t WBSCL_TEST_DEBUG_INDEX;
0401     uint32_t WBSCL_TEST_DEBUG_DATA;
0402     uint32_t WB_WARM_UP_MODE_CTL1;
0403     uint32_t WB_WARM_UP_MODE_CTL2;
0404 };
0405
0406
0407 struct dcn20_dwbc_mask {
0408     DWBC_REG_FIELD_LIST_DCN2_0(uint32_t)
0409 };
0410
0411 struct dcn20_dwbc_shift {
0412     DWBC_REG_FIELD_LIST_DCN2_0(uint8_t)
0413 };
0414
0415 struct dcn20_dwbc {
0416     struct dwbc base;
0417     const struct dcn20_dwbc_registers *dwbc_regs;
0418     const struct dcn20_dwbc_shift *dwbc_shift;
0419     const struct dcn20_dwbc_mask *dwbc_mask;
0420 };
0421
0422 void dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20,
0423     struct dc_context *ctx,
0424     const struct dcn20_dwbc_registers *dwbc_regs,
0425     const struct dcn20_dwbc_shift *dwbc_shift,
0426     const struct dcn20_dwbc_mask *dwbc_mask,
0427     int inst);
0428
0429 bool dwb2_disable(struct dwbc *dwbc);
0430
0431 bool dwb2_is_enabled(struct dwbc *dwbc);
0432
0433 void dwb2_set_stereo(struct dwbc *dwbc,
0434     struct dwb_stereo_params *stereo_params);
0435
0436 void dwb2_set_new_content(struct dwbc *dwbc,
0437     bool is_new_content);
0438
0439 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
0440     struct dc_dwb_params *params);
0441
0442 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
0443
0444 bool dwb_program_vert_scalar(struct dcn20_dwbc *dwbc20,
0445     uint32_t src_height,
0446     uint32_t dest_height,
0447     struct scaling_taps num_taps,
0448     enum dwb_subsample_position subsample_position);
0449
0450 bool dwb_program_horz_scalar(struct dcn20_dwbc *dwbc20,
0451     uint32_t src_width,
0452     uint32_t dest_width,
0453     struct scaling_taps num_taps);
0454
0455
0456 #endif
0457
0458