Back to home page

OSCL-LXR
 
 

     

0001 /* Copyright 2017 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 #ifndef __DCN20_DSC_H__
0025 #define __DCN20_DSC_H__
0026 
0027 #include "dsc.h"
0028 #include "dsc/dscc_types.h"
0029 #include <drm/display/drm_dsc.h>
0030 
0031 #define TO_DCN20_DSC(dsc)\
0032     container_of(dsc, struct dcn20_dsc, base)
0033 
0034 #define DSC_REG_LIST_DCN20(id) \
0035     SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
0036     SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\
0037     SRI(DSCC_CONFIG0, DSCC, id),\
0038     SRI(DSCC_CONFIG1, DSCC, id),\
0039     SRI(DSCC_STATUS, DSCC, id),\
0040     SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\
0041     SRI(DSCC_PPS_CONFIG0, DSCC, id),\
0042     SRI(DSCC_PPS_CONFIG1, DSCC, id),\
0043     SRI(DSCC_PPS_CONFIG2, DSCC, id),\
0044     SRI(DSCC_PPS_CONFIG3, DSCC, id),\
0045     SRI(DSCC_PPS_CONFIG4, DSCC, id),\
0046     SRI(DSCC_PPS_CONFIG5, DSCC, id),\
0047     SRI(DSCC_PPS_CONFIG6, DSCC, id),\
0048     SRI(DSCC_PPS_CONFIG7, DSCC, id),\
0049     SRI(DSCC_PPS_CONFIG8, DSCC, id),\
0050     SRI(DSCC_PPS_CONFIG9, DSCC, id),\
0051     SRI(DSCC_PPS_CONFIG10, DSCC, id),\
0052     SRI(DSCC_PPS_CONFIG11, DSCC, id),\
0053     SRI(DSCC_PPS_CONFIG12, DSCC, id),\
0054     SRI(DSCC_PPS_CONFIG13, DSCC, id),\
0055     SRI(DSCC_PPS_CONFIG14, DSCC, id),\
0056     SRI(DSCC_PPS_CONFIG15, DSCC, id),\
0057     SRI(DSCC_PPS_CONFIG16, DSCC, id),\
0058     SRI(DSCC_PPS_CONFIG17, DSCC, id),\
0059     SRI(DSCC_PPS_CONFIG18, DSCC, id),\
0060     SRI(DSCC_PPS_CONFIG19, DSCC, id),\
0061     SRI(DSCC_PPS_CONFIG20, DSCC, id),\
0062     SRI(DSCC_PPS_CONFIG21, DSCC, id),\
0063     SRI(DSCC_PPS_CONFIG22, DSCC, id),\
0064     SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\
0065     SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\
0066     SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\
0067     SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\
0068     SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\
0069     SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\
0070     SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\
0071     SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\
0072     SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\
0073     SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
0074     SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
0075     SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
0076     SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
0077     SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
0078     SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
0079     SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
0080     SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
0081     SRI(DSCCIF_CONFIG0, DSCCIF, id),\
0082     SRI(DSCCIF_CONFIG1, DSCCIF, id),\
0083     SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
0084 
0085 
0086 #define DSC_SF(reg_name, field_name, post_fix)\
0087     .field_name = reg_name ## __ ## field_name ## post_fix
0088 
0089 //Used in resolving the corner case with duplicate field name
0090 #define DSC2_SF(reg_name, field_name, post_fix)\
0091     .field_name = reg_name ## _ ## field_name ## post_fix
0092 
0093 #define DSC_REG_LIST_SH_MASK_DCN20(mask_sh)\
0094     DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
0095     DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
0096     DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
0097     DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
0098     DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
0099     DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
0100     DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
0101     DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
0102     DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
0103     /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
0104     DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
0105     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
0106     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
0107     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
0108     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
0109     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
0110     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
0111     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
0112     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
0113     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
0114     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
0115     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
0116     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
0117     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0118     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0119     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0120     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0121     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
0122     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
0123     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
0124     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
0125     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0126     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0127     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0128     DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
0129     DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
0130     DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
0131     DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
0132     DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
0133     DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
0134     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
0135     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
0136     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
0137     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
0138     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
0139     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
0140     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
0141     DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
0142     DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
0143     DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
0144     DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
0145     DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
0146     DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
0147     DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
0148     DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
0149     DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
0150     DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
0151     DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
0152     DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
0153     DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
0154     DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
0155     DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
0156     DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
0157     DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
0158     DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
0159     DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \
0160     DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
0161     DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
0162     DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
0163     DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
0164     DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
0165     DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
0166     DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
0167     DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
0168     DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
0169     DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
0170     DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
0171     DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
0172     DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
0173     DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
0174     DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
0175     DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
0176     DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
0177     DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
0178     DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
0179     DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
0180     DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
0181     DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
0182     DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
0183     DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
0184     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
0185     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
0186     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
0187     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
0188     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
0189     DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
0190     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
0191     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
0192     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
0193     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
0194     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
0195     DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
0196     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
0197     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
0198     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
0199     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
0200     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
0201     DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
0202     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
0203     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
0204     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
0205     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
0206     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
0207     DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
0208     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
0209     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
0210     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
0211     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
0212     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
0213     DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
0214     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
0215     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
0216     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
0217     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
0218     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
0219     DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
0220     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
0221     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
0222     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
0223     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
0224     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
0225     DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
0226     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
0227     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \
0228     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \
0229     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \
0230     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \
0231     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \
0232     DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \
0233     DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
0234     DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
0235     DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
0236     DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
0237     DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
0238     DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
0239     DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
0240     DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
0241     DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
0242     DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
0243     DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
0244     DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
0245     DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
0246     DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
0247     DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
0248     DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
0249     DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
0250     DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
0251     DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
0252     DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
0253     DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
0254     DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
0255     DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
0256     DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \
0257     DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \
0258     DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
0259     DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)
0260 
0261 
0262 
0263 #define DSC_FIELD_LIST_DCN20(type)\
0264     type DSC_CLOCK_EN; \
0265     type DSC_DISPCLK_R_GATE_DIS; \
0266     type DSC_DSCCLK_R_GATE_DIS; \
0267     type DSC_DBG_EN; \
0268     type DSC_TEST_CLOCK_MUX_SEL; \
0269     type ICH_RESET_AT_END_OF_LINE; \
0270     type NUMBER_OF_SLICES_PER_LINE; \
0271     type ALTERNATE_ICH_ENCODING_EN; \
0272     type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
0273     type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
0274     /*type DSCC_DISABLE_ICH;*/ \
0275     type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
0276     type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
0277     type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
0278     type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED; \
0279     type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED; \
0280     type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED; \
0281     type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED; \
0282     type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED; \
0283     type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED; \
0284     type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED; \
0285     type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED; \
0286     type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED; \
0287     type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED; \
0288     type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN; \
0289     type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN; \
0290     type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN; \
0291     type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN; \
0292     type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN; \
0293     type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN; \
0294     type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN; \
0295     type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN; \
0296     type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN; \
0297     type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN; \
0298     type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN; \
0299     type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN; \
0300     type DSC_VERSION_MINOR; \
0301     type DSC_VERSION_MAJOR; \
0302     type PPS_IDENTIFIER; \
0303     type LINEBUF_DEPTH; \
0304     type DSCC_PPS_CONFIG0__BITS_PER_COMPONENT; \
0305     type BITS_PER_PIXEL; \
0306     type VBR_ENABLE; \
0307     type SIMPLE_422; \
0308     type CONVERT_RGB; \
0309     type BLOCK_PRED_ENABLE; \
0310     type NATIVE_422; \
0311     type NATIVE_420; \
0312     type CHUNK_SIZE; \
0313     type PIC_WIDTH; \
0314     type PIC_HEIGHT; \
0315     type SLICE_WIDTH; \
0316     type SLICE_HEIGHT; \
0317     type INITIAL_XMIT_DELAY; \
0318     type INITIAL_DEC_DELAY; \
0319     type INITIAL_SCALE_VALUE; \
0320     type SCALE_INCREMENT_INTERVAL; \
0321     type SCALE_DECREMENT_INTERVAL; \
0322     type FIRST_LINE_BPG_OFFSET; \
0323     type SECOND_LINE_BPG_OFFSET; \
0324     type NFL_BPG_OFFSET; \
0325     type SLICE_BPG_OFFSET; \
0326     type NSL_BPG_OFFSET; \
0327     type SECOND_LINE_OFFSET_ADJ; \
0328     type INITIAL_OFFSET; \
0329     type FINAL_OFFSET; \
0330     type FLATNESS_MIN_QP; \
0331     type FLATNESS_MAX_QP; \
0332     type RC_MODEL_SIZE; \
0333     type RC_EDGE_FACTOR; \
0334     type RC_QUANT_INCR_LIMIT0; \
0335     type RC_QUANT_INCR_LIMIT1; \
0336     type RC_TGT_OFFSET_LO; \
0337     type RC_TGT_OFFSET_HI; \
0338     type RC_BUF_THRESH0; \
0339     type RC_BUF_THRESH1; \
0340     type RC_BUF_THRESH2; \
0341     type RC_BUF_THRESH3; \
0342     type RC_BUF_THRESH4; \
0343     type RC_BUF_THRESH5; \
0344     type RC_BUF_THRESH6; \
0345     type RC_BUF_THRESH7; \
0346     type RC_BUF_THRESH8; \
0347     type RC_BUF_THRESH9; \
0348     type RC_BUF_THRESH10; \
0349     type RC_BUF_THRESH11; \
0350     type RC_BUF_THRESH12; \
0351     type RC_BUF_THRESH13; \
0352     type RANGE_MIN_QP0; \
0353     type RANGE_MAX_QP0; \
0354     type RANGE_BPG_OFFSET0; \
0355     type RANGE_MIN_QP1; \
0356     type RANGE_MAX_QP1; \
0357     type RANGE_BPG_OFFSET1; \
0358     type RANGE_MIN_QP2; \
0359     type RANGE_MAX_QP2; \
0360     type RANGE_BPG_OFFSET2; \
0361     type RANGE_MIN_QP3; \
0362     type RANGE_MAX_QP3; \
0363     type RANGE_BPG_OFFSET3; \
0364     type RANGE_MIN_QP4; \
0365     type RANGE_MAX_QP4; \
0366     type RANGE_BPG_OFFSET4; \
0367     type RANGE_MIN_QP5; \
0368     type RANGE_MAX_QP5; \
0369     type RANGE_BPG_OFFSET5; \
0370     type RANGE_MIN_QP6; \
0371     type RANGE_MAX_QP6; \
0372     type RANGE_BPG_OFFSET6; \
0373     type RANGE_MIN_QP7; \
0374     type RANGE_MAX_QP7; \
0375     type RANGE_BPG_OFFSET7; \
0376     type RANGE_MIN_QP8; \
0377     type RANGE_MAX_QP8; \
0378     type RANGE_BPG_OFFSET8; \
0379     type RANGE_MIN_QP9; \
0380     type RANGE_MAX_QP9; \
0381     type RANGE_BPG_OFFSET9; \
0382     type RANGE_MIN_QP10; \
0383     type RANGE_MAX_QP10; \
0384     type RANGE_BPG_OFFSET10; \
0385     type RANGE_MIN_QP11; \
0386     type RANGE_MAX_QP11; \
0387     type RANGE_BPG_OFFSET11; \
0388     type RANGE_MIN_QP12; \
0389     type RANGE_MAX_QP12; \
0390     type RANGE_BPG_OFFSET12; \
0391     type RANGE_MIN_QP13; \
0392     type RANGE_MAX_QP13; \
0393     type RANGE_BPG_OFFSET13; \
0394     type RANGE_MIN_QP14; \
0395     type RANGE_MAX_QP14; \
0396     type RANGE_BPG_OFFSET14; \
0397     type DSCC_DEFAULT_MEM_LOW_POWER_STATE; \
0398     type DSCC_MEM_PWR_FORCE; \
0399     type DSCC_MEM_PWR_DIS; \
0400     type DSCC_MEM_PWR_STATE; \
0401     type DSCC_NATIVE_422_MEM_PWR_FORCE; \
0402     type DSCC_NATIVE_422_MEM_PWR_DIS; \
0403     type DSCC_NATIVE_422_MEM_PWR_STATE; \
0404     type DSCC_R_Y_SQUARED_ERROR_LOWER; \
0405     type DSCC_R_Y_SQUARED_ERROR_UPPER; \
0406     type DSCC_G_CB_SQUARED_ERROR_LOWER; \
0407     type DSCC_G_CB_SQUARED_ERROR_UPPER; \
0408     type DSCC_B_CR_SQUARED_ERROR_LOWER; \
0409     type DSCC_B_CR_SQUARED_ERROR_UPPER; \
0410     type DSCC_R_Y_MAX_ABS_ERROR; \
0411     type DSCC_G_CB_MAX_ABS_ERROR; \
0412     type DSCC_B_CR_MAX_ABS_ERROR; \
0413     type DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL; \
0414     type DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL; \
0415     type DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL; \
0416     type DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL; \
0417     type DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL; \
0418     type DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; \
0419     type DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; \
0420     type DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; \
0421     type DSCC_UPDATE_PENDING_STATUS; \
0422     type DSCC_UPDATE_TAKEN_STATUS; \
0423     type DSCC_UPDATE_TAKEN_ACK; \
0424     type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
0425     type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
0426     type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
0427     type DSCC_RATE_BUFFER3_FULLNESS_LEVEL; \
0428     type DSCC_RATE_CONTROL_BUFFER0_FULLNESS_LEVEL; \
0429     type DSCC_RATE_CONTROL_BUFFER1_FULLNESS_LEVEL; \
0430     type DSCC_RATE_CONTROL_BUFFER2_FULLNESS_LEVEL; \
0431     type DSCC_RATE_CONTROL_BUFFER3_FULLNESS_LEVEL; \
0432     type DSCC_RATE_BUFFER0_INITIAL_XMIT_DELAY_REACHED; \
0433     type DSCC_RATE_BUFFER1_INITIAL_XMIT_DELAY_REACHED; \
0434     type DSCC_RATE_BUFFER2_INITIAL_XMIT_DELAY_REACHED; \
0435     type DSCC_RATE_BUFFER3_INITIAL_XMIT_DELAY_REACHED; \
0436     type INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN; \
0437     type INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN; \
0438     type INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS; \
0439     type INPUT_PIXEL_FORMAT; \
0440     type DSCCIF_CONFIG0__BITS_PER_COMPONENT; \
0441     type DOUBLE_BUFFER_REG_UPDATE_PENDING; \
0442     type DSCCIF_UPDATE_PENDING_STATUS; \
0443     type DSCCIF_UPDATE_TAKEN_STATUS; \
0444     type DSCCIF_UPDATE_TAKEN_ACK; \
0445     type DSCRM_DSC_FORWARD_EN; \
0446     type DSCRM_DSC_OPP_PIPE_SOURCE
0447 
0448 struct dcn20_dsc_registers {
0449     uint32_t DSC_TOP_CONTROL;
0450     uint32_t DSC_DEBUG_CONTROL;
0451     uint32_t DSCC_CONFIG0;
0452     uint32_t DSCC_CONFIG1;
0453     uint32_t DSCC_STATUS;
0454     uint32_t DSCC_INTERRUPT_CONTROL_STATUS;
0455     uint32_t DSCC_PPS_CONFIG0;
0456     uint32_t DSCC_PPS_CONFIG1;
0457     uint32_t DSCC_PPS_CONFIG2;
0458     uint32_t DSCC_PPS_CONFIG3;
0459     uint32_t DSCC_PPS_CONFIG4;
0460     uint32_t DSCC_PPS_CONFIG5;
0461     uint32_t DSCC_PPS_CONFIG6;
0462     uint32_t DSCC_PPS_CONFIG7;
0463     uint32_t DSCC_PPS_CONFIG8;
0464     uint32_t DSCC_PPS_CONFIG9;
0465     uint32_t DSCC_PPS_CONFIG10;
0466     uint32_t DSCC_PPS_CONFIG11;
0467     uint32_t DSCC_PPS_CONFIG12;
0468     uint32_t DSCC_PPS_CONFIG13;
0469     uint32_t DSCC_PPS_CONFIG14;
0470     uint32_t DSCC_PPS_CONFIG15;
0471     uint32_t DSCC_PPS_CONFIG16;
0472     uint32_t DSCC_PPS_CONFIG17;
0473     uint32_t DSCC_PPS_CONFIG18;
0474     uint32_t DSCC_PPS_CONFIG19;
0475     uint32_t DSCC_PPS_CONFIG20;
0476     uint32_t DSCC_PPS_CONFIG21;
0477     uint32_t DSCC_PPS_CONFIG22;
0478     uint32_t DSCC_MEM_POWER_CONTROL;
0479     uint32_t DSCC_R_Y_SQUARED_ERROR_LOWER;
0480     uint32_t DSCC_R_Y_SQUARED_ERROR_UPPER;
0481     uint32_t DSCC_G_CB_SQUARED_ERROR_LOWER;
0482     uint32_t DSCC_G_CB_SQUARED_ERROR_UPPER;
0483     uint32_t DSCC_B_CR_SQUARED_ERROR_LOWER;
0484     uint32_t DSCC_B_CR_SQUARED_ERROR_UPPER;
0485     uint32_t DSCC_MAX_ABS_ERROR0;
0486     uint32_t DSCC_MAX_ABS_ERROR1;
0487     uint32_t DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL;
0488     uint32_t DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL;
0489     uint32_t DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL;
0490     uint32_t DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL;
0491     uint32_t DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL;
0492     uint32_t DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL;
0493     uint32_t DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL;
0494     uint32_t DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL;
0495     uint32_t DSCCIF_CONFIG0;
0496     uint32_t DSCCIF_CONFIG1;
0497     uint32_t DSCRM_DSC_FORWARD_CONFIG;
0498 };
0499 
0500 
0501 struct dcn20_dsc_shift {
0502     DSC_FIELD_LIST_DCN20(uint8_t);
0503 };
0504 
0505 struct dcn20_dsc_mask {
0506     DSC_FIELD_LIST_DCN20(uint32_t);
0507 };
0508 
0509 /* DSCCIF_CONFIG.INPUT_PIXEL_FORMAT values */
0510 enum dsc_pixel_format {
0511     DSC_PIXFMT_RGB,
0512     DSC_PIXFMT_YCBCR444,
0513     DSC_PIXFMT_SIMPLE_YCBCR422,
0514     DSC_PIXFMT_NATIVE_YCBCR422,
0515     DSC_PIXFMT_NATIVE_YCBCR420,
0516     DSC_PIXFMT_UNKNOWN
0517 };
0518 
0519 struct dsc_reg_values {
0520     /* PPS registers */
0521     struct drm_dsc_config pps;
0522 
0523     /* Additional registers */
0524     uint32_t dsc_clock_enable;
0525     uint32_t dsc_clock_gating_disable;
0526     uint32_t underflow_recovery_en;
0527     uint32_t underflow_occurred_int_en;
0528     uint32_t underflow_occurred_status;
0529     enum dsc_pixel_format pixel_format;
0530     uint32_t ich_reset_at_eol;
0531     uint32_t alternate_ich_encoding_en;
0532     uint32_t num_slices_h;
0533     uint32_t num_slices_v;
0534     uint32_t rc_buffer_model_size;
0535     uint32_t disable_ich;
0536     uint32_t bpp_x32;
0537     uint32_t dsc_dbg_en;
0538     uint32_t rc_buffer_model_overflow_int_en[4];
0539 };
0540 
0541 struct dcn20_dsc {
0542     struct display_stream_compressor base;
0543     const struct dcn20_dsc_registers *dsc_regs;
0544     const struct dcn20_dsc_shift *dsc_shift;
0545     const struct dcn20_dsc_mask *dsc_mask;
0546 
0547     struct dsc_reg_values reg_vals;
0548 
0549     int max_image_width;
0550 };
0551 
0552 
0553 void dsc2_construct(struct dcn20_dsc *dsc,
0554         struct dc_context *ctx,
0555         int inst,
0556         const struct dcn20_dsc_registers *dsc_regs,
0557         const struct dcn20_dsc_shift *dsc_shift,
0558         const struct dcn20_dsc_mask *dsc_mask);
0559 
0560 #endif
0561
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!