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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include <drm/display/drm_dsc_helper.h>
0027 
0028 #include "reg_helper.h"
0029 #include "dcn20_dsc.h"
0030 #include "dsc/dscc_types.h"
0031 
0032 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
0033 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
0034             struct dsc_optc_config *dsc_optc_cfg);
0035 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
0036 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
0037 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
0038 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple);
0039 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth);
0040 
0041 /* Object I/F functions */
0042 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
0043 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
0044 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
0045 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
0046         struct dsc_optc_config *dsc_optc_cfg);
0047 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
0048 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
0049 static void dsc2_disable(struct display_stream_compressor *dsc);
0050 static void dsc2_disconnect(struct display_stream_compressor *dsc);
0051 
0052 const struct dsc_funcs dcn20_dsc_funcs = {
0053     .dsc_get_enc_caps = dsc2_get_enc_caps,
0054     .dsc_read_state = dsc2_read_state,
0055     .dsc_validate_stream = dsc2_validate_stream,
0056     .dsc_set_config = dsc2_set_config,
0057     .dsc_get_packed_pps = dsc2_get_packed_pps,
0058     .dsc_enable = dsc2_enable,
0059     .dsc_disable = dsc2_disable,
0060     .dsc_disconnect = dsc2_disconnect,
0061 };
0062 
0063 /* Macro definitios for REG_SET macros*/
0064 #define CTX \
0065     dsc20->base.ctx
0066 
0067 #define REG(reg)\
0068     dsc20->dsc_regs->reg
0069 
0070 #undef FN
0071 #define FN(reg_name, field_name) \
0072     dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
0073 #define DC_LOGGER \
0074     dsc->ctx->logger
0075 
0076 enum dsc_bits_per_comp {
0077     DSC_BPC_8 = 8,
0078     DSC_BPC_10 = 10,
0079     DSC_BPC_12 = 12,
0080     DSC_BPC_UNKNOWN
0081 };
0082 
0083 /* API functions (external or via structure->function_pointer) */
0084 
0085 void dsc2_construct(struct dcn20_dsc *dsc,
0086         struct dc_context *ctx,
0087         int inst,
0088         const struct dcn20_dsc_registers *dsc_regs,
0089         const struct dcn20_dsc_shift *dsc_shift,
0090         const struct dcn20_dsc_mask *dsc_mask)
0091 {
0092     dsc->base.ctx = ctx;
0093     dsc->base.inst = inst;
0094     dsc->base.funcs = &dcn20_dsc_funcs;
0095 
0096     dsc->dsc_regs = dsc_regs;
0097     dsc->dsc_shift = dsc_shift;
0098     dsc->dsc_mask = dsc_mask;
0099 
0100     dsc->max_image_width = 5184;
0101 }
0102 
0103 
0104 #define DCN20_MAX_PIXEL_CLOCK_Mhz      1188
0105 #define DCN20_MAX_DISPLAY_CLOCK_Mhz    1200
0106 
0107 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
0108  * can be doubled, tripled etc. by using additional DSC engines.
0109  */
0110 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
0111 {
0112     dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
0113 
0114     dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
0115     dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
0116     dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
0117     dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
0118 
0119     dsc_enc_caps->lb_bit_depth = 13;
0120     dsc_enc_caps->is_block_pred_supported = true;
0121 
0122     dsc_enc_caps->color_formats.bits.RGB = 1;
0123     dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
0124     dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
0125     dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
0126     dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
0127 
0128     dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
0129     dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
0130     dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
0131 
0132     /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
0133      * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
0134      * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
0135      * be sufficient to process the input pixel rate fed into a single DSC engine.
0136      */
0137     dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
0138 
0139     /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
0140      * throughput and number of slices, but also introduces a lower limit of 2 slices
0141      */
0142     if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
0143         dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
0144         dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
0145         dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
0146     }
0147 
0148     // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM.
0149     dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
0150     dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
0151 }
0152 
0153 
0154 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
0155  * into a dcn_dsc_state struct.
0156  */
0157 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
0158 {
0159     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0160 
0161     REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
0162     REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
0163     REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
0164     REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
0165     REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
0166     REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
0167     REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
0168     REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
0169     REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
0170         DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
0171 }
0172 
0173 
0174 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
0175 {
0176     struct dsc_optc_config dsc_optc_cfg;
0177     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0178 
0179     if (dsc_cfg->pic_width > dsc20->max_image_width)
0180         return false;
0181 
0182     return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
0183 }
0184 
0185 
0186 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
0187 {
0188     DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
0189     DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
0190     DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
0191         config->dc_dsc_cfg.bits_per_pixel,
0192         config->dc_dsc_cfg.bits_per_pixel / 16,
0193         ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
0194     DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
0195 }
0196 
0197 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
0198         struct dsc_optc_config *dsc_optc_cfg)
0199 {
0200     bool is_config_ok;
0201     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0202 
0203     DC_LOG_DSC(" ");
0204     DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
0205     dsc_config_log(dsc, dsc_cfg);
0206     is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
0207     ASSERT(is_config_ok);
0208     DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
0209     dsc_log_pps(dsc, &dsc20->reg_vals.pps);
0210     dsc_write_to_registers(dsc, &dsc20->reg_vals);
0211 }
0212 
0213 
0214 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
0215 {
0216     bool is_config_ok;
0217     struct dsc_reg_values dsc_reg_vals;
0218     struct dsc_optc_config dsc_optc_cfg;
0219 
0220     memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
0221     memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
0222 
0223     DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
0224     dsc_config_log(dsc, dsc_cfg);
0225     DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
0226     is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
0227     ASSERT(is_config_ok);
0228     drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
0229     dsc_log_pps(dsc, &dsc_reg_vals.pps);
0230 
0231     return is_config_ok;
0232 }
0233 
0234 
0235 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
0236 {
0237     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0238     int dsc_clock_en;
0239     int dsc_fw_config;
0240     int enabled_opp_pipe;
0241 
0242     DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
0243 
0244     REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
0245     REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
0246     if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
0247         DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
0248         ASSERT(0);
0249     }
0250 
0251     REG_UPDATE(DSC_TOP_CONTROL,
0252         DSC_CLOCK_EN, 1);
0253 
0254     REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
0255         DSCRM_DSC_FORWARD_EN, 1,
0256         DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
0257 }
0258 
0259 
0260 static void dsc2_disable(struct display_stream_compressor *dsc)
0261 {
0262     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0263     int dsc_clock_en;
0264     int dsc_fw_config;
0265     int enabled_opp_pipe;
0266 
0267     DC_LOG_DSC("disable DSC %d", dsc->inst);
0268 
0269     REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
0270     REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
0271     if (!dsc_clock_en || !dsc_fw_config) {
0272         DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe);
0273         ASSERT(0);
0274     }
0275 
0276     REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
0277         DSCRM_DSC_FORWARD_EN, 0);
0278 
0279     REG_UPDATE(DSC_TOP_CONTROL,
0280         DSC_CLOCK_EN, 0);
0281 }
0282 
0283 static void dsc2_disconnect(struct display_stream_compressor *dsc)
0284 {
0285     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0286 
0287     DC_LOG_DSC("disconnect DSC %d", dsc->inst);
0288 
0289     REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
0290         DSCRM_DSC_FORWARD_EN, 0);
0291 }
0292 
0293 /* This module's internal functions */
0294 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
0295 {
0296     int i;
0297     int bits_per_pixel = pps->bits_per_pixel;
0298 
0299     DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
0300     DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
0301     DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
0302     DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
0303     DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
0304     DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
0305     DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
0306     DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
0307     DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
0308     DC_LOG_DSC("\tpic_height %d", pps->pic_height);
0309     DC_LOG_DSC("\tpic_width %d", pps->pic_width);
0310     DC_LOG_DSC("\tslice_height %d", pps->slice_height);
0311     DC_LOG_DSC("\tslice_width %d", pps->slice_width);
0312     DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
0313     DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
0314     DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
0315     DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
0316     DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
0317     DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
0318     DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
0319     DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
0320     DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
0321     DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
0322     DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
0323     DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
0324     DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
0325     /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
0326     DC_LOG_DSC("\tnative_420 %d", pps->native_420);
0327     DC_LOG_DSC("\tnative_422 %d", pps->native_422);
0328     DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
0329     DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
0330     DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
0331     DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
0332     DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
0333     DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
0334     DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
0335     DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
0336     DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
0337 
0338     for (i = 0; i < NUM_BUF_RANGES - 1; i++)
0339         DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
0340 
0341     for (i = 0; i < NUM_BUF_RANGES; i++) {
0342         DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
0343         DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
0344         DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
0345     }
0346 }
0347 
0348 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
0349             struct dsc_optc_config *dsc_optc_cfg)
0350 {
0351     struct dsc_parameters dsc_params;
0352 
0353     /* Validate input parameters */
0354     ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
0355     ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
0356     ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
0357     ASSERT(dsc_cfg->pic_width);
0358     ASSERT(dsc_cfg->pic_height);
0359     ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
0360           (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
0361         (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
0362           ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
0363             dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
0364     ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
0365 
0366     if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
0367         !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
0368         !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
0369         !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
0370             8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
0371         (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
0372             ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
0373             dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
0374         !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
0375         dm_output_to_console("%s: Invalid parameters\n", __func__);
0376         return false;
0377     }
0378 
0379     dsc_init_reg_values(dsc_reg_vals);
0380 
0381     /* Copy input config */
0382     dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
0383     dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
0384     dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
0385     dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
0386     dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
0387     dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
0388     dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
0389     dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
0390     dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
0391     dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
0392     dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
0393 
0394     // TODO: in addition to validating slice height (pic height must be divisible by slice height),
0395     // see what happens when the same condition doesn't apply for slice_width/pic_width.
0396     dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
0397     dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
0398 
0399     ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
0400     if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
0401         dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
0402         return false;
0403     }
0404 
0405     dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
0406     if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
0407         dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
0408     else
0409         dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
0410 
0411     dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
0412     dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
0413     dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
0414     dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
0415 
0416     if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
0417         dm_output_to_console("%s: DSC config failed\n", __func__);
0418         return false;
0419     }
0420 
0421     dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
0422 
0423     dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
0424     dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
0425     dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
0426                     dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
0427                     dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
0428 
0429     return true;
0430 }
0431 
0432 
0433 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
0434 {
0435     enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
0436 
0437     /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
0438 
0439     switch (dc_pix_enc) {
0440     case PIXEL_ENCODING_RGB:
0441         dsc_pix_fmt = DSC_PIXFMT_RGB;
0442         break;
0443     case PIXEL_ENCODING_YCBCR422:
0444         if (is_ycbcr422_simple)
0445             dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
0446         else
0447             dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
0448         break;
0449     case PIXEL_ENCODING_YCBCR444:
0450         dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
0451         break;
0452     case PIXEL_ENCODING_YCBCR420:
0453         dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
0454         break;
0455     default:
0456         dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
0457         break;
0458     }
0459 
0460     ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
0461     return dsc_pix_fmt;
0462 }
0463 
0464 
0465 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
0466 {
0467     enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
0468 
0469     switch (dc_color_depth) {
0470     case COLOR_DEPTH_888:
0471         bpc = DSC_BPC_8;
0472         break;
0473     case COLOR_DEPTH_101010:
0474         bpc = DSC_BPC_10;
0475         break;
0476     case COLOR_DEPTH_121212:
0477         bpc = DSC_BPC_12;
0478         break;
0479     default:
0480         bpc = DSC_BPC_UNKNOWN;
0481         break;
0482     }
0483 
0484     return bpc;
0485 }
0486 
0487 
0488 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
0489 {
0490     int i;
0491 
0492     memset(reg_vals, 0, sizeof(struct dsc_reg_values));
0493 
0494     /* Non-PPS values */
0495     reg_vals->dsc_clock_enable            = 1;
0496     reg_vals->dsc_clock_gating_disable    = 0;
0497     reg_vals->underflow_recovery_en       = 0;
0498     reg_vals->underflow_occurred_int_en   = 0;
0499     reg_vals->underflow_occurred_status   = 0;
0500     reg_vals->ich_reset_at_eol            = 0;
0501     reg_vals->alternate_ich_encoding_en   = 0;
0502     reg_vals->rc_buffer_model_size        = 0;
0503     /*reg_vals->disable_ich                 = 0;*/
0504     reg_vals->dsc_dbg_en                  = 0;
0505 
0506     for (i = 0; i < 4; i++)
0507         reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
0508 
0509     /* PPS values */
0510     reg_vals->pps.dsc_version_minor           = 2;
0511     reg_vals->pps.dsc_version_major           = 1;
0512     reg_vals->pps.line_buf_depth              = 9;
0513     reg_vals->pps.bits_per_component          = 8;
0514     reg_vals->pps.block_pred_enable           = 1;
0515     reg_vals->pps.slice_chunk_size            = 0;
0516     reg_vals->pps.pic_width                   = 0;
0517     reg_vals->pps.pic_height                  = 0;
0518     reg_vals->pps.slice_width                 = 0;
0519     reg_vals->pps.slice_height                = 0;
0520     reg_vals->pps.initial_xmit_delay          = 170;
0521     reg_vals->pps.initial_dec_delay           = 0;
0522     reg_vals->pps.initial_scale_value         = 0;
0523     reg_vals->pps.scale_increment_interval    = 0;
0524     reg_vals->pps.scale_decrement_interval    = 0;
0525     reg_vals->pps.nfl_bpg_offset              = 0;
0526     reg_vals->pps.slice_bpg_offset            = 0;
0527     reg_vals->pps.nsl_bpg_offset              = 0;
0528     reg_vals->pps.initial_offset              = 6144;
0529     reg_vals->pps.final_offset                = 0;
0530     reg_vals->pps.flatness_min_qp             = 3;
0531     reg_vals->pps.flatness_max_qp             = 12;
0532     reg_vals->pps.rc_model_size               = 8192;
0533     reg_vals->pps.rc_edge_factor              = 6;
0534     reg_vals->pps.rc_quant_incr_limit0        = 11;
0535     reg_vals->pps.rc_quant_incr_limit1        = 11;
0536     reg_vals->pps.rc_tgt_offset_low           = 3;
0537     reg_vals->pps.rc_tgt_offset_high          = 3;
0538 }
0539 
0540 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
0541  * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
0542  * affects non-PPS register values.
0543  */
0544 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
0545 {
0546     int i;
0547 
0548     reg_vals->pps = dsc_params->pps;
0549 
0550     // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
0551     for (i = 0; i < NUM_BUF_RANGES - 1; i++)
0552         reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
0553 
0554     reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
0555 }
0556 
0557 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
0558 {
0559     uint32_t temp_int;
0560     struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
0561 
0562     REG_SET(DSC_DEBUG_CONTROL, 0,
0563         DSC_DBG_EN, reg_vals->dsc_dbg_en);
0564 
0565     // dsccif registers
0566     REG_SET_5(DSCCIF_CONFIG0, 0,
0567         INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
0568         INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
0569         INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
0570         INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
0571         DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
0572 
0573     REG_SET_2(DSCCIF_CONFIG1, 0,
0574         PIC_WIDTH, reg_vals->pps.pic_width,
0575         PIC_HEIGHT, reg_vals->pps.pic_height);
0576 
0577     // dscc registers
0578     if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
0579         REG_SET_3(DSCC_CONFIG0, 0,
0580               NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
0581               ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
0582               NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
0583     } else {
0584         REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
0585               reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
0586               reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
0587               reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
0588               reg_vals->num_slices_v - 1);
0589     }
0590 
0591     REG_SET(DSCC_CONFIG1, 0,
0592             DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
0593     /*REG_SET_2(DSCC_CONFIG1, 0,
0594         DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
0595         DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
0596 
0597     REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
0598         DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
0599         DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
0600         DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
0601         DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
0602 
0603     REG_SET_3(DSCC_PPS_CONFIG0, 0,
0604         DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
0605         LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
0606         DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
0607 
0608     if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
0609         temp_int = reg_vals->bpp_x32;
0610     else
0611         temp_int = reg_vals->bpp_x32 >> 1;
0612 
0613     REG_SET_7(DSCC_PPS_CONFIG1, 0,
0614         BITS_PER_PIXEL, temp_int,
0615         SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
0616         CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
0617         BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
0618         NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
0619         NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
0620         CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
0621 
0622     REG_SET_2(DSCC_PPS_CONFIG2, 0,
0623         PIC_WIDTH, reg_vals->pps.pic_width,
0624         PIC_HEIGHT, reg_vals->pps.pic_height);
0625 
0626     REG_SET_2(DSCC_PPS_CONFIG3, 0,
0627         SLICE_WIDTH, reg_vals->pps.slice_width,
0628         SLICE_HEIGHT, reg_vals->pps.slice_height);
0629 
0630     REG_SET(DSCC_PPS_CONFIG4, 0,
0631         INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
0632 
0633     REG_SET_2(DSCC_PPS_CONFIG5, 0,
0634         INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
0635         SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
0636 
0637     REG_SET_3(DSCC_PPS_CONFIG6, 0,
0638         SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
0639         FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
0640         SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
0641 
0642     REG_SET_2(DSCC_PPS_CONFIG7, 0,
0643         NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
0644         SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
0645 
0646     REG_SET_2(DSCC_PPS_CONFIG8, 0,
0647         NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
0648         SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
0649 
0650     REG_SET_2(DSCC_PPS_CONFIG9, 0,
0651         INITIAL_OFFSET, reg_vals->pps.initial_offset,
0652         FINAL_OFFSET, reg_vals->pps.final_offset);
0653 
0654     REG_SET_3(DSCC_PPS_CONFIG10, 0,
0655         FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
0656         FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
0657         RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
0658 
0659     REG_SET_5(DSCC_PPS_CONFIG11, 0,
0660         RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
0661         RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
0662         RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
0663         RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
0664         RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
0665 
0666     REG_SET_4(DSCC_PPS_CONFIG12, 0,
0667         RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
0668         RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
0669         RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
0670         RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
0671 
0672     REG_SET_4(DSCC_PPS_CONFIG13, 0,
0673         RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
0674         RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
0675         RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
0676         RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
0677 
0678     REG_SET_4(DSCC_PPS_CONFIG14, 0,
0679         RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
0680         RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
0681         RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
0682         RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
0683 
0684     REG_SET_5(DSCC_PPS_CONFIG15, 0,
0685         RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
0686         RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
0687         RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
0688         RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
0689         RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
0690 
0691     REG_SET_6(DSCC_PPS_CONFIG16, 0,
0692         RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
0693         RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
0694         RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
0695         RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
0696         RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
0697         RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
0698 
0699     REG_SET_6(DSCC_PPS_CONFIG17, 0,
0700         RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
0701         RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
0702         RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
0703         RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
0704         RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
0705         RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
0706 
0707     REG_SET_6(DSCC_PPS_CONFIG18, 0,
0708         RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
0709         RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
0710         RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
0711         RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
0712         RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
0713         RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
0714 
0715     REG_SET_6(DSCC_PPS_CONFIG19, 0,
0716         RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
0717         RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
0718         RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
0719         RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
0720         RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
0721         RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
0722 
0723     REG_SET_6(DSCC_PPS_CONFIG20, 0,
0724         RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
0725         RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
0726         RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
0727         RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
0728         RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
0729         RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
0730 
0731     REG_SET_6(DSCC_PPS_CONFIG21, 0,
0732         RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
0733         RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
0734         RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
0735         RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
0736         RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
0737         RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
0738 
0739     REG_SET_6(DSCC_PPS_CONFIG22, 0,
0740         RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
0741         RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
0742         RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
0743         RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
0744         RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
0745         RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
0746 
0747 }
0748
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