dc/dcn20/dcn20_dpp.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 #include "core_types.h"
0029
0030 #include "reg_helper.h"
0031 #include "dcn20_dpp.h"
0032 #include "basics/conversion.h"
0033
0034 #define NUM_PHASES    64
0035 #define HORZ_MAX_TAPS 8
0036 #define VERT_MAX_TAPS 8
0037
0038 #define BLACK_OFFSET_RGB_Y 0x0
0039 #define BLACK_OFFSET_CBCR  0x8000
0040
0041 #define REG(reg)\
0042     dpp->tf_regs->reg
0043
0044 #define CTX \
0045     dpp->base.ctx
0046
0047 #undef FN
0048 #define FN(reg_name, field_name) \
0049     dpp->tf_shift->field_name, dpp->tf_mask->field_name
0050
0051 void dpp20_read_state(struct dpp *dpp_base,
0052         struct dcn_dpp_state *s)
0053 {
0054     struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
0055
0056     REG_GET(DPP_CONTROL,
0057             DPP_CLOCK_ENABLE, &s->is_enabled);
0058     REG_GET(CM_DGAM_CONTROL,
0059             CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
0060     // BGAM has no ROM, and definition is different, can't reuse same dump
0061     //REG_GET(CM_BLNDGAM_CONTROL,
0062     //      CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
0063     REG_GET(CM_GAMUT_REMAP_CONTROL,
0064             CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
0065     if (s->gamut_remap_mode) {
0066         s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
0067         s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
0068         s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
0069         s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
0070         s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
0071         s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
0072     }
0073 }
0074
0075 void dpp2_power_on_obuf(
0076         struct dpp *dpp_base,
0077     bool power_on)
0078 {
0079     struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
0080
0081     REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
0082
0083     REG_UPDATE(OBUF_MEM_PWR_CTRL,
0084             OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
0085
0086     REG_UPDATE(DSCL_MEM_PWR_CTRL,
0087             LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
0088 }
0089
0090 void dpp2_dummy_program_input_lut(
0091         struct dpp *dpp_base,
0092         const struct dc_gamma *gamma)
0093 {}
0094
0095 static void dpp2_cnv_setup (
0096         struct dpp *dpp_base,
0097         enum surface_pixel_format format,
0098         enum expansion_mode mode,
0099         struct dc_csc_transform input_csc_color_matrix,
0100         enum dc_color_space input_color_space,
0101         struct cnv_alpha_2bit_lut *alpha_2bit_lut)
0102 {
0103     struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
0104     uint32_t pixel_format = 0;
0105     uint32_t alpha_en = 1;
0106     enum dc_color_space color_space = COLOR_SPACE_SRGB;
0107     enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS;
0108     bool force_disable_cursor = false;
0109     struct out_csc_color_matrix tbl_entry;
0110     uint32_t is_2bit = 0;
0111     int i = 0;
0112
0113     REG_SET_2(FORMAT_CONTROL, 0,
0114         CNVC_BYPASS, 0,
0115         FORMAT_EXPANSION_MODE, mode);
0116
0117     //hardcode default
0118     //FORMAT_CONTROL. FORMAT_CNV16                                  default 0: U0.16/S.1.15;         1: U1.15/ S.1.14
0119     //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN                         default 0: disabled              1: enabled
0120     //FORMAT_CONTROL. CLAMP_POSITIVE                                default 0: disabled              1: enabled
0121     //FORMAT_CONTROL. CLAMP_POSITIVE_C                              default 0: disabled              1: enabled
0122     REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
0123     REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
0124     REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
0125     REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
0126
0127     switch (format) {
0128     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0129         pixel_format = 1;
0130         break;
0131     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0132         pixel_format = 3;
0133         alpha_en = 0;
0134         break;
0135     case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
0136     case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
0137         pixel_format = 8;
0138         break;
0139     case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
0140     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
0141         pixel_format = 10;
0142         is_2bit = 1;
0143         break;
0144     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0145         force_disable_cursor = false;
0146         pixel_format = 65;
0147         color_space = COLOR_SPACE_YCBCR709;
0148         select = DCN2_ICSC_SELECT_ICSC_A;
0149         break;
0150     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0151         force_disable_cursor = true;
0152         pixel_format = 64;
0153         color_space = COLOR_SPACE_YCBCR709;
0154         select = DCN2_ICSC_SELECT_ICSC_A;
0155         break;
0156     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0157         force_disable_cursor = true;
0158         pixel_format = 67;
0159         color_space = COLOR_SPACE_YCBCR709;
0160         select = DCN2_ICSC_SELECT_ICSC_A;
0161         break;
0162     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0163         force_disable_cursor = true;
0164         pixel_format = 66;
0165         color_space = COLOR_SPACE_YCBCR709;
0166         select = DCN2_ICSC_SELECT_ICSC_A;
0167         break;
0168     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0169     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
0170         pixel_format = 26; /* ARGB16161616_UNORM */
0171         break;
0172     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0173         pixel_format = 24;
0174         break;
0175     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0176         pixel_format = 25;
0177         break;
0178     case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
0179         pixel_format = 12;
0180         color_space = COLOR_SPACE_YCBCR709;
0181         select = DCN2_ICSC_SELECT_ICSC_A;
0182         break;
0183     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
0184         pixel_format = 112;
0185         alpha_en = 0;
0186         break;
0187     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
0188         pixel_format = 113;
0189         alpha_en = 0;
0190         break;
0191     case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
0192         pixel_format = 114;
0193         color_space = COLOR_SPACE_YCBCR709;
0194         select = DCN2_ICSC_SELECT_ICSC_A;
0195         is_2bit = 1;
0196         break;
0197     case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
0198         pixel_format = 115;
0199         color_space = COLOR_SPACE_YCBCR709;
0200         select = DCN2_ICSC_SELECT_ICSC_A;
0201         is_2bit = 1;
0202         break;
0203     case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
0204         pixel_format = 118;
0205         alpha_en = 0;
0206         break;
0207     case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
0208         pixel_format = 119;
0209         alpha_en = 0;
0210         break;
0211     default:
0212         break;
0213     }
0214
0215     /* Set default color space based on format if none is given. */
0216     color_space = input_color_space ? input_color_space : color_space;
0217
0218     if (is_2bit == 1 && alpha_2bit_lut != NULL) {
0219         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
0220         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
0221         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
0222         REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
0223     }
0224
0225     REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
0226             CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
0227     REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
0228
0229     // if input adjustments exist, program icsc with those values
0230     if (input_csc_color_matrix.enable_adjustment
0231                 == true) {
0232         for (i = 0; i < 12; i++)
0233             tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
0234
0235         tbl_entry.color_space = input_color_space;
0236
0237         if (color_space >= COLOR_SPACE_YCBCR601)
0238             select = DCN2_ICSC_SELECT_ICSC_A;
0239         else
0240             select = DCN2_ICSC_SELECT_BYPASS;
0241
0242         dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry);
0243     } else
0244     dpp2_program_input_csc(dpp_base, color_space, select, NULL);
0245
0246     if (force_disable_cursor) {
0247         REG_UPDATE(CURSOR_CONTROL,
0248                 CURSOR_ENABLE, 0);
0249         REG_UPDATE(CURSOR0_CONTROL,
0250                 CUR0_ENABLE, 0);
0251
0252     }
0253     dpp2_power_on_obuf(dpp_base, true);
0254
0255 }
0256
0257 /*compute the maximum number of lines that we can fit in the line buffer*/
0258 void dscl2_calc_lb_num_partitions(
0259         const struct scaler_data *scl_data,
0260         enum lb_memory_config lb_config,
0261         int *num_part_y,
0262         int *num_part_c)
0263 {
0264     int memory_line_size_y, memory_line_size_c, memory_line_size_a,
0265     lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
0266
0267     int line_size = scl_data->viewport.width < scl_data->recout.width ?
0268             scl_data->viewport.width : scl_data->recout.width;
0269     int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
0270             scl_data->viewport_c.width : scl_data->recout.width;
0271
0272     if (line_size == 0)
0273         line_size = 1;
0274
0275     if (line_size_c == 0)
0276         line_size_c = 1;
0277
0278     memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
0279     memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
0280     memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
0281
0282     if (lb_config == LB_MEMORY_CONFIG_1) {
0283         lb_memory_size = 970;
0284         lb_memory_size_c = 970;
0285         lb_memory_size_a = 970;
0286     } else if (lb_config == LB_MEMORY_CONFIG_2) {
0287         lb_memory_size = 1290;
0288         lb_memory_size_c = 1290;
0289         lb_memory_size_a = 1290;
0290     } else if (lb_config == LB_MEMORY_CONFIG_3) {
0291         /* 420 mode: using 3rd mem from Y, Cr and Cb */
0292         lb_memory_size = 970 + 1290 + 484 + 484 + 484;
0293         lb_memory_size_c = 970 + 1290;
0294         lb_memory_size_a = 970 + 1290 + 484;
0295     } else {
0296         lb_memory_size = 970 + 1290 + 484;
0297         lb_memory_size_c = 970 + 1290 + 484;
0298         lb_memory_size_a = 970 + 1290 + 484;
0299     }
0300     *num_part_y = lb_memory_size / memory_line_size_y;
0301     *num_part_c = lb_memory_size_c / memory_line_size_c;
0302     num_partitions_a = lb_memory_size_a / memory_line_size_a;
0303
0304     if (scl_data->lb_params.alpha_en
0305             && (num_partitions_a < *num_part_y))
0306         *num_part_y = num_partitions_a;
0307
0308     if (*num_part_y > 64)
0309         *num_part_y = 64;
0310     if (*num_part_c > 64)
0311         *num_part_c = 64;
0312 }
0313
0314 void dpp2_cnv_set_alpha_keyer(
0315         struct dpp *dpp_base,
0316         struct cnv_color_keyer_params *color_keyer)
0317 {
0318     struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
0319
0320     REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en);
0321
0322     REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode);
0323
0324     REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low);
0325     REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high);
0326
0327     REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low);
0328     REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high);
0329
0330     REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low);
0331     REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high);
0332
0333     REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low);
0334     REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high);
0335 }
0336
0337 void dpp2_set_cursor_attributes(
0338         struct dpp *dpp_base,
0339         struct dc_cursor_attributes *cursor_attributes)
0340 {
0341     enum dc_cursor_color_format color_format = cursor_attributes->color_format;
0342     struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
0343     int cur_rom_en = 0;
0344
0345     if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
0346         color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
0347         if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
0348             cur_rom_en = 1;
0349         }
0350     }
0351
0352     REG_UPDATE_3(CURSOR0_CONTROL,
0353             CUR0_MODE, color_format,
0354             CUR0_EXPANSION_MODE, 0,
0355             CUR0_ROM_EN, cur_rom_en);
0356
0357     if (color_format == CURSOR_MODE_MONO) {
0358         /* todo: clarify what to program these to */
0359         REG_UPDATE(CURSOR0_COLOR0,
0360                 CUR0_COLOR0, 0x00000000);
0361         REG_UPDATE(CURSOR0_COLOR1,
0362                 CUR0_COLOR1, 0xFFFFFFFF);
0363     }
0364 }
0365
0366 void oppn20_dummy_program_regamma_pwl(
0367         struct dpp *dpp,
0368         const struct pwl_params *params,
0369         enum opp_regamma mode)
0370 {}
0371
0372 static struct dpp_funcs dcn20_dpp_funcs = {
0373     .dpp_read_state = dpp20_read_state,
0374     .dpp_reset = dpp_reset,
0375     .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
0376     .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
0377     .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap,
0378     .dpp_set_csc_adjustment = NULL,
0379     .dpp_set_csc_default = NULL,
0380     .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl,
0381     .dpp_set_degamma        = dpp2_set_degamma,
0382     .dpp_program_input_lut      = dpp2_dummy_program_input_lut,
0383     .dpp_full_bypass        = dpp1_full_bypass,
0384     .dpp_setup          = dpp2_cnv_setup,
0385     .dpp_program_degamma_pwl    = dpp2_set_degamma_pwl,
0386     .dpp_program_blnd_lut = dpp20_program_blnd_lut,
0387     .dpp_program_shaper_lut = dpp20_program_shaper,
0388     .dpp_program_3dlut = dpp20_program_3dlut,
0389     .dpp_program_bias_and_scale = NULL,
0390     .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
0391     .set_cursor_attributes = dpp2_set_cursor_attributes,
0392     .set_cursor_position = dpp1_set_cursor_position,
0393     .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
0394     .dpp_dppclk_control = dpp1_dppclk_control,
0395     .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier,
0396 };
0397
0398 static struct dpp_caps dcn20_dpp_cap = {
0399     .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
0400     .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions,
0401 };
0402
0403 bool dpp2_construct(
0404     struct dcn20_dpp *dpp,
0405     struct dc_context *ctx,
0406     uint32_t inst,
0407     const struct dcn2_dpp_registers *tf_regs,
0408     const struct dcn2_dpp_shift *tf_shift,
0409     const struct dcn2_dpp_mask *tf_mask)
0410 {
0411     dpp->base.ctx = ctx;
0412
0413     dpp->base.inst = inst;
0414     dpp->base.funcs = &dcn20_dpp_funcs;
0415     dpp->base.caps = &dcn20_dpp_cap;
0416
0417     dpp->tf_regs = tf_regs;
0418     dpp->tf_shift = tf_shift;
0419     dpp->tf_mask = tf_mask;
0420
0421     dpp->lb_pixel_depth_supported =
0422         LB_PIXEL_DEPTH_18BPP |
0423         LB_PIXEL_DEPTH_24BPP |
0424         LB_PIXEL_DEPTH_30BPP |
0425         LB_PIXEL_DEPTH_36BPP;
0426
0427     dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
0428     dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
0429
0430     return true;
0431 }
0432