dc/dcn20/dcn20_dccg.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCN20_DCCG_H__
0027 #define __DCN20_DCCG_H__
0028
0029 #include "dccg.h"
0030
0031 #define DCCG_COMMON_REG_LIST_DCN_BASE() \
0032     SR(DPPCLK_DTO_CTRL),\
0033     DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
0034     DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
0035     DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
0036     DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
0037     SR(REFCLK_CNTL),\
0038     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
0039     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
0040     SR(DISPCLK_FREQ_CHANGE_CNTL)
0041
0042 #define DCCG_REG_LIST_DCN2() \
0043     DCCG_COMMON_REG_LIST_DCN_BASE(),\
0044     DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
0045     DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
0046     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
0047     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
0048     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
0049     DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
0050
0051 #define DCCG_SF(reg_name, field_name, post_fix)\
0052     .field_name = reg_name ## __ ## field_name ## post_fix
0053
0054 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
0055     .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
0056
0057 #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
0058     .field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
0059
0060 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
0061     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
0062     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
0063     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
0064     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
0065     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
0066     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
0067     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
0068     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
0069     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
0070     DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
0071     DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
0072     DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
0073     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
0074     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
0075     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
0076     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
0077     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
0078     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
0079     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
0080     DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
0081     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
0082     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
0083     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
0084     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
0085
0086
0087
0088
0089 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
0090     DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
0091     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
0092     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
0093     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
0094     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
0095     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
0096     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
0097     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
0098     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
0099     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
0100     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
0101     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
0102     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
0103
0104 #define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
0105     DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
0106     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
0107     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
0108     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
0109     DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
0110     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
0111     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
0112     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
0113     DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
0114
0115
0116 #define DCCG_REG_FIELD_LIST(type) \
0117     type DPPCLK0_DTO_PHASE;\
0118     type DPPCLK0_DTO_MODULO;\
0119     type DPPCLK_DTO_ENABLE[6];\
0120     type DPPCLK_DTO_DB_EN[6];\
0121     type REFCLK_CLOCK_EN;\
0122     type REFCLK_SRC_SEL;\
0123     type DISPCLK_STEP_DELAY;\
0124     type DISPCLK_STEP_SIZE;\
0125     type DISPCLK_FREQ_RAMP_DONE;\
0126     type DISPCLK_MAX_ERRDET_CYCLES;\
0127     type DCCG_FIFO_ERRDET_RESET;\
0128     type DCCG_FIFO_ERRDET_STATE;\
0129     type DCCG_FIFO_ERRDET_OVR_EN;\
0130     type DISPCLK_CHG_FWD_CORR_DISABLE;\
0131     type DISPCLK_FREQ_CHANGE_CNTL;\
0132     type OTG_ADD_PIXEL[MAX_PIPES];\
0133     type OTG_DROP_PIXEL[MAX_PIPES];
0134
0135 #define DCCG3_REG_FIELD_LIST(type) \
0136     type HDMICHARCLK0_EN;\
0137     type HDMICHARCLK0_SRC_SEL;\
0138     type PHYASYMCLK_FORCE_EN;\
0139     type PHYASYMCLK_FORCE_SRC_SEL;\
0140     type PHYBSYMCLK_FORCE_EN;\
0141     type PHYBSYMCLK_FORCE_SRC_SEL;\
0142     type PHYCSYMCLK_FORCE_EN;\
0143     type PHYCSYMCLK_FORCE_SRC_SEL;
0144
0145 #define DCCG31_REG_FIELD_LIST(type) \
0146     type PHYDSYMCLK_FORCE_EN;\
0147     type PHYDSYMCLK_FORCE_SRC_SEL;\
0148     type PHYESYMCLK_FORCE_EN;\
0149     type PHYESYMCLK_FORCE_SRC_SEL;\
0150     type DPSTREAMCLK_PIPE0_EN;\
0151     type DPSTREAMCLK_PIPE1_EN;\
0152     type DPSTREAMCLK_PIPE2_EN;\
0153     type DPSTREAMCLK_PIPE3_EN;\
0154     type HDMISTREAMCLK0_SRC_SEL;\
0155     type HDMISTREAMCLK0_DTO_FORCE_DIS;\
0156     type SYMCLK32_SE0_SRC_SEL;\
0157     type SYMCLK32_SE1_SRC_SEL;\
0158     type SYMCLK32_SE2_SRC_SEL;\
0159     type SYMCLK32_SE3_SRC_SEL;\
0160     type SYMCLK32_SE0_EN;\
0161     type SYMCLK32_SE1_EN;\
0162     type SYMCLK32_SE2_EN;\
0163     type SYMCLK32_SE3_EN;\
0164     type SYMCLK32_LE0_SRC_SEL;\
0165     type SYMCLK32_LE1_SRC_SEL;\
0166     type SYMCLK32_LE0_EN;\
0167     type SYMCLK32_LE1_EN;\
0168     type DTBCLK_DTO_ENABLE[MAX_PIPES];\
0169     type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
0170     type PIPE_DTO_SRC_SEL[MAX_PIPES];\
0171     type DTBCLK_DTO_DIV[MAX_PIPES];\
0172     type DCCG_AUDIO_DTO_SEL;\
0173     type DCCG_AUDIO_DTO0_SOURCE_SEL;\
0174     type DENTIST_DISPCLK_CHG_MODE;\
0175     type DSCCLK0_DTO_PHASE;\
0176     type DSCCLK0_DTO_MODULO;\
0177     type DSCCLK1_DTO_PHASE;\
0178     type DSCCLK1_DTO_MODULO;\
0179     type DSCCLK2_DTO_PHASE;\
0180     type DSCCLK2_DTO_MODULO;\
0181     type DSCCLK0_DTO_ENABLE;\
0182     type DSCCLK1_DTO_ENABLE;\
0183     type DSCCLK2_DTO_ENABLE;\
0184     type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
0185     type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
0186     type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
0187     type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
0188     type SYMCLK32_SE0_GATE_DISABLE;\
0189     type SYMCLK32_SE1_GATE_DISABLE;\
0190     type SYMCLK32_SE2_GATE_DISABLE;\
0191     type SYMCLK32_SE3_GATE_DISABLE;\
0192     type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
0193     type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
0194     type SYMCLK32_LE0_GATE_DISABLE;\
0195     type SYMCLK32_LE1_GATE_DISABLE;\
0196     type DPSTREAMCLK_ROOT_GATE_DISABLE;\
0197     type DPSTREAMCLK_GATE_DISABLE;\
0198     type HDMISTREAMCLK0_DTO_PHASE;\
0199     type HDMISTREAMCLK0_DTO_MODULO;\
0200     type HDMICHARCLK0_GATE_DISABLE;\
0201     type HDMICHARCLK0_ROOT_GATE_DISABLE; \
0202     type PHYASYMCLK_GATE_DISABLE; \
0203     type PHYBSYMCLK_GATE_DISABLE; \
0204     type PHYCSYMCLK_GATE_DISABLE; \
0205     type PHYDSYMCLK_GATE_DISABLE; \
0206     type PHYESYMCLK_GATE_DISABLE;
0207
0208 #define DCCG32_REG_FIELD_LIST(type) \
0209     type DPSTREAMCLK0_EN;\
0210     type DPSTREAMCLK1_EN;\
0211     type DPSTREAMCLK2_EN;\
0212     type DPSTREAMCLK3_EN;\
0213     type DPSTREAMCLK0_SRC_SEL;\
0214     type DPSTREAMCLK1_SRC_SEL;\
0215     type DPSTREAMCLK2_SRC_SEL;\
0216     type DPSTREAMCLK3_SRC_SEL;\
0217     type HDMISTREAMCLK0_EN;\
0218     type OTG0_PIXEL_RATE_DIVK1;\
0219     type OTG0_PIXEL_RATE_DIVK2;\
0220     type OTG1_PIXEL_RATE_DIVK1;\
0221     type OTG1_PIXEL_RATE_DIVK2;\
0222     type OTG2_PIXEL_RATE_DIVK1;\
0223     type OTG2_PIXEL_RATE_DIVK2;\
0224     type OTG3_PIXEL_RATE_DIVK1;\
0225     type OTG3_PIXEL_RATE_DIVK2;\
0226     type DTBCLK_P0_SRC_SEL;\
0227     type DTBCLK_P0_EN;\
0228     type DTBCLK_P1_SRC_SEL;\
0229     type DTBCLK_P1_EN;\
0230     type DTBCLK_P2_SRC_SEL;\
0231     type DTBCLK_P2_EN;\
0232     type DTBCLK_P3_SRC_SEL;\
0233     type DTBCLK_P3_EN;
0234
0235 struct dccg_shift {
0236     DCCG_REG_FIELD_LIST(uint8_t)
0237     DCCG3_REG_FIELD_LIST(uint8_t)
0238     DCCG31_REG_FIELD_LIST(uint8_t)
0239     DCCG32_REG_FIELD_LIST(uint8_t)
0240 };
0241
0242 struct dccg_mask {
0243     DCCG_REG_FIELD_LIST(uint32_t)
0244     DCCG3_REG_FIELD_LIST(uint32_t)
0245     DCCG31_REG_FIELD_LIST(uint32_t)
0246     DCCG32_REG_FIELD_LIST(uint32_t)
0247 };
0248
0249 struct dccg_registers {
0250     uint32_t DPPCLK_DTO_CTRL;
0251     uint32_t DPPCLK_DTO_PARAM[6];
0252     uint32_t REFCLK_CNTL;
0253     uint32_t DISPCLK_FREQ_CHANGE_CNTL;
0254     uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
0255     uint32_t HDMICHARCLK_CLOCK_CNTL[6];
0256     uint32_t PHYASYMCLK_CLOCK_CNTL;
0257     uint32_t PHYBSYMCLK_CLOCK_CNTL;
0258     uint32_t PHYCSYMCLK_CLOCK_CNTL;
0259     uint32_t PHYDSYMCLK_CLOCK_CNTL;
0260     uint32_t PHYESYMCLK_CLOCK_CNTL;
0261     uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
0262     uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
0263     uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
0264     uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
0265     uint32_t DCCG_AUDIO_DTO_SOURCE;
0266     uint32_t DPSTREAMCLK_CNTL;
0267     uint32_t HDMISTREAMCLK_CNTL;
0268     uint32_t SYMCLK32_SE_CNTL;
0269     uint32_t SYMCLK32_LE_CNTL;
0270     uint32_t DENTIST_DISPCLK_CNTL;
0271     uint32_t DSCCLK_DTO_CTRL;
0272     uint32_t DSCCLK0_DTO_PARAM;
0273     uint32_t DSCCLK1_DTO_PARAM;
0274     uint32_t DSCCLK2_DTO_PARAM;
0275     uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
0276     uint32_t DPSTREAMCLK_GATE_DISABLE;
0277     uint32_t DCCG_GATE_DISABLE_CNTL2;
0278     uint32_t DCCG_GATE_DISABLE_CNTL3;
0279     uint32_t HDMISTREAMCLK0_DTO_PARAM;
0280     uint32_t DCCG_GATE_DISABLE_CNTL4;
0281     uint32_t OTG_PIXEL_RATE_DIV;
0282     uint32_t DTBCLK_P_CNTL;
0283 };
0284
0285 struct dcn_dccg {
0286     struct dccg base;
0287     const struct dccg_registers *regs;
0288     const struct dccg_shift *dccg_shift;
0289     const struct dccg_mask *dccg_mask;
0290 };
0291
0292 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
0293
0294 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
0295         unsigned int xtalin_freq_inKhz,
0296         unsigned int *dccg_ref_freq_inKhz);
0297
0298 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
0299         bool en);
0300 void dccg2_otg_add_pixel(struct dccg *dccg,
0301         uint32_t otg_inst);
0302 void dccg2_otg_drop_pixel(struct dccg *dccg,
0303         uint32_t otg_inst);
0304
0305
0306 void dccg2_init(struct dccg *dccg);
0307
0308 struct dccg *dccg2_create(
0309     struct dc_context *ctx,
0310     const struct dccg_registers *regs,
0311     const struct dccg_shift *dccg_shift,
0312     const struct dccg_mask *dccg_mask);
0313
0314 void dcn_dccg_destroy(struct dccg **dccg);
0315
0316 #endif //__DCN20_DCCG_H__