dc/dcn20/dcn20_dccg.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include <linux/slab.h>
0027
0028 #include "reg_helper.h"
0029 #include "core_types.h"
0030 #include "dcn20_dccg.h"
0031
0032 #define TO_DCN_DCCG(dccg)\
0033     container_of(dccg, struct dcn_dccg, base)
0034
0035 #define REG(reg) \
0036     (dccg_dcn->regs->reg)
0037
0038 #undef FN
0039 #define FN(reg_name, field_name) \
0040     dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
0041
0042 #define CTX \
0043     dccg_dcn->base.ctx
0044 #define DC_LOGGER \
0045     dccg->ctx->logger
0046
0047 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
0048 {
0049     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
0050
0051     if (dccg->ref_dppclk && req_dppclk) {
0052         int ref_dppclk = dccg->ref_dppclk;
0053         int modulo, phase;
0054
0055         // phase / modulo = dpp pipe clk / dpp global clk
0056         modulo = 0xff;   // use FF at the end
0057         phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
0058
0059         if (phase > 0xff) {
0060             ASSERT(false);
0061             phase = 0xff;
0062         }
0063
0064         REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
0065                 DPPCLK0_DTO_PHASE, phase,
0066                 DPPCLK0_DTO_MODULO, modulo);
0067         REG_UPDATE(DPPCLK_DTO_CTRL,
0068                 DPPCLK_DTO_ENABLE[dpp_inst], 1);
0069     } else {
0070         REG_UPDATE(DPPCLK_DTO_CTRL,
0071                 DPPCLK_DTO_ENABLE[dpp_inst], 0);
0072     }
0073
0074     dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
0075 }
0076
0077 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
0078         unsigned int xtalin_freq_inKhz,
0079         unsigned int *dccg_ref_freq_inKhz)
0080 {
0081     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
0082     uint32_t clk_en = 0;
0083     uint32_t clk_sel = 0;
0084
0085     REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
0086
0087     if (clk_en != 0) {
0088         // DCN20 has never been validated for non-xtalin as reference
0089         // frequency.  There's actually no way for DC to determine what
0090         // frequency a non-xtalin source is.
0091         ASSERT_CRITICAL(false);
0092     }
0093
0094     *dccg_ref_freq_inKhz = xtalin_freq_inKhz;
0095
0096     return;
0097 }
0098
0099 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
0100         bool en)
0101 {
0102     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
0103
0104     REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,
0105             DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
0106 }
0107
0108 void dccg2_otg_add_pixel(struct dccg *dccg,
0109         uint32_t otg_inst)
0110 {
0111     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
0112
0113     REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
0114             OTG_ADD_PIXEL[otg_inst], 0,
0115             OTG_DROP_PIXEL[otg_inst], 0);
0116     REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
0117             OTG_ADD_PIXEL[otg_inst], 1);
0118 }
0119
0120 void dccg2_otg_drop_pixel(struct dccg *dccg,
0121         uint32_t otg_inst)
0122 {
0123     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
0124
0125     REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
0126             OTG_ADD_PIXEL[otg_inst], 0,
0127             OTG_DROP_PIXEL[otg_inst], 0);
0128     REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
0129             OTG_DROP_PIXEL[otg_inst], 1);
0130 }
0131
0132 void dccg2_init(struct dccg *dccg)
0133 {
0134 }
0135
0136 static const struct dccg_funcs dccg2_funcs = {
0137     .update_dpp_dto = dccg2_update_dpp_dto,
0138     .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
0139     .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
0140     .otg_add_pixel = dccg2_otg_add_pixel,
0141     .otg_drop_pixel = dccg2_otg_drop_pixel,
0142     .dccg_init = dccg2_init
0143 };
0144
0145 struct dccg *dccg2_create(
0146     struct dc_context *ctx,
0147     const struct dccg_registers *regs,
0148     const struct dccg_shift *dccg_shift,
0149     const struct dccg_mask *dccg_mask)
0150 {
0151     struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC);
0152     struct dccg *base;
0153
0154     if (dccg_dcn == NULL) {
0155         BREAK_TO_DEBUGGER();
0156         return NULL;
0157     }
0158
0159     base = &dccg_dcn->base;
0160     base->ctx = ctx;
0161     base->funcs = &dccg2_funcs;
0162
0163     dccg_dcn->regs = regs;
0164     dccg_dcn->dccg_shift = dccg_shift;
0165     dccg_dcn->dccg_mask = dccg_mask;
0166
0167     return &dccg_dcn->base;
0168 }
0169
0170 void dcn_dccg_destroy(struct dccg **dccg)
0171 {
0172     struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);
0173
0174     kfree(dccg_dcn);
0175     *dccg = NULL;
0176 }