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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #ifndef __DC_STREAM_ENCODER_DCN10_H__
0027 #define __DC_STREAM_ENCODER_DCN10_H__
0028 
0029 #include "stream_encoder.h"
0030 
0031 #define DCN10STRENC_FROM_STRENC(stream_encoder)\
0032     container_of(stream_encoder, struct dcn10_stream_encoder, base)
0033 
0034 #define SE_COMMON_DCN_REG_LIST(id) \
0035     SRI(AFMT_CNTL, DIG, id), \
0036     SRI(AFMT_GENERIC_0, DIG, id), \
0037     SRI(AFMT_GENERIC_1, DIG, id), \
0038     SRI(AFMT_GENERIC_2, DIG, id), \
0039     SRI(AFMT_GENERIC_3, DIG, id), \
0040     SRI(AFMT_GENERIC_4, DIG, id), \
0041     SRI(AFMT_GENERIC_5, DIG, id), \
0042     SRI(AFMT_GENERIC_6, DIG, id), \
0043     SRI(AFMT_GENERIC_7, DIG, id), \
0044     SRI(AFMT_GENERIC_HDR, DIG, id), \
0045     SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
0046     SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
0047     SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
0048     SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
0049     SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
0050     SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
0051     SRI(AFMT_60958_0, DIG, id), \
0052     SRI(AFMT_60958_1, DIG, id), \
0053     SRI(AFMT_60958_2, DIG, id), \
0054     SRI(DIG_FE_CNTL, DIG, id), \
0055     SRI(DIG_FIFO_STATUS, DIG, id), \
0056     SRI(HDMI_CONTROL, DIG, id), \
0057     SRI(HDMI_DB_CONTROL, DIG, id), \
0058     SRI(HDMI_GC, DIG, id), \
0059     SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
0060     SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
0061     SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
0062     SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
0063     SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
0064     SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
0065     SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
0066     SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
0067     SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
0068     SRI(HDMI_ACR_32_0, DIG, id),\
0069     SRI(HDMI_ACR_32_1, DIG, id),\
0070     SRI(HDMI_ACR_44_0, DIG, id),\
0071     SRI(HDMI_ACR_44_1, DIG, id),\
0072     SRI(HDMI_ACR_48_0, DIG, id),\
0073     SRI(HDMI_ACR_48_1, DIG, id),\
0074     SRI(DP_DB_CNTL, DP, id), \
0075     SRI(DP_MSA_MISC, DP, id), \
0076     SRI(DP_MSA_VBID_MISC, DP, id), \
0077     SRI(DP_MSA_COLORIMETRY, DP, id), \
0078     SRI(DP_MSA_TIMING_PARAM1, DP, id), \
0079     SRI(DP_MSA_TIMING_PARAM2, DP, id), \
0080     SRI(DP_MSA_TIMING_PARAM3, DP, id), \
0081     SRI(DP_MSA_TIMING_PARAM4, DP, id), \
0082     SRI(DP_MSE_RATE_CNTL, DP, id), \
0083     SRI(DP_MSE_RATE_UPDATE, DP, id), \
0084     SRI(DP_PIXEL_FORMAT, DP, id), \
0085     SRI(DP_SEC_CNTL, DP, id), \
0086     SRI(DP_SEC_CNTL1, DP, id), \
0087     SRI(DP_SEC_CNTL2, DP, id), \
0088     SRI(DP_SEC_CNTL5, DP, id), \
0089     SRI(DP_SEC_CNTL6, DP, id), \
0090     SRI(DP_STEER_FIFO, DP, id), \
0091     SRI(DP_VID_M, DP, id), \
0092     SRI(DP_VID_N, DP, id), \
0093     SRI(DP_VID_STREAM_CNTL, DP, id), \
0094     SRI(DP_VID_TIMING, DP, id), \
0095     SRI(DP_SEC_AUD_N, DP, id), \
0096     SRI(DP_SEC_AUD_N_READBACK, DP, id), \
0097     SRI(DP_SEC_AUD_M_READBACK, DP, id), \
0098     SRI(DP_SEC_TIMESTAMP, DP, id), \
0099     SRI(DIG_CLOCK_PATTERN, DIG, id)
0100 
0101 #define SE_DCN_REG_LIST(id)\
0102     SE_COMMON_DCN_REG_LIST(id)
0103 
0104 
0105 struct dcn10_stream_enc_registers {
0106     uint32_t AFMT_CNTL;
0107     uint32_t AFMT_AVI_INFO0;
0108     uint32_t AFMT_AVI_INFO1;
0109     uint32_t AFMT_AVI_INFO2;
0110     uint32_t AFMT_AVI_INFO3;
0111     uint32_t AFMT_GENERIC_0;
0112     uint32_t AFMT_GENERIC_1;
0113     uint32_t AFMT_GENERIC_2;
0114     uint32_t AFMT_GENERIC_3;
0115     uint32_t AFMT_GENERIC_4;
0116     uint32_t AFMT_GENERIC_5;
0117     uint32_t AFMT_GENERIC_6;
0118     uint32_t AFMT_GENERIC_7;
0119     uint32_t AFMT_GENERIC_HDR;
0120     uint32_t AFMT_INFOFRAME_CONTROL0;
0121     uint32_t AFMT_VBI_PACKET_CONTROL;
0122     uint32_t AFMT_VBI_PACKET_CONTROL1;
0123     uint32_t AFMT_AUDIO_PACKET_CONTROL;
0124     uint32_t AFMT_AUDIO_PACKET_CONTROL2;
0125     uint32_t AFMT_AUDIO_SRC_CONTROL;
0126     uint32_t AFMT_60958_0;
0127     uint32_t AFMT_60958_1;
0128     uint32_t AFMT_60958_2;
0129     uint32_t DIG_FE_CNTL;
0130     uint32_t DIG_FE_CNTL2;
0131     uint32_t DIG_FIFO_STATUS;
0132     uint32_t DP_MSE_RATE_CNTL;
0133     uint32_t DP_MSE_RATE_UPDATE;
0134     uint32_t DP_PIXEL_FORMAT;
0135     uint32_t DP_SEC_CNTL;
0136     uint32_t DP_SEC_CNTL1;
0137     uint32_t DP_SEC_CNTL2;
0138     uint32_t DP_SEC_CNTL5;
0139     uint32_t DP_SEC_CNTL6;
0140     uint32_t DP_STEER_FIFO;
0141     uint32_t DP_VID_M;
0142     uint32_t DP_VID_N;
0143     uint32_t DP_VID_STREAM_CNTL;
0144     uint32_t DP_VID_TIMING;
0145     uint32_t DP_SEC_AUD_N;
0146     uint32_t DP_SEC_AUD_N_READBACK;
0147     uint32_t DP_SEC_AUD_M_READBACK;
0148     uint32_t DP_SEC_TIMESTAMP;
0149     uint32_t HDMI_CONTROL;
0150     uint32_t HDMI_GC;
0151     uint32_t HDMI_GENERIC_PACKET_CONTROL0;
0152     uint32_t HDMI_GENERIC_PACKET_CONTROL1;
0153     uint32_t HDMI_GENERIC_PACKET_CONTROL2;
0154     uint32_t HDMI_GENERIC_PACKET_CONTROL3;
0155     uint32_t HDMI_GENERIC_PACKET_CONTROL4;
0156     uint32_t HDMI_GENERIC_PACKET_CONTROL5;
0157     uint32_t HDMI_INFOFRAME_CONTROL0;
0158     uint32_t HDMI_INFOFRAME_CONTROL1;
0159     uint32_t HDMI_VBI_PACKET_CONTROL;
0160     uint32_t HDMI_AUDIO_PACKET_CONTROL;
0161     uint32_t HDMI_ACR_PACKET_CONTROL;
0162     uint32_t HDMI_ACR_32_0;
0163     uint32_t HDMI_ACR_32_1;
0164     uint32_t HDMI_ACR_44_0;
0165     uint32_t HDMI_ACR_44_1;
0166     uint32_t HDMI_ACR_48_0;
0167     uint32_t HDMI_ACR_48_1;
0168     uint32_t DP_DB_CNTL;
0169     uint32_t DP_MSA_MISC;
0170     uint32_t DP_MSA_VBID_MISC;
0171     uint32_t DP_MSA_COLORIMETRY;
0172     uint32_t DP_MSA_TIMING_PARAM1;
0173     uint32_t DP_MSA_TIMING_PARAM2;
0174     uint32_t DP_MSA_TIMING_PARAM3;
0175     uint32_t DP_MSA_TIMING_PARAM4;
0176     uint32_t HDMI_DB_CONTROL;
0177     uint32_t DP_DSC_CNTL;
0178     uint32_t DP_DSC_BYTES_PER_PIXEL;
0179     uint32_t DME_CONTROL;
0180     uint32_t DP_SEC_METADATA_TRANSMISSION;
0181     uint32_t HDMI_METADATA_PACKET_CONTROL;
0182     uint32_t DP_SEC_FRAMING4;
0183     uint32_t DP_GSP11_CNTL;
0184     uint32_t HDMI_GENERIC_PACKET_CONTROL6;
0185     uint32_t HDMI_GENERIC_PACKET_CONTROL7;
0186     uint32_t HDMI_GENERIC_PACKET_CONTROL8;
0187     uint32_t HDMI_GENERIC_PACKET_CONTROL9;
0188     uint32_t HDMI_GENERIC_PACKET_CONTROL10;
0189     uint32_t DIG_CLOCK_PATTERN;
0190     uint32_t DIG_FIFO_CTRL0;
0191 };
0192 
0193 
0194 #define SE_SF(reg_name, field_name, post_fix)\
0195     .field_name = reg_name ## __ ## field_name ## post_fix
0196 
0197 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
0198     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
0199     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
0200     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
0201     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
0202     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
0203     SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
0204     SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
0205     SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
0206     SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
0207     SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
0208     SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
0209     SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
0210     SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
0211     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
0212     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
0213     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
0214     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
0215     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
0216     SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
0217     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
0218     SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
0219     SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
0220     SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
0221     SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
0222     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
0223     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
0224     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
0225     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
0226     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
0227     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
0228     SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
0229     SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
0230     SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
0231     SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
0232     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
0233     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
0234     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
0235     SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
0236     SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
0237     SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
0238     SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
0239     SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
0240     SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
0241     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
0242     SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
0243     SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
0244     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
0245     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
0246     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
0247     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
0248     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
0249     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
0250     SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
0251     SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
0252     SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
0253     SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
0254     SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
0255     SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
0256     SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
0257     SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
0258     SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
0259     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
0260     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
0261     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
0262     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
0263     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
0264     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
0265     SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
0266     SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\
0267     SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\
0268     SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
0269     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
0270     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
0271     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
0272     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
0273     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
0274     SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
0275     SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
0276     SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
0277     SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
0278     SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
0279     SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
0280     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
0281     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
0282     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
0283     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
0284     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
0285     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
0286     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
0287     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
0288     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
0289     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
0290     SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
0291     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
0292     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
0293     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
0294     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
0295     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
0296     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
0297     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
0298     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
0299     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\
0300     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
0301     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
0302     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
0303     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
0304     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
0305     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
0306     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
0307     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
0308     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
0309     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
0310     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
0311     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
0312     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
0313     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
0314     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
0315     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
0316     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
0317     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
0318     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
0319     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
0320     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
0321     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
0322     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
0323     SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\
0324     SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
0325     SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
0326     SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
0327     SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
0328     SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
0329     SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
0330     SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
0331     SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
0332     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
0333     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
0334     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
0335     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
0336     SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
0337     SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
0338     SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
0339     SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
0340     SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
0341     SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
0342 
0343 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
0344     SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
0345     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
0346     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
0347     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
0348     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
0349     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
0350     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
0351 
0352 
0353 #define SE_REG_FIELD_LIST_DCN1_0(type) \
0354     type AFMT_GENERIC_INDEX;\
0355     type AFMT_GENERIC_HB0;\
0356     type AFMT_GENERIC_HB1;\
0357     type AFMT_GENERIC_HB2;\
0358     type AFMT_GENERIC_HB3;\
0359     type AFMT_GENERIC_LOCK_STATUS;\
0360     type AFMT_GENERIC_CONFLICT;\
0361     type AFMT_GENERIC_CONFLICT_CLR;\
0362     type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
0363     type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
0364     type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
0365     type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
0366     type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
0367     type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\
0368     type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
0369     type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
0370     type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
0371     type AFMT_GENERIC0_FRAME_UPDATE;\
0372     type AFMT_GENERIC1_FRAME_UPDATE;\
0373     type AFMT_GENERIC2_FRAME_UPDATE;\
0374     type AFMT_GENERIC3_FRAME_UPDATE;\
0375     type AFMT_GENERIC4_FRAME_UPDATE;\
0376     type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
0377     type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
0378     type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
0379     type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
0380     type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
0381     type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
0382     type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
0383     type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
0384     type AFMT_GENERIC5_FRAME_UPDATE;\
0385     type AFMT_GENERIC6_FRAME_UPDATE;\
0386     type AFMT_GENERIC7_FRAME_UPDATE;\
0387     type HDMI_GENERIC0_CONT;\
0388     type HDMI_GENERIC0_SEND;\
0389     type HDMI_GENERIC0_LINE;\
0390     type HDMI_GENERIC1_CONT;\
0391     type HDMI_GENERIC1_SEND;\
0392     type HDMI_GENERIC1_LINE;\
0393     type HDMI_GENERIC2_CONT;\
0394     type HDMI_GENERIC2_SEND;\
0395     type HDMI_GENERIC2_LINE;\
0396     type HDMI_GENERIC3_CONT;\
0397     type HDMI_GENERIC3_SEND;\
0398     type HDMI_GENERIC3_LINE;\
0399     type HDMI_GENERIC4_CONT;\
0400     type HDMI_GENERIC4_SEND;\
0401     type HDMI_GENERIC4_LINE;\
0402     type HDMI_GENERIC5_CONT;\
0403     type HDMI_GENERIC5_SEND;\
0404     type HDMI_GENERIC5_LINE;\
0405     type HDMI_GENERIC6_CONT;\
0406     type HDMI_GENERIC6_SEND;\
0407     type HDMI_GENERIC6_LINE;\
0408     type HDMI_GENERIC7_CONT;\
0409     type HDMI_GENERIC7_SEND;\
0410     type HDMI_GENERIC7_LINE;\
0411     type DP_PIXEL_ENCODING;\
0412     type DP_COMPONENT_DEPTH;\
0413     type HDMI_PACKET_GEN_VERSION;\
0414     type HDMI_KEEPOUT_MODE;\
0415     type HDMI_DEEP_COLOR_ENABLE;\
0416     type HDMI_CLOCK_CHANNEL_RATE;\
0417     type HDMI_DEEP_COLOR_DEPTH;\
0418     type HDMI_GC_CONT;\
0419     type HDMI_GC_SEND;\
0420     type HDMI_NULL_SEND;\
0421     type HDMI_DATA_SCRAMBLE_EN;\
0422     type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
0423     type HDMI_AUDIO_INFO_SEND;\
0424     type AFMT_AUDIO_INFO_UPDATE;\
0425     type HDMI_AUDIO_INFO_LINE;\
0426     type HDMI_GC_AVMUTE;\
0427     type DP_MSE_RATE_X;\
0428     type DP_MSE_RATE_Y;\
0429     type DP_MSE_RATE_UPDATE_PENDING;\
0430     type DP_SEC_GSP0_ENABLE;\
0431     type DP_SEC_STREAM_ENABLE;\
0432     type DP_SEC_GSP1_ENABLE;\
0433     type DP_SEC_GSP2_ENABLE;\
0434     type DP_SEC_GSP3_ENABLE;\
0435     type DP_SEC_GSP4_ENABLE;\
0436     type DP_SEC_GSP5_ENABLE;\
0437     type DP_SEC_GSP5_LINE_NUM;\
0438     type DP_SEC_GSP5_LINE_REFERENCE;\
0439     type DP_SEC_GSP6_ENABLE;\
0440     type DP_SEC_GSP7_ENABLE;\
0441     type DP_SEC_GSP7_PPS;\
0442     type DP_SEC_GSP7_SEND;\
0443     type DP_SEC_GSP4_SEND;\
0444     type DP_SEC_GSP4_SEND_PENDING;\
0445     type DP_SEC_GSP4_LINE_NUM;\
0446     type DP_SEC_GSP4_SEND_ANY_LINE;\
0447     type DP_SEC_MPG_ENABLE;\
0448     type DP_VID_STREAM_DIS_DEFER;\
0449     type DP_VID_STREAM_ENABLE;\
0450     type DP_VID_STREAM_STATUS;\
0451     type DP_STEER_FIFO_RESET;\
0452     type DP_VID_M_N_GEN_EN;\
0453     type DP_VID_N;\
0454     type DP_VID_M;\
0455     type DIG_START;\
0456     type AFMT_AUDIO_SRC_SELECT;\
0457     type AFMT_AUDIO_CHANNEL_ENABLE;\
0458     type HDMI_AUDIO_PACKETS_PER_LINE;\
0459     type HDMI_AUDIO_DELAY_EN;\
0460     type AFMT_60958_CS_UPDATE;\
0461     type AFMT_AUDIO_LAYOUT_OVRD;\
0462     type AFMT_60958_OSF_OVRD;\
0463     type HDMI_ACR_AUTO_SEND;\
0464     type HDMI_ACR_SOURCE;\
0465     type HDMI_ACR_AUDIO_PRIORITY;\
0466     type HDMI_ACR_CTS_32;\
0467     type HDMI_ACR_N_32;\
0468     type HDMI_ACR_CTS_44;\
0469     type HDMI_ACR_N_44;\
0470     type HDMI_ACR_CTS_48;\
0471     type HDMI_ACR_N_48;\
0472     type AFMT_60958_CS_CHANNEL_NUMBER_L;\
0473     type AFMT_60958_CS_CLOCK_ACCURACY;\
0474     type AFMT_60958_CS_CHANNEL_NUMBER_R;\
0475     type AFMT_60958_CS_CHANNEL_NUMBER_2;\
0476     type AFMT_60958_CS_CHANNEL_NUMBER_3;\
0477     type AFMT_60958_CS_CHANNEL_NUMBER_4;\
0478     type AFMT_60958_CS_CHANNEL_NUMBER_5;\
0479     type AFMT_60958_CS_CHANNEL_NUMBER_6;\
0480     type AFMT_60958_CS_CHANNEL_NUMBER_7;\
0481     type DP_SEC_AUD_N;\
0482     type DP_SEC_AUD_N_READBACK;\
0483     type DP_SEC_AUD_M_READBACK;\
0484     type DP_SEC_TIMESTAMP_MODE;\
0485     type DP_SEC_ASP_ENABLE;\
0486     type DP_SEC_ATP_ENABLE;\
0487     type DP_SEC_AIP_ENABLE;\
0488     type DP_SEC_ACM_ENABLE;\
0489     type DP_SEC_GSP7_LINE_NUM;\
0490     type AFMT_AUDIO_SAMPLE_SEND;\
0491     type AFMT_AUDIO_CLOCK_EN;\
0492     type TMDS_PIXEL_ENCODING;\
0493     type TMDS_COLOR_FORMAT;\
0494     type DIG_STEREOSYNC_SELECT;\
0495     type DIG_STEREOSYNC_GATE_EN;\
0496     type DP_DB_DISABLE;\
0497     type DP_MSA_MISC0;\
0498     type DP_MSA_HTOTAL;\
0499     type DP_MSA_VTOTAL;\
0500     type DP_MSA_HSTART;\
0501     type DP_MSA_VSTART;\
0502     type DP_MSA_HSYNCWIDTH;\
0503     type DP_MSA_HSYNCPOLARITY;\
0504     type DP_MSA_VSYNCWIDTH;\
0505     type DP_MSA_VSYNCPOLARITY;\
0506     type DP_MSA_HWIDTH;\
0507     type DP_MSA_VHEIGHT;\
0508     type HDMI_DB_DISABLE;\
0509     type DP_VID_N_MUL;\
0510     type DP_VID_M_DOUBLE_VALUE_EN;\
0511     type DIG_SOURCE_SELECT;\
0512     type DIG_FIFO_LEVEL_ERROR;\
0513     type DIG_FIFO_USE_OVERWRITE_LEVEL;\
0514     type DIG_FIFO_OVERWRITE_LEVEL;\
0515     type DIG_FIFO_ERROR_ACK;\
0516     type DIG_FIFO_CAL_AVERAGE_LEVEL;\
0517     type DIG_FIFO_MAXIMUM_LEVEL;\
0518     type DIG_FIFO_MINIMUM_LEVEL;\
0519     type DIG_FIFO_READ_CLOCK_SRC;\
0520     type DIG_FIFO_CALIBRATED;\
0521     type DIG_FIFO_FORCE_RECAL_AVERAGE;\
0522     type DIG_FIFO_FORCE_RECOMP_MINMAX;\
0523     type DIG_CLOCK_PATTERN
0524 
0525 #define SE_REG_FIELD_LIST_DCN2_0(type) \
0526     type DP_DSC_MODE;\
0527     type DP_DSC_SLICE_WIDTH;\
0528     type DP_DSC_BYTES_PER_PIXEL;\
0529     type DP_VBID6_LINE_REFERENCE;\
0530     type DP_VBID6_LINE_NUM;\
0531     type METADATA_ENGINE_EN;\
0532     type METADATA_HUBP_REQUESTOR_ID;\
0533     type METADATA_STREAM_TYPE;\
0534     type DP_SEC_METADATA_PACKET_ENABLE;\
0535     type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\
0536     type DP_SEC_METADATA_PACKET_LINE;\
0537     type HDMI_METADATA_PACKET_ENABLE;\
0538     type HDMI_METADATA_PACKET_LINE_REFERENCE;\
0539     type HDMI_METADATA_PACKET_LINE;\
0540     type DOLBY_VISION_EN;\
0541     type DP_PIXEL_COMBINE;\
0542     type DP_SST_SDP_SPLITTING
0543 
0544 #define SE_REG_FIELD_LIST_DCN3_0(type) \
0545     type HDMI_GENERIC8_CONT;\
0546     type HDMI_GENERIC8_SEND;\
0547     type HDMI_GENERIC8_LINE;\
0548     type HDMI_GENERIC9_CONT;\
0549     type HDMI_GENERIC9_SEND;\
0550     type HDMI_GENERIC9_LINE;\
0551     type HDMI_GENERIC10_CONT;\
0552     type HDMI_GENERIC10_SEND;\
0553     type HDMI_GENERIC10_LINE;\
0554     type HDMI_GENERIC11_CONT;\
0555     type HDMI_GENERIC11_SEND;\
0556     type HDMI_GENERIC11_LINE;\
0557     type HDMI_GENERIC12_CONT;\
0558     type HDMI_GENERIC12_SEND;\
0559     type HDMI_GENERIC12_LINE;\
0560     type HDMI_GENERIC13_CONT;\
0561     type HDMI_GENERIC13_SEND;\
0562     type HDMI_GENERIC13_LINE;\
0563     type HDMI_GENERIC14_CONT;\
0564     type HDMI_GENERIC14_SEND;\
0565     type HDMI_GENERIC14_LINE;\
0566     type DP_SEC_GSP11_PPS;\
0567     type DP_SEC_GSP11_ENABLE;\
0568     type DP_SEC_GSP11_LINE_NUM
0569 
0570 #define SE_REG_FIELD_LIST_DCN3_2(type) \
0571     type DIG_FIFO_OUTPUT_PIXEL_MODE;\
0572     type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\
0573     type DIG_SYMCLK_FE_ON;\
0574     type DIG_FIFO_READ_START_LEVEL;\
0575     type DIG_FIFO_ENABLE;\
0576     type DIG_FIFO_RESET;\
0577     type DIG_FIFO_RESET_DONE
0578 
0579 struct dcn10_stream_encoder_shift {
0580     SE_REG_FIELD_LIST_DCN1_0(uint8_t);
0581     uint8_t HDMI_ACP_SEND;
0582     SE_REG_FIELD_LIST_DCN2_0(uint8_t);
0583     SE_REG_FIELD_LIST_DCN3_0(uint8_t);
0584     SE_REG_FIELD_LIST_DCN3_2(uint8_t);
0585 
0586 };
0587 
0588 struct dcn10_stream_encoder_mask {
0589     SE_REG_FIELD_LIST_DCN1_0(uint32_t);
0590     uint32_t HDMI_ACP_SEND;
0591     SE_REG_FIELD_LIST_DCN2_0(uint32_t);
0592     SE_REG_FIELD_LIST_DCN3_0(uint32_t);
0593     SE_REG_FIELD_LIST_DCN3_2(uint32_t);
0594 
0595 };
0596 
0597 struct dcn10_stream_encoder {
0598     struct stream_encoder base;
0599     const struct dcn10_stream_enc_registers *regs;
0600     const struct dcn10_stream_encoder_shift *se_shift;
0601     const struct dcn10_stream_encoder_mask *se_mask;
0602 };
0603 
0604 void dcn10_stream_encoder_construct(
0605     struct dcn10_stream_encoder *enc1,
0606     struct dc_context *ctx,
0607     struct dc_bios *bp,
0608     enum engine_id eng_id,
0609     const struct dcn10_stream_enc_registers *regs,
0610     const struct dcn10_stream_encoder_shift *se_shift,
0611     const struct dcn10_stream_encoder_mask *se_mask);
0612 
0613 void enc1_update_generic_info_packet(
0614     struct dcn10_stream_encoder *enc1,
0615     uint32_t packet_index,
0616     const struct dc_info_packet *info_packet);
0617 
0618 void enc1_stream_encoder_dp_set_stream_attribute(
0619     struct stream_encoder *enc,
0620     struct dc_crtc_timing *crtc_timing,
0621     enum dc_color_space output_color_space,
0622     bool use_vsc_sdp_for_colorimetry,
0623     uint32_t enable_sdp_splitting);
0624 
0625 void enc1_stream_encoder_hdmi_set_stream_attribute(
0626     struct stream_encoder *enc,
0627     struct dc_crtc_timing *crtc_timing,
0628     int actual_pix_clk_khz,
0629     bool enable_audio);
0630 
0631 void enc1_stream_encoder_dvi_set_stream_attribute(
0632     struct stream_encoder *enc,
0633     struct dc_crtc_timing *crtc_timing,
0634     bool is_dual_link);
0635 
0636 void enc1_stream_encoder_set_throttled_vcp_size(
0637     struct stream_encoder *enc,
0638     struct fixed31_32 avg_time_slots_per_mtp);
0639 
0640 void enc1_stream_encoder_update_dp_info_packets(
0641     struct stream_encoder *enc,
0642     const struct encoder_info_frame *info_frame);
0643 
0644 void enc1_stream_encoder_send_immediate_sdp_message(
0645     struct stream_encoder *enc,
0646     const uint8_t *custom_sdp_message,
0647                 unsigned int sdp_message_size);
0648 
0649 void enc1_stream_encoder_stop_dp_info_packets(
0650     struct stream_encoder *enc);
0651 
0652 void enc1_stream_encoder_reset_fifo(
0653     struct stream_encoder *enc);
0654 
0655 void enc1_stream_encoder_dp_blank(
0656     struct dc_link *link,
0657     struct stream_encoder *enc);
0658 
0659 void enc1_stream_encoder_dp_unblank(
0660     struct dc_link *link,
0661     struct stream_encoder *enc,
0662     const struct encoder_unblank_param *param);
0663 
0664 void enc1_setup_stereo_sync(
0665     struct stream_encoder *enc,
0666     int tg_inst, bool enable);
0667 
0668 void enc1_stream_encoder_set_avmute(
0669     struct stream_encoder *enc,
0670     bool enable);
0671 
0672 void enc1_se_audio_mute_control(
0673     struct stream_encoder *enc,
0674     bool mute);
0675 
0676 void enc1_se_dp_audio_setup(
0677     struct stream_encoder *enc,
0678     unsigned int az_inst,
0679     struct audio_info *info);
0680 
0681 void enc1_se_dp_audio_enable(
0682     struct stream_encoder *enc);
0683 
0684 void enc1_se_dp_audio_disable(
0685     struct stream_encoder *enc);
0686 
0687 void enc1_se_hdmi_audio_setup(
0688     struct stream_encoder *enc,
0689     unsigned int az_inst,
0690     struct audio_info *info,
0691     struct audio_crtc_info *audio_crtc_info);
0692 
0693 void enc1_se_hdmi_audio_disable(
0694     struct stream_encoder *enc);
0695 
0696 void enc1_dig_connect_to_otg(
0697     struct stream_encoder *enc,
0698     int tg_inst);
0699 
0700 unsigned int enc1_dig_source_otg(
0701     struct stream_encoder *enc);
0702 
0703 void enc1_stream_encoder_set_stream_attribute_helper(
0704     struct dcn10_stream_encoder *enc1,
0705     struct dc_crtc_timing *crtc_timing);
0706 
0707 void enc1_se_enable_audio_clock(
0708     struct stream_encoder *enc,
0709     bool enable);
0710 
0711 void enc1_se_enable_dp_audio(
0712     struct stream_encoder *enc);
0713 
0714 void get_audio_clock_info(
0715     enum dc_color_depth color_depth,
0716     uint32_t crtc_pixel_clock_100Hz,
0717     uint32_t actual_pixel_clock_100Hz,
0718     struct audio_clock_info *audio_clock_info);
0719 
0720 void enc1_reset_hdmi_stream_attribute(
0721     struct stream_encoder *enc);
0722 
0723 bool enc1_stream_encoder_dp_get_pixel_format(
0724     struct stream_encoder *enc,
0725     enum dc_pixel_encoding *encoding,
0726     enum dc_color_depth *depth);
0727 
0728 #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
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