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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 #include "dc_bios_types.h"
0028 #include "dcn10_stream_encoder.h"
0029 #include "reg_helper.h"
0030 #include "hw_shared.h"
0031 #include "inc/link_dpcd.h"
0032 #include "dpcd_defs.h"
0033 #include "dcn30/dcn30_afmt.h"
0034 
0035 #define DC_LOGGER \
0036         enc1->base.ctx->logger
0037 
0038 #define REG(reg)\
0039     (enc1->regs->reg)
0040 
0041 #undef FN
0042 #define FN(reg_name, field_name) \
0043     enc1->se_shift->field_name, enc1->se_mask->field_name
0044 
0045 #define VBI_LINE_0 0
0046 #define DP_BLANK_MAX_RETRY 20
0047 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
0048 
0049 
0050 enum {
0051     DP_MST_UPDATE_MAX_RETRY = 50
0052 };
0053 
0054 #define CTX \
0055     enc1->base.ctx
0056 
0057 void enc1_update_generic_info_packet(
0058     struct dcn10_stream_encoder *enc1,
0059     uint32_t packet_index,
0060     const struct dc_info_packet *info_packet)
0061 {
0062     /* TODOFPGA Figure out a proper number for max_retries polling for lock
0063      * use 50 for now.
0064      */
0065     uint32_t max_retries = 50;
0066 
0067     /*we need turn on clock before programming AFMT block*/
0068     REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0069 
0070     if (packet_index >= 8)
0071         ASSERT(0);
0072 
0073     /* poll dig_update_lock is not locked -> asic internal signal
0074      * assume otg master lock will unlock it
0075      */
0076 /*      REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
0077             0, 10, max_retries);*/
0078 
0079     /* check if HW reading GSP memory */
0080     REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
0081             0, 10, max_retries);
0082 
0083     /* HW does is not reading GSP memory not reading too long ->
0084      * something wrong. clear GPS memory access and notify?
0085      * hw SW is writing to GSP memory
0086      */
0087     REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
0088 
0089     /* choose which generic packet to use */
0090     REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
0091             AFMT_GENERIC_INDEX, packet_index);
0092 
0093     /* write generic packet header
0094      * (4th byte is for GENERIC0 only)
0095      */
0096     REG_SET_4(AFMT_GENERIC_HDR, 0,
0097             AFMT_GENERIC_HB0, info_packet->hb0,
0098             AFMT_GENERIC_HB1, info_packet->hb1,
0099             AFMT_GENERIC_HB2, info_packet->hb2,
0100             AFMT_GENERIC_HB3, info_packet->hb3);
0101 
0102     /* write generic packet contents
0103      * (we never use last 4 bytes)
0104      * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
0105      */
0106     {
0107         const uint32_t *content =
0108             (const uint32_t *) &info_packet->sb[0];
0109 
0110         REG_WRITE(AFMT_GENERIC_0, *content++);
0111         REG_WRITE(AFMT_GENERIC_1, *content++);
0112         REG_WRITE(AFMT_GENERIC_2, *content++);
0113         REG_WRITE(AFMT_GENERIC_3, *content++);
0114         REG_WRITE(AFMT_GENERIC_4, *content++);
0115         REG_WRITE(AFMT_GENERIC_5, *content++);
0116         REG_WRITE(AFMT_GENERIC_6, *content++);
0117         REG_WRITE(AFMT_GENERIC_7, *content);
0118     }
0119 
0120     switch (packet_index) {
0121     case 0:
0122         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0123                 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
0124         break;
0125     case 1:
0126         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0127                 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
0128         break;
0129     case 2:
0130         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0131                 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
0132         break;
0133     case 3:
0134         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0135                 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
0136         break;
0137     case 4:
0138         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0139                 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
0140         break;
0141     case 5:
0142         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0143                 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
0144         break;
0145     case 6:
0146         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0147                 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
0148         break;
0149     case 7:
0150         REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0151                 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
0152         break;
0153     default:
0154         break;
0155     }
0156 }
0157 
0158 static void enc1_update_hdmi_info_packet(
0159     struct dcn10_stream_encoder *enc1,
0160     uint32_t packet_index,
0161     const struct dc_info_packet *info_packet)
0162 {
0163     uint32_t cont, send, line;
0164 
0165     if (info_packet->valid) {
0166         enc1_update_generic_info_packet(
0167             enc1,
0168             packet_index,
0169             info_packet);
0170 
0171         /* enable transmission of packet(s) -
0172          * packet transmission begins on the next frame
0173          */
0174         cont = 1;
0175         /* send packet(s) every frame */
0176         send = 1;
0177         /* select line number to send packets on */
0178         line = 2;
0179     } else {
0180         cont = 0;
0181         send = 0;
0182         line = 0;
0183     }
0184 
0185     /* choose which generic packet control to use */
0186     switch (packet_index) {
0187     case 0:
0188         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
0189                 HDMI_GENERIC0_CONT, cont,
0190                 HDMI_GENERIC0_SEND, send,
0191                 HDMI_GENERIC0_LINE, line);
0192         break;
0193     case 1:
0194         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
0195                 HDMI_GENERIC1_CONT, cont,
0196                 HDMI_GENERIC1_SEND, send,
0197                 HDMI_GENERIC1_LINE, line);
0198         break;
0199     case 2:
0200         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
0201                 HDMI_GENERIC0_CONT, cont,
0202                 HDMI_GENERIC0_SEND, send,
0203                 HDMI_GENERIC0_LINE, line);
0204         break;
0205     case 3:
0206         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
0207                 HDMI_GENERIC1_CONT, cont,
0208                 HDMI_GENERIC1_SEND, send,
0209                 HDMI_GENERIC1_LINE, line);
0210         break;
0211     case 4:
0212         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
0213                 HDMI_GENERIC0_CONT, cont,
0214                 HDMI_GENERIC0_SEND, send,
0215                 HDMI_GENERIC0_LINE, line);
0216         break;
0217     case 5:
0218         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
0219                 HDMI_GENERIC1_CONT, cont,
0220                 HDMI_GENERIC1_SEND, send,
0221                 HDMI_GENERIC1_LINE, line);
0222         break;
0223     case 6:
0224         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
0225                 HDMI_GENERIC0_CONT, cont,
0226                 HDMI_GENERIC0_SEND, send,
0227                 HDMI_GENERIC0_LINE, line);
0228         break;
0229     case 7:
0230         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
0231                 HDMI_GENERIC1_CONT, cont,
0232                 HDMI_GENERIC1_SEND, send,
0233                 HDMI_GENERIC1_LINE, line);
0234         break;
0235     default:
0236         /* invalid HW packet index */
0237         DC_LOG_WARNING(
0238             "Invalid HW packet index: %s()\n",
0239             __func__);
0240         return;
0241     }
0242 }
0243 
0244 /* setup stream encoder in dp mode */
0245 void enc1_stream_encoder_dp_set_stream_attribute(
0246     struct stream_encoder *enc,
0247     struct dc_crtc_timing *crtc_timing,
0248     enum dc_color_space output_color_space,
0249     bool use_vsc_sdp_for_colorimetry,
0250     uint32_t enable_sdp_splitting)
0251 {
0252     uint32_t h_active_start;
0253     uint32_t v_active_start;
0254     uint32_t misc0 = 0;
0255     uint32_t misc1 = 0;
0256     uint32_t h_blank;
0257     uint32_t h_back_porch;
0258     uint8_t synchronous_clock = 0; /* asynchronous mode */
0259     uint8_t colorimetry_bpc;
0260     uint8_t dp_pixel_encoding = 0;
0261     uint8_t dp_component_depth = 0;
0262 
0263     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0264     struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
0265 
0266     if (hw_crtc_timing.flags.INTERLACE) {
0267         /*the input timing is in VESA spec format with Interlace flag =1*/
0268         hw_crtc_timing.v_total /= 2;
0269         hw_crtc_timing.v_border_top /= 2;
0270         hw_crtc_timing.v_addressable /= 2;
0271         hw_crtc_timing.v_border_bottom /= 2;
0272         hw_crtc_timing.v_front_porch /= 2;
0273         hw_crtc_timing.v_sync_width /= 2;
0274     }
0275 
0276 
0277     /* set pixel encoding */
0278     switch (hw_crtc_timing.pixel_encoding) {
0279     case PIXEL_ENCODING_YCBCR422:
0280         dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
0281         break;
0282     case PIXEL_ENCODING_YCBCR444:
0283         dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
0284 
0285         if (hw_crtc_timing.flags.Y_ONLY)
0286             if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
0287                 /* HW testing only, no use case yet.
0288                  * Color depth of Y-only could be
0289                  * 8, 10, 12, 16 bits
0290                  */
0291                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
0292 
0293         /* Note: DP_MSA_MISC1 bit 7 is the indicator
0294          * of Y-only mode.
0295          * This bit is set in HW if register
0296          * DP_PIXEL_ENCODING is programmed to 0x4
0297          */
0298         break;
0299     case PIXEL_ENCODING_YCBCR420:
0300         dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
0301         break;
0302     default:
0303         dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
0304         break;
0305     }
0306 
0307     misc1 = REG_READ(DP_MSA_MISC);
0308     /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
0309      * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
0310      * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
0311      * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
0312      */
0313     if (use_vsc_sdp_for_colorimetry)
0314         misc1 = misc1 | 0x40;
0315     else
0316         misc1 = misc1 & ~0x40;
0317 
0318     /* set color depth */
0319     switch (hw_crtc_timing.display_color_depth) {
0320     case COLOR_DEPTH_666:
0321         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
0322         break;
0323     case COLOR_DEPTH_888:
0324         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
0325         break;
0326     case COLOR_DEPTH_101010:
0327         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
0328         break;
0329     case COLOR_DEPTH_121212:
0330         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
0331         break;
0332     case COLOR_DEPTH_161616:
0333         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
0334         break;
0335     default:
0336         dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
0337         break;
0338     }
0339 
0340     /* Set DP pixel encoding and component depth */
0341     REG_UPDATE_2(DP_PIXEL_FORMAT,
0342             DP_PIXEL_ENCODING, dp_pixel_encoding,
0343             DP_COMPONENT_DEPTH, dp_component_depth);
0344 
0345     /* set dynamic range and YCbCr range */
0346 
0347     switch (hw_crtc_timing.display_color_depth) {
0348     case COLOR_DEPTH_666:
0349         colorimetry_bpc = 0;
0350         break;
0351     case COLOR_DEPTH_888:
0352         colorimetry_bpc = 1;
0353         break;
0354     case COLOR_DEPTH_101010:
0355         colorimetry_bpc = 2;
0356         break;
0357     case COLOR_DEPTH_121212:
0358         colorimetry_bpc = 3;
0359         break;
0360     default:
0361         colorimetry_bpc = 0;
0362         break;
0363     }
0364 
0365     misc0 = misc0 | synchronous_clock;
0366     misc0 = colorimetry_bpc << 5;
0367 
0368     switch (output_color_space) {
0369     case COLOR_SPACE_SRGB:
0370         misc1 = misc1 & ~0x80; /* bit7 = 0*/
0371         break;
0372     case COLOR_SPACE_SRGB_LIMITED:
0373         misc0 = misc0 | 0x8; /* bit3=1 */
0374         misc1 = misc1 & ~0x80; /* bit7 = 0*/
0375         break;
0376     case COLOR_SPACE_YCBCR601:
0377     case COLOR_SPACE_YCBCR601_LIMITED:
0378         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
0379         misc1 = misc1 & ~0x80; /* bit7 = 0*/
0380         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
0381             misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
0382         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
0383             misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
0384         break;
0385     case COLOR_SPACE_YCBCR709:
0386     case COLOR_SPACE_YCBCR709_LIMITED:
0387         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
0388         misc1 = misc1 & ~0x80; /* bit7 = 0*/
0389         if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
0390             misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
0391         else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
0392             misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
0393         break;
0394     case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
0395     case COLOR_SPACE_2020_RGB_FULLRANGE:
0396     case COLOR_SPACE_2020_YCBCR:
0397     case COLOR_SPACE_XR_RGB:
0398     case COLOR_SPACE_MSREF_SCRGB:
0399     case COLOR_SPACE_ADOBERGB:
0400     case COLOR_SPACE_DCIP3:
0401     case COLOR_SPACE_XV_YCC_709:
0402     case COLOR_SPACE_XV_YCC_601:
0403     case COLOR_SPACE_DISPLAYNATIVE:
0404     case COLOR_SPACE_DOLBYVISION:
0405     case COLOR_SPACE_APPCTRL:
0406     case COLOR_SPACE_CUSTOMPOINTS:
0407     case COLOR_SPACE_UNKNOWN:
0408     case COLOR_SPACE_YCBCR709_BLACK:
0409         /* do nothing */
0410         break;
0411     }
0412 
0413     REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
0414     REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
0415 
0416     /* dcn new register
0417      * dc_crtc_timing is vesa dmt struct. data from edid
0418      */
0419     REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
0420             DP_MSA_HTOTAL, hw_crtc_timing.h_total,
0421             DP_MSA_VTOTAL, hw_crtc_timing.v_total);
0422 
0423     /* calculate from vesa timing parameters
0424      * h_active_start related to leading edge of sync
0425      */
0426 
0427     h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
0428             hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
0429 
0430     h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
0431             hw_crtc_timing.h_sync_width;
0432 
0433     /* start at beginning of left border */
0434     h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
0435 
0436 
0437     v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
0438             hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
0439             hw_crtc_timing.v_front_porch;
0440 
0441 
0442     /* start at beginning of left border */
0443     REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
0444         DP_MSA_HSTART, h_active_start,
0445         DP_MSA_VSTART, v_active_start);
0446 
0447     REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
0448             DP_MSA_HSYNCWIDTH,
0449             hw_crtc_timing.h_sync_width,
0450             DP_MSA_HSYNCPOLARITY,
0451             !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
0452             DP_MSA_VSYNCWIDTH,
0453             hw_crtc_timing.v_sync_width,
0454             DP_MSA_VSYNCPOLARITY,
0455             !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
0456 
0457     /* HWDITH include border or overscan */
0458     REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
0459         DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
0460         hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
0461         DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
0462         hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
0463 }
0464 
0465 void enc1_stream_encoder_set_stream_attribute_helper(
0466         struct dcn10_stream_encoder *enc1,
0467         struct dc_crtc_timing *crtc_timing)
0468 {
0469     switch (crtc_timing->pixel_encoding) {
0470     case PIXEL_ENCODING_YCBCR422:
0471         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
0472         break;
0473     default:
0474         REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
0475         break;
0476     }
0477     REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
0478 }
0479 
0480 /* setup stream encoder in hdmi mode */
0481 void enc1_stream_encoder_hdmi_set_stream_attribute(
0482     struct stream_encoder *enc,
0483     struct dc_crtc_timing *crtc_timing,
0484     int actual_pix_clk_khz,
0485     bool enable_audio)
0486 {
0487     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0488     struct bp_encoder_control cntl = {0};
0489 
0490     cntl.action = ENCODER_CONTROL_SETUP;
0491     cntl.engine_id = enc1->base.id;
0492     cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
0493     cntl.enable_dp_audio = enable_audio;
0494     cntl.pixel_clock = actual_pix_clk_khz;
0495     cntl.lanes_number = LANE_COUNT_FOUR;
0496 
0497     if (enc1->base.bp->funcs->encoder_control(
0498             enc1->base.bp, &cntl) != BP_RESULT_OK)
0499         return;
0500 
0501     enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
0502 
0503     /* setup HDMI engine */
0504     REG_UPDATE_6(HDMI_CONTROL,
0505         HDMI_PACKET_GEN_VERSION, 1,
0506         HDMI_KEEPOUT_MODE, 1,
0507         HDMI_DEEP_COLOR_ENABLE, 0,
0508         HDMI_DATA_SCRAMBLE_EN, 0,
0509         HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
0510         HDMI_CLOCK_CHANNEL_RATE, 0);
0511 
0512 
0513     switch (crtc_timing->display_color_depth) {
0514     case COLOR_DEPTH_888:
0515         REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
0516         DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
0517         break;
0518     case COLOR_DEPTH_101010:
0519         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0520             REG_UPDATE_2(HDMI_CONTROL,
0521                     HDMI_DEEP_COLOR_DEPTH, 1,
0522                     HDMI_DEEP_COLOR_ENABLE, 0);
0523             DC_LOG_DEBUG("HDMI source 30BPP deep color depth"  \
0524                 "disabled for YCBCR422 pixel encoding\n");
0525         } else {
0526             REG_UPDATE_2(HDMI_CONTROL,
0527                     HDMI_DEEP_COLOR_DEPTH, 1,
0528                     HDMI_DEEP_COLOR_ENABLE, 1);
0529             DC_LOG_DEBUG("HDMI source 30BPP deep color depth"  \
0530                 "enabled for YCBCR422 non-pixel encoding\n");
0531             }
0532         break;
0533     case COLOR_DEPTH_121212:
0534         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0535             REG_UPDATE_2(HDMI_CONTROL,
0536                     HDMI_DEEP_COLOR_DEPTH, 2,
0537                     HDMI_DEEP_COLOR_ENABLE, 0);
0538             DC_LOG_DEBUG("HDMI source 36BPP deep color depth"  \
0539                 "disabled for YCBCR422 pixel encoding\n");
0540         } else {
0541             REG_UPDATE_2(HDMI_CONTROL,
0542                     HDMI_DEEP_COLOR_DEPTH, 2,
0543                     HDMI_DEEP_COLOR_ENABLE, 1);
0544             DC_LOG_DEBUG("HDMI source 36BPP deep color depth"  \
0545                 "enabled for non-pixel YCBCR422 encoding\n");
0546             }
0547         break;
0548     case COLOR_DEPTH_161616:
0549         REG_UPDATE_2(HDMI_CONTROL,
0550                 HDMI_DEEP_COLOR_DEPTH, 3,
0551                 HDMI_DEEP_COLOR_ENABLE, 1);
0552         DC_LOG_DEBUG("HDMI source deep color depth enabled in"  \
0553                 "reserved mode\n");
0554         break;
0555     default:
0556         break;
0557     }
0558 
0559     if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
0560         /* enable HDMI data scrambler
0561          * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
0562          * Clock channel frequency is 1/4 of character rate.
0563          */
0564         REG_UPDATE_2(HDMI_CONTROL,
0565             HDMI_DATA_SCRAMBLE_EN, 1,
0566             HDMI_CLOCK_CHANNEL_RATE, 1);
0567     } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
0568 
0569         /* TODO: New feature for DCE11, still need to implement */
0570 
0571         /* enable HDMI data scrambler
0572          * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
0573          * Clock channel frequency is the same
0574          * as character rate
0575          */
0576         REG_UPDATE_2(HDMI_CONTROL,
0577             HDMI_DATA_SCRAMBLE_EN, 1,
0578             HDMI_CLOCK_CHANNEL_RATE, 0);
0579     }
0580 
0581 
0582     REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
0583         HDMI_GC_CONT, 1,
0584         HDMI_GC_SEND, 1,
0585         HDMI_NULL_SEND, 1);
0586 
0587     REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
0588 
0589     /* following belongs to audio */
0590     REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
0591 
0592     REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
0593 
0594     REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
0595                 VBI_LINE_0 + 2);
0596 
0597     REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
0598 }
0599 
0600 /* setup stream encoder in dvi mode */
0601 void enc1_stream_encoder_dvi_set_stream_attribute(
0602     struct stream_encoder *enc,
0603     struct dc_crtc_timing *crtc_timing,
0604     bool is_dual_link)
0605 {
0606     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0607     struct bp_encoder_control cntl = {0};
0608 
0609     cntl.action = ENCODER_CONTROL_SETUP;
0610     cntl.engine_id = enc1->base.id;
0611     cntl.signal = is_dual_link ?
0612             SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
0613     cntl.enable_dp_audio = false;
0614     cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
0615     cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
0616 
0617     if (enc1->base.bp->funcs->encoder_control(
0618             enc1->base.bp, &cntl) != BP_RESULT_OK)
0619         return;
0620 
0621     ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
0622     ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
0623     enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
0624 }
0625 
0626 void enc1_stream_encoder_set_throttled_vcp_size(
0627     struct stream_encoder *enc,
0628     struct fixed31_32 avg_time_slots_per_mtp)
0629 {
0630     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0631     uint32_t x = dc_fixpt_floor(
0632         avg_time_slots_per_mtp);
0633     uint32_t y = dc_fixpt_ceil(
0634         dc_fixpt_shl(
0635             dc_fixpt_sub_int(
0636                 avg_time_slots_per_mtp,
0637                 x),
0638             26));
0639 
0640     // If y rounds up to integer, carry it over to x.
0641     if (y >> 26) {
0642         x += 1;
0643         y = 0;
0644     }
0645 
0646     REG_SET_2(DP_MSE_RATE_CNTL, 0,
0647         DP_MSE_RATE_X, x,
0648         DP_MSE_RATE_Y, y);
0649 
0650     /* wait for update to be completed on the link */
0651     /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
0652     /* is reset to 0 (not pending) */
0653     REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
0654             0,
0655             10, DP_MST_UPDATE_MAX_RETRY);
0656 }
0657 
0658 static void enc1_stream_encoder_update_hdmi_info_packets(
0659     struct stream_encoder *enc,
0660     const struct encoder_info_frame *info_frame)
0661 {
0662     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0663 
0664     /* for bring up, disable dp double  TODO */
0665     REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
0666 
0667     /*Always add mandatory packets first followed by optional ones*/
0668     enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
0669     enc1_update_hdmi_info_packet(enc1, 1, &info_frame->hfvsif);
0670     enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
0671     enc1_update_hdmi_info_packet(enc1, 3, &info_frame->vendor);
0672     enc1_update_hdmi_info_packet(enc1, 4, &info_frame->spd);
0673     enc1_update_hdmi_info_packet(enc1, 5, &info_frame->hdrsmd);
0674 }
0675 
0676 static void enc1_stream_encoder_stop_hdmi_info_packets(
0677     struct stream_encoder *enc)
0678 {
0679     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0680 
0681     /* stop generic packets 0 & 1 on HDMI */
0682     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
0683         HDMI_GENERIC1_CONT, 0,
0684         HDMI_GENERIC1_LINE, 0,
0685         HDMI_GENERIC1_SEND, 0,
0686         HDMI_GENERIC0_CONT, 0,
0687         HDMI_GENERIC0_LINE, 0,
0688         HDMI_GENERIC0_SEND, 0);
0689 
0690     /* stop generic packets 2 & 3 on HDMI */
0691     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
0692         HDMI_GENERIC0_CONT, 0,
0693         HDMI_GENERIC0_LINE, 0,
0694         HDMI_GENERIC0_SEND, 0,
0695         HDMI_GENERIC1_CONT, 0,
0696         HDMI_GENERIC1_LINE, 0,
0697         HDMI_GENERIC1_SEND, 0);
0698 
0699     /* stop generic packets 2 & 3 on HDMI */
0700     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
0701         HDMI_GENERIC0_CONT, 0,
0702         HDMI_GENERIC0_LINE, 0,
0703         HDMI_GENERIC0_SEND, 0,
0704         HDMI_GENERIC1_CONT, 0,
0705         HDMI_GENERIC1_LINE, 0,
0706         HDMI_GENERIC1_SEND, 0);
0707 
0708     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
0709         HDMI_GENERIC0_CONT, 0,
0710         HDMI_GENERIC0_LINE, 0,
0711         HDMI_GENERIC0_SEND, 0,
0712         HDMI_GENERIC1_CONT, 0,
0713         HDMI_GENERIC1_LINE, 0,
0714         HDMI_GENERIC1_SEND, 0);
0715 }
0716 
0717 void enc1_stream_encoder_update_dp_info_packets(
0718     struct stream_encoder *enc,
0719     const struct encoder_info_frame *info_frame)
0720 {
0721     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0722     uint32_t value = 0;
0723 
0724     if (info_frame->vsc.valid)
0725         enc1_update_generic_info_packet(
0726                     enc1,
0727                     0,  /* packetIndex */
0728                     &info_frame->vsc);
0729 
0730     /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
0731      * Note that the enablement of GSP1 is not done below,
0732      * it's done in FW.
0733      */
0734     if (info_frame->vsc.valid)
0735         enc1_update_generic_info_packet(
0736                     enc1,
0737                     1,  /* packetIndex */
0738                     &info_frame->vsc);
0739 
0740     if (info_frame->spd.valid)
0741         enc1_update_generic_info_packet(
0742                 enc1,
0743                 2,  /* packetIndex */
0744                 &info_frame->spd);
0745 
0746     if (info_frame->hdrsmd.valid)
0747         enc1_update_generic_info_packet(
0748                 enc1,
0749                 3,  /* packetIndex */
0750                 &info_frame->hdrsmd);
0751 
0752     /* packetIndex 4 is used for send immediate sdp message, and please
0753      * use other packetIndex (such as 5,6) for other info packet
0754      */
0755 
0756     /* enable/disable transmission of packet(s).
0757      * If enabled, packet transmission begins on the next frame
0758      */
0759     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
0760     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
0761     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
0762 
0763     /* This bit is the master enable bit.
0764      * When enabling secondary stream engine,
0765      * this master bit must also be set.
0766      * This register shared with audio info frame.
0767      * Therefore we need to enable master bit
0768      * if at least on of the fields is not 0
0769      */
0770     value = REG_READ(DP_SEC_CNTL);
0771     if (value)
0772         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0773 }
0774 
0775 void enc1_stream_encoder_send_immediate_sdp_message(
0776     struct stream_encoder *enc,
0777     const uint8_t *custom_sdp_message,
0778     unsigned int sdp_message_size)
0779 {
0780     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0781     uint32_t value = 0;
0782 
0783     /* TODOFPGA Figure out a proper number for max_retries polling for lock
0784      * use 50 for now.
0785      */
0786     uint32_t max_retries = 50;
0787 
0788     /* check if GSP4 is transmitted */
0789     REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
0790         0, 10, max_retries);
0791 
0792     /* disable GSP4 transmitting */
0793     REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
0794 
0795     /* transmit GSP4 at the earliest time in a frame */
0796     REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
0797 
0798     /*we need turn on clock before programming AFMT block*/
0799     REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0800 
0801     /* check if HW reading GSP memory */
0802     REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
0803             0, 10, max_retries);
0804 
0805     /* HW does is not reading GSP memory not reading too long ->
0806      * something wrong. clear GPS memory access and notify?
0807      * hw SW is writing to GSP memory
0808      */
0809     REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
0810 
0811     /* use generic packet 4 for immediate sdp message */
0812     REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
0813             AFMT_GENERIC_INDEX, 4);
0814 
0815     /* write generic packet header
0816      * (4th byte is for GENERIC0 only)
0817      */
0818     REG_SET_4(AFMT_GENERIC_HDR, 0,
0819             AFMT_GENERIC_HB0, custom_sdp_message[0],
0820             AFMT_GENERIC_HB1, custom_sdp_message[1],
0821             AFMT_GENERIC_HB2, custom_sdp_message[2],
0822             AFMT_GENERIC_HB3, custom_sdp_message[3]);
0823 
0824     /* write generic packet contents
0825      * (we never use last 4 bytes)
0826      * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
0827      */
0828     {
0829         const uint32_t *content =
0830             (const uint32_t *) &custom_sdp_message[4];
0831 
0832         REG_WRITE(AFMT_GENERIC_0, *content++);
0833         REG_WRITE(AFMT_GENERIC_1, *content++);
0834         REG_WRITE(AFMT_GENERIC_2, *content++);
0835         REG_WRITE(AFMT_GENERIC_3, *content++);
0836         REG_WRITE(AFMT_GENERIC_4, *content++);
0837         REG_WRITE(AFMT_GENERIC_5, *content++);
0838         REG_WRITE(AFMT_GENERIC_6, *content++);
0839         REG_WRITE(AFMT_GENERIC_7, *content);
0840     }
0841 
0842     /* check whether GENERIC4 registers double buffer update in immediate mode
0843      * is pending
0844      */
0845     REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
0846             0, 10, max_retries);
0847 
0848     /* atomically update double-buffered GENERIC4 registers in immediate mode
0849      * (update immediately)
0850      */
0851     REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0852             AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
0853 
0854     /* enable GSP4 transmitting */
0855     REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
0856 
0857     /* This bit is the master enable bit.
0858      * When enabling secondary stream engine,
0859      * this master bit must also be set.
0860      * This register shared with audio info frame.
0861      * Therefore we need to enable master bit
0862      * if at least on of the fields is not 0
0863      */
0864     value = REG_READ(DP_SEC_CNTL);
0865     if (value)
0866         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0867 }
0868 
0869 void enc1_stream_encoder_stop_dp_info_packets(
0870     struct stream_encoder *enc)
0871 {
0872     /* stop generic packets on DP */
0873     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0874     uint32_t value = 0;
0875 
0876     REG_SET_10(DP_SEC_CNTL, 0,
0877         DP_SEC_GSP0_ENABLE, 0,
0878         DP_SEC_GSP1_ENABLE, 0,
0879         DP_SEC_GSP2_ENABLE, 0,
0880         DP_SEC_GSP3_ENABLE, 0,
0881         DP_SEC_GSP4_ENABLE, 0,
0882         DP_SEC_GSP5_ENABLE, 0,
0883         DP_SEC_GSP6_ENABLE, 0,
0884         DP_SEC_GSP7_ENABLE, 0,
0885         DP_SEC_MPG_ENABLE, 0,
0886         DP_SEC_STREAM_ENABLE, 0);
0887 
0888     /* this register shared with audio info frame.
0889      * therefore we need to keep master enabled
0890      * if at least one of the fields is not 0 */
0891     value = REG_READ(DP_SEC_CNTL);
0892     if (value)
0893         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0894 
0895 }
0896 
0897 void enc1_stream_encoder_dp_blank(
0898     struct dc_link *link,
0899     struct stream_encoder *enc)
0900 {
0901     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0902     uint32_t  reg1 = 0;
0903     uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
0904 
0905     /* Note: For CZ, we are changing driver default to disable
0906      * stream deferred to next VBLANK. If results are positive, we
0907      * will make the same change to all DCE versions. There are a
0908      * handful of panels that cannot handle disable stream at
0909      * HBLANK and will result in a white line flash across the
0910      * screen on stream disable.
0911      */
0912     REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
0913     if ((reg1 & 0x1) == 0)
0914         /*stream not enabled*/
0915         return;
0916     /* Specify the video stream disable point
0917      * (2 = start of the next vertical blank)
0918      */
0919     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
0920     /* Larger delay to wait until VBLANK - use max retry of
0921      * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
0922      * a little more because we may not trust delay accuracy.
0923      */
0924     max_retries = DP_BLANK_MAX_RETRY * 501;
0925 
0926     /* disable DP stream */
0927     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
0928 
0929     dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
0930 
0931     /* the encoder stops sending the video stream
0932      * at the start of the vertical blanking.
0933      * Poll for DP_VID_STREAM_STATUS == 0
0934      */
0935 
0936     REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
0937             0,
0938             10, max_retries);
0939 
0940     /* Tell the DP encoder to ignore timing from CRTC, must be done after
0941      * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
0942      * complete, stream status will be stuck in video stream enabled state,
0943      * i.e. DP_VID_STREAM_STATUS stuck at 1.
0944      */
0945 
0946     REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
0947 
0948     dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
0949 }
0950 
0951 /* output video stream to link encoder */
0952 void enc1_stream_encoder_dp_unblank(
0953     struct dc_link *link,
0954     struct stream_encoder *enc,
0955     const struct encoder_unblank_param *param)
0956 {
0957     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
0958 
0959     if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
0960         uint32_t n_vid = 0x8000;
0961         uint32_t m_vid;
0962         uint32_t n_multiply = 0;
0963         uint64_t m_vid_l = n_vid;
0964 
0965         /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
0966         if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
0967             /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
0968             n_multiply = 1;
0969         }
0970         /* M / N = Fstream / Flink
0971          * m_vid / n_vid = pixel rate / link rate
0972          */
0973 
0974         m_vid_l *= param->timing.pix_clk_100hz / 10;
0975         m_vid_l = div_u64(m_vid_l,
0976             param->link_settings.link_rate
0977                 * LINK_RATE_REF_FREQ_IN_KHZ);
0978 
0979         m_vid = (uint32_t) m_vid_l;
0980 
0981         /* enable auto measurement */
0982 
0983         REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
0984 
0985         /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
0986          * therefore program initial value for Mvid and Nvid
0987          */
0988 
0989         REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
0990 
0991         REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
0992 
0993         REG_UPDATE_2(DP_VID_TIMING,
0994                 DP_VID_M_N_GEN_EN, 1,
0995                 DP_VID_N_MUL, n_multiply);
0996     }
0997 
0998     /* set DIG_START to 0x1 to resync FIFO */
0999 
1000     REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1001 
1002     /* switch DP encoder to CRTC data */
1003 
1004     REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1005 
1006     /* wait 100us for DIG/DP logic to prime
1007      * (i.e. a few video lines)
1008      */
1009     udelay(100);
1010 
1011     /* the hardware would start sending video at the start of the next DP
1012      * frame (i.e. rising edge of the vblank).
1013      * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1014      * register has no effect on enable transition! HW always guarantees
1015      * VID_STREAM enable at start of next frame, and this is not
1016      * programmable
1017      */
1018 
1019     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1020 
1021     dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1022 }
1023 
1024 void enc1_stream_encoder_set_avmute(
1025     struct stream_encoder *enc,
1026     bool enable)
1027 {
1028     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1029     unsigned int value = enable ? 1 : 0;
1030 
1031     REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1032 }
1033 
1034 void enc1_reset_hdmi_stream_attribute(
1035     struct stream_encoder *enc)
1036 {
1037     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1038 
1039     REG_UPDATE_5(HDMI_CONTROL,
1040         HDMI_PACKET_GEN_VERSION, 1,
1041         HDMI_KEEPOUT_MODE, 1,
1042         HDMI_DEEP_COLOR_ENABLE, 0,
1043         HDMI_DATA_SCRAMBLE_EN, 0,
1044         HDMI_CLOCK_CHANNEL_RATE, 0);
1045 }
1046 
1047 
1048 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1049 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1050 
1051 #include "include/audio_types.h"
1052 
1053 
1054 /* 25.2MHz/1.001*/
1055 /* 25.2MHz/1.001*/
1056 /* 25.2MHz*/
1057 /* 27MHz */
1058 /* 27MHz*1.001*/
1059 /* 27MHz*1.001*/
1060 /* 54MHz*/
1061 /* 54MHz*1.001*/
1062 /* 74.25MHz/1.001*/
1063 /* 74.25MHz*/
1064 /* 148.5MHz/1.001*/
1065 /* 148.5MHz*/
1066 
1067 static const struct audio_clock_info audio_clock_info_table[16] = {
1068     {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1069     {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1070     {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1071     {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1072     {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1073     {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1074     {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1075     {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1076     {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1077     {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1078     {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1079     {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1080     {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1081     {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1082     {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1083     {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1084 };
1085 
1086 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1087     {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1088     {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1089     {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1090     {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1091     {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1092     {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1093     {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1094     {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1095     {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1096     {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1097     {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1098     {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1099     {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1100     {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1101 };
1102 
1103 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1104     {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1105     {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1106     {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1107     {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1108     {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1109     {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1110     {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1111     {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1112     {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1113     {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1114     {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1115     {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1116     {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1117     {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1118 
1119 
1120 };
1121 
1122 static union audio_cea_channels speakers_to_channels(
1123     struct audio_speaker_flags speaker_flags)
1124 {
1125     union audio_cea_channels cea_channels = {0};
1126 
1127     /* these are one to one */
1128     cea_channels.channels.FL = speaker_flags.FL_FR;
1129     cea_channels.channels.FR = speaker_flags.FL_FR;
1130     cea_channels.channels.LFE = speaker_flags.LFE;
1131     cea_channels.channels.FC = speaker_flags.FC;
1132 
1133     /* if Rear Left and Right exist move RC speaker to channel 7
1134      * otherwise to channel 5
1135      */
1136     if (speaker_flags.RL_RR) {
1137         cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1138         cea_channels.channels.RR = speaker_flags.RL_RR;
1139         cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1140     } else {
1141         cea_channels.channels.RL_RC = speaker_flags.RC;
1142     }
1143 
1144     /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1145     if (speaker_flags.FLC_FRC) {
1146         cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1147         cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1148     } else {
1149         cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1150         cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1151     }
1152 
1153     return cea_channels;
1154 }
1155 
1156 void get_audio_clock_info(
1157     enum dc_color_depth color_depth,
1158     uint32_t crtc_pixel_clock_100Hz,
1159     uint32_t actual_pixel_clock_100Hz,
1160     struct audio_clock_info *audio_clock_info)
1161 {
1162     const struct audio_clock_info *clock_info;
1163     uint32_t index;
1164     uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1165     uint32_t audio_array_size;
1166 
1167     switch (color_depth) {
1168     case COLOR_DEPTH_161616:
1169         clock_info = audio_clock_info_table_48bpc;
1170         audio_array_size = ARRAY_SIZE(
1171                 audio_clock_info_table_48bpc);
1172         break;
1173     case COLOR_DEPTH_121212:
1174         clock_info = audio_clock_info_table_36bpc;
1175         audio_array_size = ARRAY_SIZE(
1176                 audio_clock_info_table_36bpc);
1177         break;
1178     default:
1179         clock_info = audio_clock_info_table;
1180         audio_array_size = ARRAY_SIZE(
1181                 audio_clock_info_table);
1182         break;
1183     }
1184 
1185     if (clock_info != NULL) {
1186         /* search for exact pixel clock in table */
1187         for (index = 0; index < audio_array_size; index++) {
1188             if (clock_info[index].pixel_clock_in_10khz >
1189                 crtc_pixel_clock_in_10khz)
1190                 break;  /* not match */
1191             else if (clock_info[index].pixel_clock_in_10khz ==
1192                     crtc_pixel_clock_in_10khz) {
1193                 /* match found */
1194                 *audio_clock_info = clock_info[index];
1195                 return;
1196             }
1197         }
1198     }
1199 
1200     /* not found */
1201     if (actual_pixel_clock_100Hz == 0)
1202         actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1203 
1204     /* See HDMI spec  the table entry under
1205      *  pixel clock of "Other". */
1206     audio_clock_info->pixel_clock_in_10khz =
1207             actual_pixel_clock_100Hz / 100;
1208     audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1209     audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1210     audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1211 
1212     audio_clock_info->n_32khz = 4096;
1213     audio_clock_info->n_44khz = 6272;
1214     audio_clock_info->n_48khz = 6144;
1215 }
1216 
1217 static void enc1_se_audio_setup(
1218     struct stream_encoder *enc,
1219     unsigned int az_inst,
1220     struct audio_info *audio_info)
1221 {
1222     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1223 
1224     uint32_t channels = 0;
1225 
1226     ASSERT(audio_info);
1227     if (audio_info == NULL)
1228         /* This should not happen.it does so we don't get BSOD*/
1229         return;
1230 
1231     channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1232 
1233     /* setup the audio stream source select (audio -> dig mapping) */
1234     REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1235 
1236     /* Channel allocation */
1237     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1238 }
1239 
1240 static void enc1_se_setup_hdmi_audio(
1241     struct stream_encoder *enc,
1242     const struct audio_crtc_info *crtc_info)
1243 {
1244     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1245 
1246     struct audio_clock_info audio_clock_info = {0};
1247 
1248     /* HDMI_AUDIO_PACKET_CONTROL */
1249     REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1250             HDMI_AUDIO_DELAY_EN, 1);
1251 
1252     /* AFMT_AUDIO_PACKET_CONTROL */
1253     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1254 
1255     /* AFMT_AUDIO_PACKET_CONTROL2 */
1256     REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1257             AFMT_AUDIO_LAYOUT_OVRD, 0,
1258             AFMT_60958_OSF_OVRD, 0);
1259 
1260     /* HDMI_ACR_PACKET_CONTROL */
1261     REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1262             HDMI_ACR_AUTO_SEND, 1,
1263             HDMI_ACR_SOURCE, 0,
1264             HDMI_ACR_AUDIO_PRIORITY, 0);
1265 
1266     /* Program audio clock sample/regeneration parameters */
1267     get_audio_clock_info(crtc_info->color_depth,
1268                  crtc_info->requested_pixel_clock_100Hz,
1269                  crtc_info->calculated_pixel_clock_100Hz,
1270                  &audio_clock_info);
1271     DC_LOG_HW_AUDIO(
1272             "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
1273             "calculated_pixel_clock_100Hz = %d \n", __func__,   \
1274             crtc_info->requested_pixel_clock_100Hz,     \
1275             crtc_info->calculated_pixel_clock_100Hz);
1276 
1277     /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1278     REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1279 
1280     /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1281     REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1282 
1283     /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1284     REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1285 
1286     /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1287     REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1288 
1289     /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1290     REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1291 
1292     /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1293     REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1294 
1295     /* Video driver cannot know in advance which sample rate will
1296      * be used by HD Audio driver
1297      * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1298      * programmed below in interruppt callback
1299      */
1300 
1301     /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1302      * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1303      */
1304     REG_UPDATE_2(AFMT_60958_0,
1305             AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1306             AFMT_60958_CS_CLOCK_ACCURACY, 0);
1307 
1308     /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1309     REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1310 
1311     /* AFMT_60958_2 now keep this settings until
1312      * Programming guide comes out
1313      */
1314     REG_UPDATE_6(AFMT_60958_2,
1315             AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1316             AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1317             AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1318             AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1319             AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1320             AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1321 }
1322 
1323 static void enc1_se_setup_dp_audio(
1324     struct stream_encoder *enc)
1325 {
1326     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1327 
1328     /* --- DP Audio packet configurations --- */
1329 
1330     /* ATP Configuration */
1331     REG_SET(DP_SEC_AUD_N, 0,
1332             DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1333 
1334     /* Async/auto-calc timestamp mode */
1335     REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1336             DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1337 
1338     /* --- The following are the registers
1339      *  copied from the SetupHDMI ---
1340      */
1341 
1342     /* AFMT_AUDIO_PACKET_CONTROL */
1343     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1344 
1345     /* AFMT_AUDIO_PACKET_CONTROL2 */
1346     /* Program the ATP and AIP next */
1347     REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1348             AFMT_AUDIO_LAYOUT_OVRD, 0,
1349             AFMT_60958_OSF_OVRD, 0);
1350 
1351     /* AFMT_INFOFRAME_CONTROL0 */
1352     REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1353 
1354     /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1355     REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1356 }
1357 
1358 void enc1_se_enable_audio_clock(
1359     struct stream_encoder *enc,
1360     bool enable)
1361 {
1362     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1363 
1364     if (REG(AFMT_CNTL) == 0)
1365         return;   /* DCE8/10 does not have this register */
1366 
1367     REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1368 
1369     /* wait for AFMT clock to turn on,
1370      * expectation: this should complete in 1-2 reads
1371      *
1372      * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1373      *
1374      * TODO: wait for clock_on does not work well. May need HW
1375      * program sequence. But audio seems work normally even without wait
1376      * for clock_on status change
1377      */
1378 }
1379 
1380 void enc1_se_enable_dp_audio(
1381     struct stream_encoder *enc)
1382 {
1383     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1384 
1385     /* Enable Audio packets */
1386     REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1387 
1388     /* Program the ATP and AIP next */
1389     REG_UPDATE_2(DP_SEC_CNTL,
1390             DP_SEC_ATP_ENABLE, 1,
1391             DP_SEC_AIP_ENABLE, 1);
1392 
1393     /* Program STREAM_ENABLE after all the other enables. */
1394     REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1395 }
1396 
1397 static void enc1_se_disable_dp_audio(
1398     struct stream_encoder *enc)
1399 {
1400     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1401     uint32_t value = 0;
1402 
1403     /* Disable Audio packets */
1404     REG_UPDATE_5(DP_SEC_CNTL,
1405             DP_SEC_ASP_ENABLE, 0,
1406             DP_SEC_ATP_ENABLE, 0,
1407             DP_SEC_AIP_ENABLE, 0,
1408             DP_SEC_ACM_ENABLE, 0,
1409             DP_SEC_STREAM_ENABLE, 0);
1410 
1411     /* This register shared with encoder info frame. Therefore we need to
1412      * keep master enabled if at least on of the fields is not 0
1413      */
1414     value = REG_READ(DP_SEC_CNTL);
1415     if (value != 0)
1416         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1417 
1418 }
1419 
1420 void enc1_se_audio_mute_control(
1421     struct stream_encoder *enc,
1422     bool mute)
1423 {
1424     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1425 
1426     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1427 }
1428 
1429 void enc1_se_dp_audio_setup(
1430     struct stream_encoder *enc,
1431     unsigned int az_inst,
1432     struct audio_info *info)
1433 {
1434     enc1_se_audio_setup(enc, az_inst, info);
1435 }
1436 
1437 void enc1_se_dp_audio_enable(
1438     struct stream_encoder *enc)
1439 {
1440     enc1_se_enable_audio_clock(enc, true);
1441     enc1_se_setup_dp_audio(enc);
1442     enc1_se_enable_dp_audio(enc);
1443 }
1444 
1445 void enc1_se_dp_audio_disable(
1446     struct stream_encoder *enc)
1447 {
1448     enc1_se_disable_dp_audio(enc);
1449     enc1_se_enable_audio_clock(enc, false);
1450 }
1451 
1452 void enc1_se_hdmi_audio_setup(
1453     struct stream_encoder *enc,
1454     unsigned int az_inst,
1455     struct audio_info *info,
1456     struct audio_crtc_info *audio_crtc_info)
1457 {
1458     enc1_se_enable_audio_clock(enc, true);
1459     enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1460     enc1_se_audio_setup(enc, az_inst, info);
1461 }
1462 
1463 void enc1_se_hdmi_audio_disable(
1464     struct stream_encoder *enc)
1465 {
1466 #if defined(CONFIG_DRM_AMD_DC_DCN)
1467     if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1468         enc->afmt->funcs->afmt_powerdown(enc->afmt);
1469 #endif
1470     enc1_se_enable_audio_clock(enc, false);
1471 }
1472 
1473 
1474 void enc1_setup_stereo_sync(
1475     struct stream_encoder *enc,
1476     int tg_inst, bool enable)
1477 {
1478     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1479     REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1480     REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1481 }
1482 
1483 void enc1_dig_connect_to_otg(
1484     struct stream_encoder *enc,
1485     int tg_inst)
1486 {
1487     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1488 
1489     REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1490 }
1491 
1492 unsigned int enc1_dig_source_otg(
1493     struct stream_encoder *enc)
1494 {
1495     uint32_t tg_inst = 0;
1496     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1497 
1498     REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1499 
1500     return tg_inst;
1501 }
1502 
1503 bool enc1_stream_encoder_dp_get_pixel_format(
1504     struct stream_encoder *enc,
1505     enum dc_pixel_encoding *encoding,
1506     enum dc_color_depth *depth)
1507 {
1508     uint32_t hw_encoding = 0;
1509     uint32_t hw_depth = 0;
1510     struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1511 
1512     if (enc == NULL ||
1513         encoding == NULL ||
1514         depth == NULL)
1515         return false;
1516 
1517     REG_GET_2(DP_PIXEL_FORMAT,
1518         DP_PIXEL_ENCODING, &hw_encoding,
1519         DP_COMPONENT_DEPTH, &hw_depth);
1520 
1521     switch (hw_depth) {
1522     case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1523         *depth = COLOR_DEPTH_666;
1524         break;
1525     case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1526         *depth = COLOR_DEPTH_888;
1527         break;
1528     case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1529         *depth = COLOR_DEPTH_101010;
1530         break;
1531     case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1532         *depth = COLOR_DEPTH_121212;
1533         break;
1534     case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1535         *depth = COLOR_DEPTH_161616;
1536         break;
1537     default:
1538         *depth = COLOR_DEPTH_UNDEFINED;
1539         break;
1540     }
1541 
1542     switch (hw_encoding) {
1543     case DP_PIXEL_ENCODING_TYPE_RGB444:
1544         *encoding = PIXEL_ENCODING_RGB;
1545         break;
1546     case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1547         *encoding = PIXEL_ENCODING_YCBCR422;
1548         break;
1549     case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1550     case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1551         *encoding = PIXEL_ENCODING_YCBCR444;
1552         break;
1553     case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1554         *encoding = PIXEL_ENCODING_YCBCR420;
1555         break;
1556     default:
1557         *encoding = PIXEL_ENCODING_UNDEFINED;
1558         break;
1559     }
1560     return true;
1561 }
1562 
1563 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1564     .dp_set_stream_attribute =
1565         enc1_stream_encoder_dp_set_stream_attribute,
1566     .hdmi_set_stream_attribute =
1567         enc1_stream_encoder_hdmi_set_stream_attribute,
1568     .dvi_set_stream_attribute =
1569         enc1_stream_encoder_dvi_set_stream_attribute,
1570     .set_throttled_vcp_size =
1571         enc1_stream_encoder_set_throttled_vcp_size,
1572     .update_hdmi_info_packets =
1573         enc1_stream_encoder_update_hdmi_info_packets,
1574     .stop_hdmi_info_packets =
1575         enc1_stream_encoder_stop_hdmi_info_packets,
1576     .update_dp_info_packets =
1577         enc1_stream_encoder_update_dp_info_packets,
1578     .send_immediate_sdp_message =
1579         enc1_stream_encoder_send_immediate_sdp_message,
1580     .stop_dp_info_packets =
1581         enc1_stream_encoder_stop_dp_info_packets,
1582     .dp_blank =
1583         enc1_stream_encoder_dp_blank,
1584     .dp_unblank =
1585         enc1_stream_encoder_dp_unblank,
1586     .audio_mute_control = enc1_se_audio_mute_control,
1587 
1588     .dp_audio_setup = enc1_se_dp_audio_setup,
1589     .dp_audio_enable = enc1_se_dp_audio_enable,
1590     .dp_audio_disable = enc1_se_dp_audio_disable,
1591 
1592     .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1593     .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1594     .setup_stereo_sync  = enc1_setup_stereo_sync,
1595     .set_avmute = enc1_stream_encoder_set_avmute,
1596     .dig_connect_to_otg  = enc1_dig_connect_to_otg,
1597     .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1598     .dig_source_otg = enc1_dig_source_otg,
1599 
1600     .dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
1601 };
1602 
1603 void dcn10_stream_encoder_construct(
1604     struct dcn10_stream_encoder *enc1,
1605     struct dc_context *ctx,
1606     struct dc_bios *bp,
1607     enum engine_id eng_id,
1608     const struct dcn10_stream_enc_registers *regs,
1609     const struct dcn10_stream_encoder_shift *se_shift,
1610     const struct dcn10_stream_encoder_mask *se_mask)
1611 {
1612     enc1->base.funcs = &dcn10_str_enc_funcs;
1613     enc1->base.ctx = ctx;
1614     enc1->base.id = eng_id;
1615     enc1->base.bp = bp;
1616     enc1->regs = regs;
1617     enc1->se_shift = se_shift;
1618     enc1->se_mask = se_mask;
1619     enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1620 }
1621
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