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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #ifndef __DC_TIMING_GENERATOR_DCN10_H__
0027 #define __DC_TIMING_GENERATOR_DCN10_H__
0028 
0029 #include "timing_generator.h"
0030 
0031 #define DCN10TG_FROM_TG(tg)\
0032     container_of(tg, struct optc, base)
0033 
0034 #define TG_COMMON_REG_LIST_DCN(inst) \
0035     SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
0036     SRI(OTG_VUPDATE_PARAM, OTG, inst),\
0037     SRI(OTG_VREADY_PARAM, OTG, inst),\
0038     SRI(OTG_BLANK_CONTROL, OTG, inst),\
0039     SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
0040     SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
0041     SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
0042     SRI(OTG_H_TOTAL, OTG, inst),\
0043     SRI(OTG_H_BLANK_START_END, OTG, inst),\
0044     SRI(OTG_H_SYNC_A, OTG, inst),\
0045     SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
0046     SRI(OTG_H_TIMING_CNTL, OTG, inst),\
0047     SRI(OTG_V_TOTAL, OTG, inst),\
0048     SRI(OTG_V_BLANK_START_END, OTG, inst),\
0049     SRI(OTG_V_SYNC_A, OTG, inst),\
0050     SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
0051     SRI(OTG_INTERLACE_CONTROL, OTG, inst),\
0052     SRI(OTG_CONTROL, OTG, inst),\
0053     SRI(OTG_STEREO_CONTROL, OTG, inst),\
0054     SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
0055     SRI(OTG_STEREO_STATUS, OTG, inst),\
0056     SRI(OTG_V_TOTAL_MAX, OTG, inst),\
0057     SRI(OTG_V_TOTAL_MID, OTG, inst),\
0058     SRI(OTG_V_TOTAL_MIN, OTG, inst),\
0059     SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
0060     SRI(OTG_TRIGA_CNTL, OTG, inst),\
0061     SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
0062     SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
0063     SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
0064     SRI(OTG_STATUS, OTG, inst),\
0065     SRI(OTG_STATUS_POSITION, OTG, inst),\
0066     SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
0067     SRI(OTG_BLACK_COLOR, OTG, inst),\
0068     SRI(OTG_CLOCK_CONTROL, OTG, inst),\
0069     SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
0070     SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
0071     SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
0072     SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
0073     SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
0074     SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
0075     SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
0076     SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
0077     SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
0078     SRI(CONTROL, VTG, inst),\
0079     SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
0080     SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\
0081     SRI(OTG_GSL_CONTROL, OTG, inst),\
0082     SRI(OTG_CRC_CNTL, OTG, inst),\
0083     SRI(OTG_CRC0_DATA_RG, OTG, inst),\
0084     SRI(OTG_CRC0_DATA_B, OTG, inst),\
0085     SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
0086     SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
0087     SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
0088     SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
0089     SR(GSL_SOURCE_SELECT),\
0090     SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
0091     SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
0092 
0093 #define TG_COMMON_REG_LIST_DCN1_0(inst) \
0094     TG_COMMON_REG_LIST_DCN(inst),\
0095     SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
0096     SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\
0097     SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\
0098     SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
0099 
0100 
0101 struct dcn_optc_registers {
0102     uint32_t OTG_GLOBAL_CONTROL1;
0103     uint32_t OTG_GLOBAL_CONTROL2;
0104     uint32_t OTG_VERT_SYNC_CONTROL;
0105     uint32_t OTG_MASTER_UPDATE_MODE;
0106     uint32_t OTG_GSL_CONTROL;
0107     uint32_t OTG_VSTARTUP_PARAM;
0108     uint32_t OTG_VUPDATE_PARAM;
0109     uint32_t OTG_VREADY_PARAM;
0110     uint32_t OTG_BLANK_CONTROL;
0111     uint32_t OTG_MASTER_UPDATE_LOCK;
0112     uint32_t OTG_GLOBAL_CONTROL0;
0113     uint32_t OTG_DOUBLE_BUFFER_CONTROL;
0114     uint32_t OTG_H_TOTAL;
0115     uint32_t OTG_H_BLANK_START_END;
0116     uint32_t OTG_H_SYNC_A;
0117     uint32_t OTG_H_SYNC_A_CNTL;
0118     uint32_t OTG_H_TIMING_CNTL;
0119     uint32_t OTG_V_TOTAL;
0120     uint32_t OTG_V_BLANK_START_END;
0121     uint32_t OTG_V_SYNC_A;
0122     uint32_t OTG_V_SYNC_A_CNTL;
0123     uint32_t OTG_INTERLACE_CONTROL;
0124     uint32_t OTG_CONTROL;
0125     uint32_t OTG_STEREO_CONTROL;
0126     uint32_t OTG_3D_STRUCTURE_CONTROL;
0127     uint32_t OTG_STEREO_STATUS;
0128     uint32_t OTG_V_TOTAL_MAX;
0129     uint32_t OTG_V_TOTAL_MID;
0130     uint32_t OTG_V_TOTAL_MIN;
0131     uint32_t OTG_V_TOTAL_CONTROL;
0132     uint32_t OTG_TRIGA_CNTL;
0133     uint32_t OTG_TRIGA_MANUAL_TRIG;
0134     uint32_t OTG_MANUAL_FLOW_CONTROL;
0135     uint32_t OTG_FORCE_COUNT_NOW_CNTL;
0136     uint32_t OTG_STATIC_SCREEN_CONTROL;
0137     uint32_t OTG_STATUS_FRAME_COUNT;
0138     uint32_t OTG_STATUS;
0139     uint32_t OTG_STATUS_POSITION;
0140     uint32_t OTG_NOM_VERT_POSITION;
0141     uint32_t OTG_BLACK_COLOR;
0142     uint32_t OTG_TEST_PATTERN_PARAMETERS;
0143     uint32_t OTG_TEST_PATTERN_CONTROL;
0144     uint32_t OTG_TEST_PATTERN_COLOR;
0145     uint32_t OTG_CLOCK_CONTROL;
0146     uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
0147     uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
0148     uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL;
0149     uint32_t OTG_VERTICAL_INTERRUPT1_POSITION;
0150     uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
0151     uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
0152     uint32_t OPTC_INPUT_CLOCK_CONTROL;
0153     uint32_t OPTC_DATA_SOURCE_SELECT;
0154     uint32_t OPTC_MEMORY_CONFIG;
0155     uint32_t OPTC_INPUT_GLOBAL_CONTROL;
0156     uint32_t CONTROL;
0157     uint32_t OTG_GSL_WINDOW_X;
0158     uint32_t OTG_GSL_WINDOW_Y;
0159     uint32_t OTG_VUPDATE_KEEPOUT;
0160     uint32_t OTG_CRC_CNTL;
0161     uint32_t OTG_CRC_CNTL2;
0162     uint32_t OTG_CRC0_DATA_RG;
0163     uint32_t OTG_CRC0_DATA_B;
0164     uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
0165     uint32_t OTG_CRC0_WINDOWA_Y_CONTROL;
0166     uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
0167     uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
0168     uint32_t GSL_SOURCE_SELECT;
0169     uint32_t DWB_SOURCE_SELECT;
0170     uint32_t OTG_DSC_START_POSITION;
0171     uint32_t OPTC_DATA_FORMAT_CONTROL;
0172     uint32_t OPTC_BYTES_PER_PIXEL;
0173     uint32_t OPTC_WIDTH_CONTROL;
0174     uint32_t OTG_DRR_CONTROL;
0175     uint32_t OTG_BLANK_DATA_COLOR;
0176     uint32_t OTG_BLANK_DATA_COLOR_EXT;
0177     uint32_t OTG_DRR_TRIGGER_WINDOW;
0178     uint32_t OTG_M_CONST_DTO0;
0179     uint32_t OTG_M_CONST_DTO1;
0180     uint32_t OTG_DRR_V_TOTAL_CHANGE;
0181     uint32_t OTG_GLOBAL_CONTROL4;
0182 };
0183 
0184 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
0185     SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
0186     SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
0187     SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
0188     SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
0189     SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
0190     SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
0191     SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
0192     SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
0193     SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
0194     SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
0195     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
0196     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\
0197     SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
0198     SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
0199     SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
0200     SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
0201     SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
0202     SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
0203     SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
0204     SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
0205     SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
0206     SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
0207     SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\
0208     SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
0209     SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
0210     SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
0211     SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
0212     SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
0213     SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
0214     SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\
0215     SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
0216     SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
0217     SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
0218     SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
0219     SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\
0220     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
0221     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
0222     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
0223     SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
0224     SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
0225     SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
0226     SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
0227     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
0228     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
0229     SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
0230     SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
0231     SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
0232     SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
0233     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
0234     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
0235     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
0236     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
0237     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
0238     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
0239     SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
0240     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
0241     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
0242     SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
0243     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
0244     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
0245     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
0246     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
0247     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
0248     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
0249     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
0250     SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
0251     SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
0252     SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
0253     SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
0254     SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
0255     SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
0256     SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
0257     SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
0258     SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
0259     SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
0260     SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\
0261     SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\
0262     SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\
0263     SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
0264     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
0265     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
0266     SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
0267     SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
0268     SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
0269     SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
0270     SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
0271     SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
0272     SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
0273     SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
0274     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
0275     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
0276     SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
0277     SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
0278     SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
0279     SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
0280     SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
0281     SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
0282     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
0283     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
0284     SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
0285     SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\
0286     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
0287     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
0288     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
0289     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
0290     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
0291     SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
0292     SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
0293     SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
0294     SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
0295     SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
0296     SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
0297     SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
0298     SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
0299     SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
0300     SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
0301     SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
0302     SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
0303     SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
0304     SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
0305     SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
0306     SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
0307     SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
0308     SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
0309     SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
0310 
0311 
0312 
0313 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
0314     TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
0315     SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\
0316     SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\
0317     SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\
0318     SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\
0319     SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\
0320     SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\
0321     SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\
0322     SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\
0323     SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\
0324     SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\
0325     SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\
0326     SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\
0327     SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\
0328 
0329 #define TG_REG_FIELD_LIST_DCN1_0(type) \
0330     type VSTARTUP_START;\
0331     type VUPDATE_OFFSET;\
0332     type VUPDATE_WIDTH;\
0333     type VREADY_OFFSET;\
0334     type OTG_BLANK_DATA_EN;\
0335     type OTG_BLANK_DE_MODE;\
0336     type OTG_CURRENT_BLANK_STATE;\
0337     type OTG_MASTER_UPDATE_LOCK;\
0338     type UPDATE_LOCK_STATUS;\
0339     type OTG_UPDATE_PENDING;\
0340     type OTG_MASTER_UPDATE_LOCK_SEL;\
0341     type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
0342     type OTG_H_TOTAL;\
0343     type OTG_H_BLANK_START;\
0344     type OTG_H_BLANK_END;\
0345     type OTG_H_SYNC_A_START;\
0346     type OTG_H_SYNC_A_END;\
0347     type OTG_H_SYNC_A_POL;\
0348     type OTG_H_TIMING_DIV_BY2;\
0349     type OTG_V_TOTAL;\
0350     type OTG_V_BLANK_START;\
0351     type OTG_V_BLANK_END;\
0352     type OTG_V_SYNC_A_START;\
0353     type OTG_V_SYNC_A_END;\
0354     type OTG_V_SYNC_A_POL;\
0355     type OTG_INTERLACE_ENABLE;\
0356     type OTG_MASTER_EN;\
0357     type OTG_START_POINT_CNTL;\
0358     type OTG_DISABLE_POINT_CNTL;\
0359     type OTG_FIELD_NUMBER_CNTL;\
0360     type OTG_CURRENT_MASTER_EN_STATE;\
0361     type OTG_STEREO_EN;\
0362     type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\
0363     type OTG_STEREO_SYNC_OUTPUT_POLARITY;\
0364     type OTG_STEREO_EYE_FLAG_POLARITY;\
0365     type OTG_STEREO_CURRENT_EYE;\
0366     type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\
0367     type OTG_3D_STRUCTURE_EN;\
0368     type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
0369     type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
0370     type OTG_V_TOTAL_MAX;\
0371     type OTG_V_TOTAL_MID;\
0372     type OTG_V_TOTAL_MIN;\
0373     type OTG_V_TOTAL_MIN_SEL;\
0374     type OTG_V_TOTAL_MAX_SEL;\
0375     type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
0376     type OTG_VTOTAL_MID_FRAME_NUM;\
0377     type OTG_FORCE_LOCK_ON_EVENT;\
0378     type OTG_SET_V_TOTAL_MIN_MASK_EN;\
0379     type OTG_SET_V_TOTAL_MIN_MASK;\
0380     type OTG_FORCE_COUNT_NOW_CLEAR;\
0381     type OTG_FORCE_COUNT_NOW_MODE;\
0382     type OTG_FORCE_COUNT_NOW_OCCURRED;\
0383     type OTG_TRIGA_SOURCE_SELECT;\
0384     type OTG_TRIGA_SOURCE_PIPE_SELECT;\
0385     type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\
0386     type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\
0387     type OTG_TRIGA_POLARITY_SELECT;\
0388     type OTG_TRIGA_FREQUENCY_SELECT;\
0389     type OTG_TRIGA_DELAY;\
0390     type OTG_TRIGA_CLEAR;\
0391     type OTG_TRIGA_MANUAL_TRIG;\
0392     type OTG_STATIC_SCREEN_EVENT_MASK;\
0393     type OTG_STATIC_SCREEN_FRAME_COUNT;\
0394     type OTG_FRAME_COUNT;\
0395     type OTG_V_BLANK;\
0396     type OTG_V_ACTIVE_DISP;\
0397     type OTG_HORZ_COUNT;\
0398     type OTG_VERT_COUNT;\
0399     type OTG_VERT_COUNT_NOM;\
0400     type OTG_BLACK_COLOR_B_CB;\
0401     type OTG_BLACK_COLOR_G_Y;\
0402     type OTG_BLACK_COLOR_R_CR;\
0403     type OTG_BLANK_DATA_COLOR_BLUE_CB;\
0404     type OTG_BLANK_DATA_COLOR_GREEN_Y;\
0405     type OTG_BLANK_DATA_COLOR_RED_CR;\
0406     type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\
0407     type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\
0408     type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\
0409     type OTG_VTOTAL_MID_REPLACING_MIN_EN;\
0410     type OTG_TEST_PATTERN_INC0;\
0411     type OTG_TEST_PATTERN_INC1;\
0412     type OTG_TEST_PATTERN_VRES;\
0413     type OTG_TEST_PATTERN_HRES;\
0414     type OTG_TEST_PATTERN_RAMP0_OFFSET;\
0415     type OTG_TEST_PATTERN_EN;\
0416     type OTG_TEST_PATTERN_MODE;\
0417     type OTG_TEST_PATTERN_DYNAMIC_RANGE;\
0418     type OTG_TEST_PATTERN_COLOR_FORMAT;\
0419     type OTG_TEST_PATTERN_MASK;\
0420     type OTG_TEST_PATTERN_DATA;\
0421     type OTG_BUSY;\
0422     type OTG_CLOCK_EN;\
0423     type OTG_CLOCK_ON;\
0424     type OTG_CLOCK_GATE_DIS;\
0425     type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
0426     type OTG_VERTICAL_INTERRUPT0_LINE_START;\
0427     type OTG_VERTICAL_INTERRUPT0_LINE_END;\
0428     type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\
0429     type OTG_VERTICAL_INTERRUPT1_LINE_START;\
0430     type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
0431     type OTG_VERTICAL_INTERRUPT2_LINE_START;\
0432     type OPTC_INPUT_CLK_EN;\
0433     type OPTC_INPUT_CLK_ON;\
0434     type OPTC_INPUT_CLK_GATE_DIS;\
0435     type OPTC_UNDERFLOW_OCCURRED_STATUS;\
0436     type OPTC_UNDERFLOW_CLEAR;\
0437     type OPTC_SRC_SEL;\
0438     type VTG0_ENABLE;\
0439     type VTG0_FP2;\
0440     type VTG0_VCOUNT_INIT;\
0441     type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\
0442     type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\
0443     type OTG_AUTO_FORCE_VSYNC_MODE;\
0444     type MASTER_UPDATE_INTERLACED_MODE;\
0445     type OTG_GSL0_EN;\
0446     type OTG_GSL1_EN;\
0447     type OTG_GSL2_EN;\
0448     type OTG_GSL_MASTER_EN;\
0449     type OTG_GSL_FORCE_DELAY;\
0450     type OTG_GSL_CHECK_ALL_FIELDS;\
0451     type OTG_GSL_WINDOW_START_X;\
0452     type OTG_GSL_WINDOW_END_X;\
0453     type OTG_GSL_WINDOW_START_Y;\
0454     type OTG_GSL_WINDOW_END_Y;\
0455     type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\
0456     type OTG_GSL_MASTER_MODE;\
0457     type OTG_MASTER_UPDATE_LOCK_GSL_EN;\
0458     type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\
0459     type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\
0460     type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\
0461     type OTG_CRC_CONT_EN;\
0462     type OTG_CRC0_SELECT;\
0463     type OTG_CRC_EN;\
0464     type CRC0_R_CR;\
0465     type CRC0_G_Y;\
0466     type CRC0_B_CB;\
0467     type OTG_CRC0_WINDOWA_X_START;\
0468     type OTG_CRC0_WINDOWA_X_END;\
0469     type OTG_CRC0_WINDOWA_Y_START;\
0470     type OTG_CRC0_WINDOWA_Y_END;\
0471     type OTG_CRC0_WINDOWB_X_START;\
0472     type OTG_CRC0_WINDOWB_X_END;\
0473     type OTG_CRC0_WINDOWB_Y_START;\
0474     type OTG_CRC0_WINDOWB_Y_END;\
0475     type GSL0_READY_SOURCE_SEL;\
0476     type GSL1_READY_SOURCE_SEL;\
0477     type GSL2_READY_SOURCE_SEL;\
0478     type MANUAL_FLOW_CONTROL;\
0479     type MANUAL_FLOW_CONTROL_SEL;
0480 
0481 #define TG_REG_FIELD_LIST(type) \
0482     TG_REG_FIELD_LIST_DCN1_0(type)\
0483     type OTG_V_SYNC_MODE;\
0484     type OTG_DRR_TRIGGER_WINDOW_START_X;\
0485     type OTG_DRR_TRIGGER_WINDOW_END_X;\
0486     type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\
0487     type OTG_OUT_MUX;\
0488     type OTG_M_CONST_DTO_PHASE;\
0489     type OTG_M_CONST_DTO_MODULO;\
0490     type MASTER_UPDATE_LOCK_DB_X;\
0491     type MASTER_UPDATE_LOCK_DB_Y;\
0492     type MASTER_UPDATE_LOCK_DB_EN;\
0493     type GLOBAL_UPDATE_LOCK_EN;\
0494     type DIG_UPDATE_LOCATION;\
0495     type OTG_DSC_START_POSITION_X;\
0496     type OTG_DSC_START_POSITION_LINE_NUM;\
0497     type OPTC_NUM_OF_INPUT_SEGMENT;\
0498     type OPTC_SEG0_SRC_SEL;\
0499     type OPTC_SEG1_SRC_SEL;\
0500     type OPTC_SEG2_SRC_SEL;\
0501     type OPTC_SEG3_SRC_SEL;\
0502     type OPTC_MEM_SEL;\
0503     type OPTC_DATA_FORMAT;\
0504     type OPTC_DSC_MODE;\
0505     type OPTC_DSC_BYTES_PER_PIXEL;\
0506     type OPTC_DSC_SLICE_WIDTH;\
0507     type OPTC_SEGMENT_WIDTH;\
0508     type OPTC_DWB0_SOURCE_SELECT;\
0509     type OPTC_DWB1_SOURCE_SELECT;\
0510     type MASTER_UPDATE_LOCK_DB_START_X;\
0511     type MASTER_UPDATE_LOCK_DB_END_X;\
0512     type MASTER_UPDATE_LOCK_DB_START_Y;\
0513     type MASTER_UPDATE_LOCK_DB_END_Y;\
0514     type DIG_UPDATE_POSITION_X;\
0515     type DIG_UPDATE_POSITION_Y;\
0516     type OTG_H_TIMING_DIV_MODE;\
0517     type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\
0518     type OTG_CRC_DSC_MODE;\
0519     type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
0520     type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
0521     type OTG_CRC_DATA_FORMAT;\
0522     type OTG_V_TOTAL_LAST_USED_BY_DRR;
0523 
0524 #define TG_REG_FIELD_LIST_DCN3_2(type) \
0525     type OTG_H_TIMING_DIV_MODE_MANUAL;
0526 
0527 struct dcn_optc_shift {
0528     TG_REG_FIELD_LIST(uint8_t)
0529     TG_REG_FIELD_LIST_DCN3_2(uint8_t)
0530 };
0531 
0532 struct dcn_optc_mask {
0533     TG_REG_FIELD_LIST(uint32_t)
0534     TG_REG_FIELD_LIST_DCN3_2(uint32_t)
0535 };
0536 
0537 struct optc {
0538     struct timing_generator base;
0539 
0540     const struct dcn_optc_registers *tg_regs;
0541     const struct dcn_optc_shift *tg_shift;
0542     const struct dcn_optc_mask *tg_mask;
0543 
0544     int opp_count;
0545 
0546     uint32_t max_h_total;
0547     uint32_t max_v_total;
0548 
0549     uint32_t min_h_blank;
0550 
0551     uint32_t min_h_sync_width;
0552     uint32_t min_v_sync_width;
0553     uint32_t min_v_blank;
0554     uint32_t min_v_blank_interlace;
0555 
0556     int vstartup_start;
0557     int vupdate_offset;
0558     int vupdate_width;
0559     int vready_offset;
0560     struct dc_crtc_timing orginal_patched_timing;
0561     enum signal_type signal;
0562 };
0563 
0564 void dcn10_timing_generator_init(struct optc *optc);
0565 
0566 struct dcn_otg_state {
0567     uint32_t v_blank_start;
0568     uint32_t v_blank_end;
0569     uint32_t v_sync_a_pol;
0570     uint32_t v_total;
0571     uint32_t v_total_max;
0572     uint32_t v_total_min;
0573     uint32_t v_total_min_sel;
0574     uint32_t v_total_max_sel;
0575     uint32_t v_sync_a_start;
0576     uint32_t v_sync_a_end;
0577     uint32_t h_blank_start;
0578     uint32_t h_blank_end;
0579     uint32_t h_sync_a_start;
0580     uint32_t h_sync_a_end;
0581     uint32_t h_sync_a_pol;
0582     uint32_t h_total;
0583     uint32_t underflow_occurred_status;
0584     uint32_t otg_enabled;
0585     uint32_t blank_enabled;
0586     uint32_t vertical_interrupt2_en;
0587     uint32_t vertical_interrupt2_line;
0588 };
0589 
0590 void optc1_read_otg_state(struct optc *optc1,
0591         struct dcn_otg_state *s);
0592 
0593 bool optc1_get_hw_timing(struct timing_generator *tg,
0594         struct dc_crtc_timing *hw_crtc_timing);
0595 
0596 bool optc1_validate_timing(
0597     struct timing_generator *optc,
0598     const struct dc_crtc_timing *timing);
0599 
0600 void optc1_program_timing(
0601     struct timing_generator *optc,
0602     const struct dc_crtc_timing *dc_crtc_timing,
0603     int vready_offset,
0604     int vstartup_start,
0605     int vupdate_offset,
0606     int vupdate_width,
0607     const enum signal_type signal,
0608     bool use_vbios);
0609 
0610 void optc1_setup_vertical_interrupt0(
0611         struct timing_generator *optc,
0612         uint32_t start_line,
0613         uint32_t end_line);
0614 void optc1_setup_vertical_interrupt1(
0615         struct timing_generator *optc,
0616         uint32_t start_line);
0617 void optc1_setup_vertical_interrupt2(
0618         struct timing_generator *optc,
0619         uint32_t start_line);
0620 
0621 void optc1_program_global_sync(
0622         struct timing_generator *optc,
0623         int vready_offset,
0624         int vstartup_start,
0625         int vupdate_offset,
0626         int vupdate_width);
0627 
0628 bool optc1_disable_crtc(struct timing_generator *optc);
0629 
0630 bool optc1_is_counter_moving(struct timing_generator *optc);
0631 
0632 void optc1_get_position(struct timing_generator *optc,
0633         struct crtc_position *position);
0634 
0635 uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
0636 
0637 void optc1_get_crtc_scanoutpos(
0638     struct timing_generator *optc,
0639     uint32_t *v_blank_start,
0640     uint32_t *v_blank_end,
0641     uint32_t *h_position,
0642     uint32_t *v_position);
0643 
0644 void optc1_set_early_control(
0645     struct timing_generator *optc,
0646     uint32_t early_cntl);
0647 
0648 void optc1_wait_for_state(struct timing_generator *optc,
0649         enum crtc_state state);
0650 
0651 void optc1_set_blank(struct timing_generator *optc,
0652         bool enable_blanking);
0653 
0654 bool optc1_is_blanked(struct timing_generator *optc);
0655 bool optc1_is_locked(struct timing_generator *optc);
0656 
0657 void optc1_program_blank_color(
0658         struct timing_generator *optc,
0659         const struct tg_color *black_color);
0660 
0661 bool optc1_did_triggered_reset_occur(
0662     struct timing_generator *optc);
0663 
0664 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
0665 
0666 void optc1_disable_reset_trigger(struct timing_generator *optc);
0667 
0668 void optc1_lock(struct timing_generator *optc);
0669 
0670 void optc1_unlock(struct timing_generator *optc);
0671 
0672 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
0673 
0674 void optc1_set_drr(
0675     struct timing_generator *optc,
0676     const struct drr_params *params);
0677 
0678 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
0679 
0680 void optc1_set_static_screen_control(
0681     struct timing_generator *optc,
0682     uint32_t event_triggers,
0683     uint32_t num_frames);
0684 
0685 void optc1_program_stereo(struct timing_generator *optc,
0686     const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
0687 
0688 bool optc1_is_stereo_left_eye(struct timing_generator *optc);
0689 
0690 void optc1_clear_optc_underflow(struct timing_generator *optc);
0691 
0692 void optc1_tg_init(struct timing_generator *optc);
0693 
0694 bool optc1_is_tg_enabled(struct timing_generator *optc);
0695 
0696 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
0697 
0698 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
0699 
0700 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
0701 
0702 bool optc1_get_otg_active_size(struct timing_generator *optc,
0703         uint32_t *otg_active_width,
0704         uint32_t *otg_active_height);
0705 
0706 void optc1_enable_crtc_reset(
0707         struct timing_generator *optc,
0708         int source_tg_inst,
0709         struct crtc_trigger_info *crtc_tp);
0710 
0711 bool optc1_configure_crc(struct timing_generator *optc,
0712               const struct crc_params *params);
0713 
0714 bool optc1_get_crc(struct timing_generator *optc,
0715             uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
0716 
0717 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
0718 
0719 void optc1_set_vtg_params(struct timing_generator *optc,
0720         const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
0721 
0722 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
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