dc/dcn10/dcn10_opp.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_OPP_DCN10_H__
0026 #define __DC_OPP_DCN10_H__
0027
0028 #include "opp.h"
0029
0030 #define TO_DCN10_OPP(opp)\
0031     container_of(opp, struct dcn10_opp, base)
0032
0033 #define OPP_SF(reg_name, field_name, post_fix)\
0034     .field_name = reg_name ## __ ## field_name ## post_fix
0035
0036 #define OPP_REG_LIST_DCN(id) \
0037     SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
0038     SRI(FMT_CONTROL, FMT, id), \
0039     SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
0040     SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
0041     SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
0042     SRI(FMT_CLAMP_CNTL, FMT, id), \
0043     SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
0044     SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
0045     SRI(OPPBUF_CONTROL, OPPBUF, id),\
0046     SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
0047     SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \
0048     SRI(OPP_PIPE_CONTROL, OPP_PIPE, id)
0049
0050 #define OPP_REG_LIST_DCN10(id) \
0051     OPP_REG_LIST_DCN(id)
0052
0053 #define OPP_COMMON_REG_VARIABLE_LIST \
0054     uint32_t FMT_BIT_DEPTH_CONTROL; \
0055     uint32_t FMT_CONTROL; \
0056     uint32_t FMT_DITHER_RAND_R_SEED; \
0057     uint32_t FMT_DITHER_RAND_G_SEED; \
0058     uint32_t FMT_DITHER_RAND_B_SEED; \
0059     uint32_t FMT_CLAMP_CNTL; \
0060     uint32_t FMT_DYNAMIC_EXP_CNTL; \
0061     uint32_t FMT_MAP420_MEMORY_CONTROL; \
0062     uint32_t OPPBUF_CONTROL; \
0063     uint32_t OPPBUF_CONTROL1; \
0064     uint32_t OPPBUF_3D_PARAMETERS_0; \
0065     uint32_t OPPBUF_3D_PARAMETERS_1; \
0066     uint32_t OPP_PIPE_CONTROL
0067
0068 #define OPP_MASK_SH_LIST_DCN(mask_sh) \
0069     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
0070     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
0071     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \
0072     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \
0073     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \
0074     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \
0075     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \
0076     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \
0077     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \
0078     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
0079     OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \
0080     OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \
0081     OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
0082     OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
0083     OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
0084     OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
0085     OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
0086     OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
0087     OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
0088     OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
0089     OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \
0090     OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \
0091     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
0092     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\
0093     OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \
0094     OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \
0095     OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh)
0096
0097 #define OPP_MASK_SH_LIST_DCN10(mask_sh) \
0098     OPP_MASK_SH_LIST_DCN(mask_sh), \
0099     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\
0100     OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh)
0101
0102 #define OPP_DCN10_REG_FIELD_LIST(type) \
0103     type FMT_TRUNCATE_EN; \
0104     type FMT_TRUNCATE_DEPTH; \
0105     type FMT_TRUNCATE_MODE; \
0106     type FMT_SPATIAL_DITHER_EN; \
0107     type FMT_SPATIAL_DITHER_MODE; \
0108     type FMT_SPATIAL_DITHER_DEPTH; \
0109     type FMT_TEMPORAL_DITHER_EN; \
0110     type FMT_HIGHPASS_RANDOM_ENABLE; \
0111     type FMT_FRAME_RANDOM_ENABLE; \
0112     type FMT_RGB_RANDOM_ENABLE; \
0113     type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
0114     type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
0115     type FMT_RAND_R_SEED; \
0116     type FMT_RAND_G_SEED; \
0117     type FMT_RAND_B_SEED; \
0118     type FMT_PIXEL_ENCODING; \
0119     type FMT_SUBSAMPLING_MODE; \
0120     type FMT_CBCR_BIT_REDUCTION_BYPASS; \
0121     type FMT_CLAMP_DATA_EN; \
0122     type FMT_CLAMP_COLOR_FORMAT; \
0123     type FMT_DYNAMIC_EXP_EN; \
0124     type FMT_DYNAMIC_EXP_MODE; \
0125     type FMT_MAP420MEM_PWR_FORCE; \
0126     type FMT_STEREOSYNC_OVERRIDE; \
0127     type OPPBUF_ACTIVE_WIDTH;\
0128     type OPPBUF_PIXEL_REPETITION;\
0129     type OPPBUF_DISPLAY_SEGMENTATION;\
0130     type OPPBUF_OVERLAP_PIXEL_NUM;\
0131     type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \
0132     type OPPBUF_3D_VACT_SPACE1_SIZE; \
0133     type OPPBUF_3D_VACT_SPACE2_SIZE; \
0134     type OPP_PIPE_CLOCK_EN
0135
0136 struct dcn10_opp_registers {
0137     OPP_COMMON_REG_VARIABLE_LIST;
0138 };
0139
0140 struct dcn10_opp_shift {
0141     OPP_DCN10_REG_FIELD_LIST(uint8_t);
0142 };
0143
0144 struct dcn10_opp_mask {
0145     OPP_DCN10_REG_FIELD_LIST(uint32_t);
0146 };
0147
0148 struct dcn10_opp {
0149     struct output_pixel_processor base;
0150
0151     const struct dcn10_opp_registers *regs;
0152     const struct dcn10_opp_shift *opp_shift;
0153     const struct dcn10_opp_mask *opp_mask;
0154
0155     bool is_write_to_ram_a_safe;
0156 };
0157
0158 void dcn10_opp_construct(struct dcn10_opp *oppn10,
0159     struct dc_context *ctx,
0160     uint32_t inst,
0161     const struct dcn10_opp_registers *regs,
0162     const struct dcn10_opp_shift *opp_shift,
0163     const struct dcn10_opp_mask *opp_mask);
0164
0165 void opp1_set_dyn_expansion(
0166     struct output_pixel_processor *opp,
0167     enum dc_color_space color_sp,
0168     enum dc_color_depth color_dpth,
0169     enum signal_type signal);
0170
0171 void opp1_program_fmt(
0172     struct output_pixel_processor *opp,
0173     struct bit_depth_reduction_params *fmt_bit_depth,
0174     struct clamping_and_pixel_encoding_params *clamping);
0175
0176 void opp1_program_bit_depth_reduction(
0177     struct output_pixel_processor *opp,
0178     const struct bit_depth_reduction_params *params);
0179
0180 void opp1_program_stereo(
0181     struct output_pixel_processor *opp,
0182     bool enable,
0183     const struct dc_crtc_timing *timing);
0184
0185 void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);
0186
0187 void opp1_destroy(struct output_pixel_processor **opp);
0188
0189 #endif