dc/dcn10/dcn10_mpc.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_MPCC_DCN10_H__
0026 #define __DC_MPCC_DCN10_H__
0027
0028 #include "mpc.h"
0029
0030 #define TO_DCN10_MPC(mpc_base) \
0031     container_of(mpc_base, struct dcn10_mpc, base)
0032
0033 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \
0034     SRII(MPCC_TOP_SEL, MPCC, inst),\
0035     SRII(MPCC_BOT_SEL, MPCC, inst),\
0036     SRII(MPCC_CONTROL, MPCC, inst),\
0037     SRII(MPCC_STATUS, MPCC, inst),\
0038     SRII(MPCC_OPP_ID, MPCC, inst),\
0039     SRII(MPCC_BG_G_Y, MPCC, inst),\
0040     SRII(MPCC_BG_R_CR, MPCC, inst),\
0041     SRII(MPCC_BG_B_CB, MPCC, inst),\
0042     SRII(MPCC_SM_CONTROL, MPCC, inst),\
0043     SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
0044
0045 #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
0046     SRII(MUX, MPC_OUT, inst),\
0047     VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
0048
0049 #define MPC_COMMON_REG_VARIABLE_LIST \
0050     uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
0051     uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
0052     uint32_t MPCC_CONTROL[MAX_MPCC]; \
0053     uint32_t MPCC_STATUS[MAX_MPCC]; \
0054     uint32_t MPCC_OPP_ID[MAX_MPCC]; \
0055     uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
0056     uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
0057     uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
0058     uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
0059     uint32_t MUX[MAX_OPP]; \
0060     uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
0061     uint32_t CUR[MAX_OPP];
0062
0063 #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
0064     SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
0065     SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
0066     SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
0067     SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
0068     SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
0069     SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
0070     SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
0071     SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
0072     SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
0073     SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
0074     SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
0075     SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
0076     SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
0077     SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
0078     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
0079     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
0080     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
0081     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
0082     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
0083     SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
0084     SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
0085     SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
0086
0087 #define MPC_REG_FIELD_LIST(type) \
0088     type MPCC_TOP_SEL;\
0089     type MPCC_BOT_SEL;\
0090     type MPCC_MODE;\
0091     type MPCC_ALPHA_BLND_MODE;\
0092     type MPCC_ALPHA_MULTIPLIED_MODE;\
0093     type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
0094     type MPCC_GLOBAL_ALPHA;\
0095     type MPCC_GLOBAL_GAIN;\
0096     type MPCC_IDLE;\
0097     type MPCC_BUSY;\
0098     type MPCC_OPP_ID;\
0099     type MPCC_BG_G_Y;\
0100     type MPCC_BG_R_CR;\
0101     type MPCC_BG_B_CB;\
0102     type MPCC_SM_EN;\
0103     type MPCC_SM_MODE;\
0104     type MPCC_SM_FRAME_ALT;\
0105     type MPCC_SM_FIELD_ALT;\
0106     type MPCC_SM_FORCE_NEXT_FRAME_POL;\
0107     type MPCC_SM_FORCE_NEXT_TOP_POL;\
0108     type MPC_OUT_MUX;\
0109     type MPCC_UPDATE_LOCK_SEL;\
0110     type CUR_VUPDATE_LOCK_SET;
0111
0112 struct dcn_mpc_registers {
0113     MPC_COMMON_REG_VARIABLE_LIST
0114 };
0115
0116 struct dcn_mpc_shift {
0117     MPC_REG_FIELD_LIST(uint8_t)
0118 };
0119
0120 struct dcn_mpc_mask {
0121     MPC_REG_FIELD_LIST(uint32_t)
0122 };
0123
0124 struct dcn10_mpc {
0125     struct mpc base;
0126
0127     int mpcc_in_use_mask;
0128     int num_mpcc;
0129     const struct dcn_mpc_registers *mpc_regs;
0130     const struct dcn_mpc_shift *mpc_shift;
0131     const struct dcn_mpc_mask *mpc_mask;
0132 };
0133
0134 void dcn10_mpc_construct(struct dcn10_mpc *mpcc10,
0135     struct dc_context *ctx,
0136     const struct dcn_mpc_registers *mpc_regs,
0137     const struct dcn_mpc_shift *mpc_shift,
0138     const struct dcn_mpc_mask *mpc_mask,
0139     int num_mpcc);
0140
0141 struct mpcc *mpc1_insert_plane(
0142     struct mpc *mpc,
0143     struct mpc_tree *tree,
0144     struct mpcc_blnd_cfg *blnd_cfg,
0145     struct mpcc_sm_cfg *sm_cfg,
0146     struct mpcc *insert_above_mpcc,
0147     int dpp_id,
0148     int mpcc_id);
0149
0150 void mpc1_remove_mpcc(
0151     struct mpc *mpc,
0152     struct mpc_tree *tree,
0153     struct mpcc *mpcc);
0154
0155 void mpc1_mpc_init(
0156     struct mpc *mpc);
0157
0158 void mpc1_mpc_init_single_inst(
0159     struct mpc *mpc,
0160     unsigned int mpcc_id);
0161
0162 void mpc1_assert_idle_mpcc(
0163     struct mpc *mpc,
0164     int id);
0165
0166 void mpc1_set_bg_color(
0167     struct mpc *mpc,
0168     struct tg_color *bg_color,
0169     int id);
0170
0171 void mpc1_update_stereo_mix(
0172     struct mpc *mpc,
0173     struct mpcc_sm_cfg *sm_cfg,
0174     int mpcc_id);
0175
0176 bool mpc1_is_mpcc_idle(
0177     struct mpc *mpc,
0178     int mpcc_id);
0179
0180 void mpc1_assert_mpcc_idle_before_connect(
0181     struct mpc *mpc,
0182     int mpcc_id);
0183
0184 void mpc1_init_mpcc_list_from_hw(
0185     struct mpc *mpc,
0186     struct mpc_tree *tree);
0187
0188 struct mpcc *mpc1_get_mpcc(
0189     struct mpc *mpc,
0190     int mpcc_id);
0191
0192 struct mpcc *mpc1_get_mpcc_for_dpp(
0193     struct mpc_tree *tree,
0194     int dpp_id);
0195
0196 void mpc1_read_mpcc_state(
0197         struct mpc *mpc,
0198         int mpcc_inst,
0199         struct mpcc_state *s);
0200
0201 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
0202
0203 unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
0204 #endif