dc/dcn10/dcn10_link_encoder.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCN10_H__
0027 #define __DC_LINK_ENCODER__DCN10_H__
0028
0029 #include "link_encoder.h"
0030
0031 #define TO_DCN10_LINK_ENC(link_encoder)\
0032     container_of(link_encoder, struct dcn10_link_encoder, base)
0033
0034 #define AUX_REG_LIST(id)\
0035     SRI(AUX_CONTROL, DP_AUX, id), \
0036     SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
0037     SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
0038
0039 #define HPD_REG_LIST(id)\
0040     SRI(DC_HPD_CONTROL, HPD, id)
0041
0042 #define LE_DCN_COMMON_REG_LIST(id) \
0043     SRI(DIG_BE_CNTL, DIG, id), \
0044     SRI(DIG_BE_EN_CNTL, DIG, id), \
0045     SRI(DIG_CLOCK_PATTERN, DIG, id), \
0046     SRI(TMDS_CTL_BITS, DIG, id), \
0047     SRI(DP_CONFIG, DP, id), \
0048     SRI(DP_DPHY_CNTL, DP, id), \
0049     SRI(DP_DPHY_PRBS_CNTL, DP, id), \
0050     SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
0051     SRI(DP_DPHY_SYM0, DP, id), \
0052     SRI(DP_DPHY_SYM1, DP, id), \
0053     SRI(DP_DPHY_SYM2, DP, id), \
0054     SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
0055     SRI(DP_LINK_CNTL, DP, id), \
0056     SRI(DP_LINK_FRAMING_CNTL, DP, id), \
0057     SRI(DP_MSE_SAT0, DP, id), \
0058     SRI(DP_MSE_SAT1, DP, id), \
0059     SRI(DP_MSE_SAT2, DP, id), \
0060     SRI(DP_MSE_SAT_UPDATE, DP, id), \
0061     SRI(DP_SEC_CNTL, DP, id), \
0062     SRI(DP_VID_STREAM_CNTL, DP, id), \
0063     SRI(DP_DPHY_FAST_TRAINING, DP, id), \
0064     SRI(DP_SEC_CNTL1, DP, id), \
0065     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0066     SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
0067
0068
0069 #define LE_DCN10_REG_LIST(id)\
0070     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0071     LE_DCN_COMMON_REG_LIST(id)
0072
0073 struct dcn10_link_enc_aux_registers {
0074     uint32_t AUX_CONTROL;
0075     uint32_t AUX_DPHY_RX_CONTROL0;
0076     uint32_t AUX_DPHY_TX_CONTROL;
0077     uint32_t AUX_DPHY_RX_CONTROL1;
0078 };
0079
0080 struct dcn10_link_enc_hpd_registers {
0081     uint32_t DC_HPD_CONTROL;
0082 };
0083
0084 struct dcn10_link_enc_registers {
0085     uint32_t DIG_BE_CNTL;
0086     uint32_t DIG_BE_EN_CNTL;
0087     uint32_t DIG_CLOCK_PATTERN;
0088     uint32_t DP_CONFIG;
0089     uint32_t DP_DPHY_CNTL;
0090     uint32_t DP_DPHY_INTERNAL_CTRL;
0091     uint32_t DP_DPHY_PRBS_CNTL;
0092     uint32_t DP_DPHY_SCRAM_CNTL;
0093     uint32_t DP_DPHY_SYM0;
0094     uint32_t DP_DPHY_SYM1;
0095     uint32_t DP_DPHY_SYM2;
0096     uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
0097     uint32_t DP_LINK_CNTL;
0098     uint32_t DP_LINK_FRAMING_CNTL;
0099     uint32_t DP_MSE_SAT0;
0100     uint32_t DP_MSE_SAT1;
0101     uint32_t DP_MSE_SAT2;
0102     uint32_t DP_MSE_SAT_UPDATE;
0103     uint32_t DP_SEC_CNTL;
0104     uint32_t DP_VID_STREAM_CNTL;
0105     uint32_t DP_DPHY_FAST_TRAINING;
0106     uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
0107     uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
0108     uint32_t DP_SEC_CNTL1;
0109     uint32_t TMDS_CTL_BITS;
0110     /* DCCG  */
0111     uint32_t CLOCK_ENABLE;
0112     /* DIG */
0113     uint32_t DIG_LANE_ENABLE;
0114     /* UNIPHY */
0115     uint32_t CHANNEL_XBAR_CNTL;
0116     /* DPCS */
0117     uint32_t RDPCSTX_PHY_CNTL3;
0118     uint32_t RDPCSTX_PHY_CNTL4;
0119     uint32_t RDPCSTX_PHY_CNTL5;
0120     uint32_t RDPCSTX_PHY_CNTL6;
0121     uint32_t RDPCSPIPE_PHY_CNTL6;
0122     uint32_t RDPCSTX_PHY_CNTL7;
0123     uint32_t RDPCSTX_PHY_CNTL8;
0124     uint32_t RDPCSTX_PHY_CNTL9;
0125     uint32_t RDPCSTX_PHY_CNTL10;
0126     uint32_t RDPCSTX_PHY_CNTL11;
0127     uint32_t RDPCSTX_PHY_CNTL12;
0128     uint32_t RDPCSTX_PHY_CNTL13;
0129     uint32_t RDPCSTX_PHY_CNTL14;
0130     uint32_t RDPCSTX_PHY_CNTL15;
0131     uint32_t RDPCSTX_CNTL;
0132     uint32_t RDPCSTX_CLOCK_CNTL;
0133     uint32_t RDPCSTX_PHY_CNTL0;
0134     uint32_t RDPCSTX_PHY_CNTL2;
0135     uint32_t RDPCSTX_PLL_UPDATE_DATA;
0136     uint32_t RDPCS_TX_CR_ADDR;
0137     uint32_t RDPCS_TX_CR_DATA;
0138     uint32_t DPCSTX_TX_CLOCK_CNTL;
0139     uint32_t DPCSTX_TX_CNTL;
0140     uint32_t RDPCSTX_INTERRUPT_CONTROL;
0141     uint32_t RDPCSTX_PHY_FUSE0;
0142     uint32_t RDPCSTX_PHY_FUSE1;
0143     uint32_t RDPCSTX_PHY_FUSE2;
0144     uint32_t RDPCSTX_PHY_FUSE3;
0145     uint32_t RDPCSTX_PHY_RX_LD_VAL;
0146     uint32_t DPCSTX_DEBUG_CONFIG;
0147     uint32_t RDPCSTX_DEBUG_CONFIG;
0148     uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
0149     uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
0150     uint32_t DCIO_SOFT_RESET;
0151     /* indirect registers */
0152     uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
0153     uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
0154     uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
0155     uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
0156     uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
0157     uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
0158     uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
0159     uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
0160     uint32_t TMDS_DCBALANCER_CONTROL;
0161     uint32_t PHYA_LINK_CNTL2;
0162     uint32_t PHYB_LINK_CNTL2;
0163     uint32_t PHYC_LINK_CNTL2;
0164     uint32_t DIO_LINKA_CNTL;
0165     uint32_t DIO_LINKB_CNTL;
0166     uint32_t DIO_LINKC_CNTL;
0167     uint32_t DIO_LINKD_CNTL;
0168     uint32_t DIO_LINKE_CNTL;
0169     uint32_t DIO_LINKF_CNTL;
0170     uint32_t DIG_FIFO_CTRL0;
0171 };
0172
0173 #define LE_SF(reg_name, field_name, post_fix)\
0174     .field_name = reg_name ## __ ## field_name ## post_fix
0175
0176 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
0177     LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
0178     LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
0179     LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
0180     LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
0181     LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\
0182     LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
0183     LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
0184     LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
0185     LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
0186     LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
0187     LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
0188     LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
0189     LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
0190     LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
0191     LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
0192     LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
0193     LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
0194     LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
0195     LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
0196     LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
0197     LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
0198     LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
0199     LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
0200     LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
0201     LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
0202     LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
0203     LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
0204     LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
0205     LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
0206     LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
0207     LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
0208     LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
0209     LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
0210     LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
0211     LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
0212     LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
0213     LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
0214     LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
0215     LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
0216     LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
0217     LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
0218     LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
0219     LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
0220     LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
0221     LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
0222     LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
0223     LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
0224     LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
0225     LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
0226
0227 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
0228     type DIG_ENABLE;\
0229     type DIG_HPD_SELECT;\
0230     type DIG_MODE;\
0231     type DIG_FE_SOURCE_SELECT;\
0232     type DIG_CLOCK_PATTERN;\
0233     type DPHY_BYPASS;\
0234     type DPHY_ATEST_SEL_LANE0;\
0235     type DPHY_ATEST_SEL_LANE1;\
0236     type DPHY_ATEST_SEL_LANE2;\
0237     type DPHY_ATEST_SEL_LANE3;\
0238     type DPHY_PRBS_EN;\
0239     type DPHY_PRBS_SEL;\
0240     type DPHY_SYM1;\
0241     type DPHY_SYM2;\
0242     type DPHY_SYM3;\
0243     type DPHY_SYM4;\
0244     type DPHY_SYM5;\
0245     type DPHY_SYM6;\
0246     type DPHY_SYM7;\
0247     type DPHY_SYM8;\
0248     type DPHY_SCRAMBLER_BS_COUNT;\
0249     type DPHY_SCRAMBLER_ADVANCE;\
0250     type DPHY_RX_FAST_TRAINING_CAPABLE;\
0251     type DPHY_LOAD_BS_COUNT;\
0252     type DPHY_TRAINING_PATTERN_SEL;\
0253     type DP_DPHY_HBR2_PATTERN_CONTROL;\
0254     type DP_LINK_TRAINING_COMPLETE;\
0255     type DP_IDLE_BS_INTERVAL;\
0256     type DP_VBID_DISABLE;\
0257     type DP_VID_ENHANCED_FRAME_MODE;\
0258     type DP_VID_STREAM_ENABLE;\
0259     type DP_UDI_LANES;\
0260     type DP_SEC_GSP0_LINE_NUM;\
0261     type DP_SEC_GSP0_PRIORITY;\
0262     type DP_MSE_SAT_SRC0;\
0263     type DP_MSE_SAT_SRC1;\
0264     type DP_MSE_SAT_SRC2;\
0265     type DP_MSE_SAT_SRC3;\
0266     type DP_MSE_SAT_SLOT_COUNT0;\
0267     type DP_MSE_SAT_SLOT_COUNT1;\
0268     type DP_MSE_SAT_SLOT_COUNT2;\
0269     type DP_MSE_SAT_SLOT_COUNT3;\
0270     type DP_MSE_SAT_UPDATE;\
0271     type DP_MSE_16_MTP_KEEPOUT;\
0272     type DC_HPD_EN;\
0273     type TMDS_CTL0;\
0274     type AUX_HPD_SEL;\
0275     type AUX_LS_READ_EN;\
0276     type AUX_RX_RECEIVE_WINDOW
0277
0278
0279 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
0280         type RDPCS_PHY_DP_TX0_DATA_EN;\
0281         type RDPCS_PHY_DP_TX1_DATA_EN;\
0282         type RDPCS_PHY_DP_TX2_DATA_EN;\
0283         type RDPCS_PHY_DP_TX3_DATA_EN;\
0284         type RDPCS_PHY_DP_TX0_PSTATE;\
0285         type RDPCS_PHY_DP_TX1_PSTATE;\
0286         type RDPCS_PHY_DP_TX2_PSTATE;\
0287         type RDPCS_PHY_DP_TX3_PSTATE;\
0288         type RDPCS_PHY_DP_TX0_MPLL_EN;\
0289         type RDPCS_PHY_DP_TX1_MPLL_EN;\
0290         type RDPCS_PHY_DP_TX2_MPLL_EN;\
0291         type RDPCS_PHY_DP_TX3_MPLL_EN;\
0292         type RDPCS_TX_FIFO_LANE0_EN;\
0293         type RDPCS_TX_FIFO_LANE1_EN;\
0294         type RDPCS_TX_FIFO_LANE2_EN;\
0295         type RDPCS_TX_FIFO_LANE3_EN;\
0296         type RDPCS_EXT_REFCLK_EN;\
0297         type RDPCS_TX_FIFO_EN;\
0298         type UNIPHY_LINK_ENABLE;\
0299         type UNIPHY_CHANNEL0_XBAR_SOURCE;\
0300         type UNIPHY_CHANNEL1_XBAR_SOURCE;\
0301         type UNIPHY_CHANNEL2_XBAR_SOURCE;\
0302         type UNIPHY_CHANNEL3_XBAR_SOURCE;\
0303         type UNIPHY_CHANNEL0_INVERT;\
0304         type UNIPHY_CHANNEL1_INVERT;\
0305         type UNIPHY_CHANNEL2_INVERT;\
0306         type UNIPHY_CHANNEL3_INVERT;\
0307         type UNIPHY_LINK_ENABLE_HPD_MASK;\
0308         type UNIPHY_LANE_STAGGER_DELAY;\
0309         type RDPCS_SRAMCLK_BYPASS;\
0310         type RDPCS_SRAMCLK_EN;\
0311         type RDPCS_SRAMCLK_CLOCK_ON;\
0312         type DPCS_TX_FIFO_EN;\
0313         type RDPCS_PHY_DP_TX0_DISABLE;\
0314         type RDPCS_PHY_DP_TX1_DISABLE;\
0315         type RDPCS_PHY_DP_TX2_DISABLE;\
0316         type RDPCS_PHY_DP_TX3_DISABLE;\
0317         type RDPCS_PHY_DP_TX0_CLK_RDY;\
0318         type RDPCS_PHY_DP_TX1_CLK_RDY;\
0319         type RDPCS_PHY_DP_TX2_CLK_RDY;\
0320         type RDPCS_PHY_DP_TX3_CLK_RDY;\
0321         type RDPCS_PHY_DP_TX0_REQ;\
0322         type RDPCS_PHY_DP_TX1_REQ;\
0323         type RDPCS_PHY_DP_TX2_REQ;\
0324         type RDPCS_PHY_DP_TX3_REQ;\
0325         type RDPCS_PHY_DP_TX0_ACK;\
0326         type RDPCS_PHY_DP_TX1_ACK;\
0327         type RDPCS_PHY_DP_TX2_ACK;\
0328         type RDPCS_PHY_DP_TX3_ACK;\
0329         type RDPCS_PHY_DP_TX0_RESET;\
0330         type RDPCS_PHY_DP_TX1_RESET;\
0331         type RDPCS_PHY_DP_TX2_RESET;\
0332         type RDPCS_PHY_DP_TX3_RESET;\
0333         type RDPCS_PHY_RESET;\
0334         type RDPCS_PHY_CR_MUX_SEL;\
0335         type RDPCS_PHY_REF_RANGE;\
0336         type RDPCS_PHY_DP4_POR;\
0337         type RDPCS_SRAM_BYPASS;\
0338         type RDPCS_SRAM_EXT_LD_DONE;\
0339         type RDPCS_PHY_DP_TX0_TERM_CTRL;\
0340         type RDPCS_PHY_DP_TX1_TERM_CTRL;\
0341         type RDPCS_PHY_DP_TX2_TERM_CTRL;\
0342         type RDPCS_PHY_DP_TX3_TERM_CTRL;\
0343         type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
0344         type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
0345         type RDPCS_PHY_DP_MPLLB_SSC_EN;\
0346         type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
0347         type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
0348         type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
0349         type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
0350         type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
0351         type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
0352         type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
0353         type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
0354         type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
0355         type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
0356         type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
0357         type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
0358         type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
0359         type RDPCS_PHY_TX_VBOOST_LVL;\
0360         type RDPCS_PHY_HDMIMODE_ENABLE;\
0361         type RDPCS_PHY_DP_REF_CLK_EN;\
0362         type RDPCS_PLL_UPDATE_DATA;\
0363         type RDPCS_SRAM_INIT_DONE;\
0364         type RDPCS_TX_CR_ADDR;\
0365         type RDPCS_TX_CR_DATA;\
0366         type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
0367         type RDPCS_PHY_DP_MPLLB_STATE;\
0368         type RDPCS_PHY_DP_TX0_WIDTH;\
0369         type RDPCS_PHY_DP_TX0_RATE;\
0370         type RDPCS_PHY_DP_TX1_WIDTH;\
0371         type RDPCS_PHY_DP_TX1_RATE;\
0372         type RDPCS_PHY_DP_TX2_WIDTH;\
0373         type RDPCS_PHY_DP_TX2_RATE;\
0374         type RDPCS_PHY_DP_TX3_WIDTH;\
0375         type RDPCS_PHY_DP_TX3_RATE;\
0376         type DPCS_SYMCLK_CLOCK_ON;\
0377         type DPCS_SYMCLK_GATE_DIS;\
0378         type DPCS_SYMCLK_EN;\
0379         type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
0380         type RDPCS_SYMCLK_DIV2_GATE_DIS;\
0381         type RDPCS_SYMCLK_DIV2_EN;\
0382         type DPCS_TX_DATA_SWAP;\
0383         type DPCS_TX_DATA_ORDER_INVERT;\
0384         type DPCS_TX_FIFO_RD_START_DELAY;\
0385         type RDPCS_TX_FIFO_RD_START_DELAY;\
0386         type RDPCS_REG_FIFO_ERROR_MASK;\
0387         type RDPCS_TX_FIFO_ERROR_MASK;\
0388         type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
0389         type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
0390         type RDPCS_PHY_DPALT_DP4;\
0391         type RDPCS_PHY_DPALT_DISABLE;\
0392         type RDPCS_PHY_DPALT_DISABLE_ACK;\
0393         type RDPCS_PHY_DP_MPLLB_V2I;\
0394         type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
0395         type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
0396         type RDPCS_PHY_RX_VREF_CTRL;\
0397         type RDPCS_PHY_DP_MPLLB_CP_INT;\
0398         type RDPCS_PHY_DP_MPLLB_CP_PROP;\
0399         type RDPCS_PHY_RX_REF_LD_VAL;\
0400         type RDPCS_PHY_RX_VCO_LD_VAL;\
0401         type DPCSTX_DEBUG_CONFIG; \
0402         type RDPCSTX_DEBUG_CONFIG; \
0403         type RDPCS_PHY_DP_TX0_EQ_MAIN;\
0404         type RDPCS_PHY_DP_TX0_EQ_PRE;\
0405         type RDPCS_PHY_DP_TX0_EQ_POST;\
0406         type RDPCS_PHY_DP_TX1_EQ_MAIN;\
0407         type RDPCS_PHY_DP_TX1_EQ_PRE;\
0408         type RDPCS_PHY_DP_TX1_EQ_POST;\
0409         type RDPCS_PHY_DP_TX2_EQ_MAIN;\
0410         type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
0411         type RDPCS_PHY_DP_TX2_EQ_PRE;\
0412         type RDPCS_PHY_DP_TX2_EQ_POST;\
0413         type RDPCS_PHY_DP_TX3_EQ_MAIN;\
0414         type RDPCS_PHY_DCO_RANGE;\
0415         type RDPCS_PHY_DCO_FINETUNE;\
0416         type RDPCS_PHY_DP_TX3_EQ_PRE;\
0417         type RDPCS_PHY_DP_TX3_EQ_POST;\
0418         type RDPCS_PHY_SUP_PRE_HP;\
0419         type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
0420         type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
0421         type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
0422         type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
0423         type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
0424         type UNIPHYA_SOFT_RESET;\
0425         type UNIPHYB_SOFT_RESET;\
0426         type UNIPHYC_SOFT_RESET;\
0427         type UNIPHYD_SOFT_RESET;\
0428         type UNIPHYE_SOFT_RESET;\
0429         type UNIPHYF_SOFT_RESET
0430
0431 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
0432     type DIG_LANE0EN;\
0433     type DIG_LANE1EN;\
0434     type DIG_LANE2EN;\
0435     type DIG_LANE3EN;\
0436     type DIG_CLK_EN;\
0437     type SYMCLKA_CLOCK_ENABLE;\
0438     type DPHY_FEC_EN;\
0439     type DPHY_FEC_READY_SHADOW;\
0440     type DPHY_FEC_ACTIVE_STATUS;\
0441     DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
0442     type VCO_LD_VAL_OVRD;\
0443     type VCO_LD_VAL_OVRD_EN;\
0444     type REF_LD_VAL_OVRD;\
0445     type REF_LD_VAL_OVRD_EN;\
0446     type AUX_RX_START_WINDOW; \
0447     type AUX_RX_HALF_SYM_DETECT_LEN; \
0448     type AUX_RX_TRANSITION_FILTER_EN; \
0449     type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
0450     type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
0451     type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
0452     type AUX_RX_PHASE_DETECT_LEN; \
0453     type AUX_RX_DETECTION_THRESHOLD; \
0454     type AUX_TX_PRECHARGE_LEN; \
0455     type AUX_TX_PRECHARGE_SYMBOLS; \
0456     type AUX_MODE_DET_CHECK_DELAY;\
0457     type DPCS_DBG_CBUS_DIS;\
0458     type AUX_RX_PRECHARGE_SKIP;\
0459     type AUX_RX_TIMEOUT_LEN;\
0460     type AUX_RX_TIMEOUT_LEN_MUL
0461
0462 #define DCN30_LINK_ENCODER_REG_FIELD_LIST(type) \
0463     type TMDS_SYNC_DCBAL_EN;\
0464     type PHY_HPO_DIG_SRC_SEL;\
0465     type PHY_HPO_ENC_SRC_SEL;\
0466     type DPCS_TX_HDMI_FRL_MODE;\
0467     type DPCS_TX_DATA_SWAP_10_BIT;\
0468     type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
0469     type RDPCS_TX_CLK_EN
0470
0471 #define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
0472     type ENC_TYPE_SEL;\
0473     type HPO_DP_ENC_SEL;\
0474     type HPO_HDMI_ENC_SEL
0475
0476 #define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \
0477     type DIG_FIFO_OUTPUT_PIXEL_MODE
0478
0479 struct dcn10_link_enc_shift {
0480     DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
0481     DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
0482     DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
0483     DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
0484     DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
0485 };
0486
0487 struct dcn10_link_enc_mask {
0488     DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
0489     DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
0490     DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
0491     DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
0492     DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
0493 };
0494
0495 struct dcn10_link_encoder {
0496     struct link_encoder base;
0497     const struct dcn10_link_enc_registers *link_regs;
0498     const struct dcn10_link_enc_aux_registers *aux_regs;
0499     const struct dcn10_link_enc_hpd_registers *hpd_regs;
0500     const struct dcn10_link_enc_shift *link_shift;
0501     const struct dcn10_link_enc_mask *link_mask;
0502 };
0503
0504
0505 void dcn10_link_encoder_construct(
0506     struct dcn10_link_encoder *enc10,
0507     const struct encoder_init_data *init_data,
0508     const struct encoder_feature_support *enc_features,
0509     const struct dcn10_link_enc_registers *link_regs,
0510     const struct dcn10_link_enc_aux_registers *aux_regs,
0511     const struct dcn10_link_enc_hpd_registers *hpd_regs,
0512     const struct dcn10_link_enc_shift *link_shift,
0513     const struct dcn10_link_enc_mask *link_mask);
0514
0515 bool dcn10_link_encoder_validate_dvi_output(
0516     const struct dcn10_link_encoder *enc10,
0517     enum signal_type connector_signal,
0518     enum signal_type signal,
0519     const struct dc_crtc_timing *crtc_timing);
0520
0521 bool dcn10_link_encoder_validate_rgb_output(
0522     const struct dcn10_link_encoder *enc10,
0523     const struct dc_crtc_timing *crtc_timing);
0524
0525 bool dcn10_link_encoder_validate_dp_output(
0526     const struct dcn10_link_encoder *enc10,
0527     const struct dc_crtc_timing *crtc_timing);
0528
0529 bool dcn10_link_encoder_validate_wireless_output(
0530     const struct dcn10_link_encoder *enc10,
0531     const struct dc_crtc_timing *crtc_timing);
0532
0533 bool dcn10_link_encoder_validate_output_with_stream(
0534     struct link_encoder *enc,
0535     const struct dc_stream_state *stream);
0536
0537 /****************** HW programming ************************/
0538
0539 /* initialize HW */  /* why do we initialze aux in here? */
0540 void dcn10_link_encoder_hw_init(struct link_encoder *enc);
0541
0542 void dcn10_link_encoder_destroy(struct link_encoder **enc);
0543
0544 /* program DIG_MODE in DIG_BE */
0545 /* TODO can this be combined with enable_output? */
0546 void dcn10_link_encoder_setup(
0547     struct link_encoder *enc,
0548     enum signal_type signal);
0549
0550 void enc1_configure_encoder(
0551     struct dcn10_link_encoder *enc10,
0552     const struct dc_link_settings *link_settings);
0553
0554 /* enables TMDS PHY output */
0555 /* TODO: still need depth or just pass in adjusted pixel clock? */
0556 void dcn10_link_encoder_enable_tmds_output(
0557     struct link_encoder *enc,
0558     enum clock_source_id clock_source,
0559     enum dc_color_depth color_depth,
0560     enum signal_type signal,
0561     uint32_t pixel_clock);
0562
0563 void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
0564     struct link_encoder *enc,
0565     enum clock_source_id clock_source,
0566     enum dc_color_depth color_depth,
0567     enum signal_type signal,
0568     uint32_t pixel_clock);
0569
0570 /* enables DP PHY output */
0571 void dcn10_link_encoder_enable_dp_output(
0572     struct link_encoder *enc,
0573     const struct dc_link_settings *link_settings,
0574     enum clock_source_id clock_source);
0575
0576 /* enables DP PHY output in MST mode */
0577 void dcn10_link_encoder_enable_dp_mst_output(
0578     struct link_encoder *enc,
0579     const struct dc_link_settings *link_settings,
0580     enum clock_source_id clock_source);
0581
0582 /* disable PHY output */
0583 void dcn10_link_encoder_disable_output(
0584     struct link_encoder *enc,
0585     enum signal_type signal);
0586
0587 /* set DP lane settings */
0588 void dcn10_link_encoder_dp_set_lane_settings(
0589     struct link_encoder *enc,
0590     const struct dc_link_settings *link_settings,
0591     const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
0592
0593 void dcn10_link_encoder_dp_set_phy_pattern(
0594     struct link_encoder *enc,
0595     const struct encoder_set_dp_phy_pattern_param *param);
0596
0597 /* programs DP MST VC payload allocation */
0598 void dcn10_link_encoder_update_mst_stream_allocation_table(
0599     struct link_encoder *enc,
0600     const struct link_mst_stream_allocation_table *table);
0601
0602 void dcn10_link_encoder_connect_dig_be_to_fe(
0603     struct link_encoder *enc,
0604     enum engine_id engine,
0605     bool connect);
0606
0607 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
0608     struct link_encoder *enc,
0609     uint32_t index);
0610
0611 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
0612
0613 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
0614
0615 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
0616             bool exit_link_training_required);
0617
0618 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
0619             unsigned int sdp_transmit_line_num_deadline);
0620
0621 bool dcn10_is_dig_enabled(struct link_encoder *enc);
0622
0623 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
0624
0625 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
0626
0627 enum signal_type dcn10_get_dig_mode(
0628     struct link_encoder *enc);
0629
0630 void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
0631     struct dc_link_settings *link_settings);
0632 #endif /* __DC_LINK_ENCODER__DCN10_H__ */