Back to home page

OSCL-LXR
 
 

     

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 
0025 #ifndef __DC_MEM_INPUT_DCN10_H__
0026 #define __DC_MEM_INPUT_DCN10_H__
0027 
0028 #include "hubp.h"
0029 
0030 #define TO_DCN10_HUBP(hubp)\
0031     container_of(hubp, struct dcn10_hubp, base)
0032 
0033 /* Register address initialization macro for all ASICs (including those with reduced functionality) */
0034 #define HUBP_REG_LIST_DCN(id)\
0035     SRI(DCHUBP_CNTL, HUBP, id),\
0036     SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
0037     SRI(HUBPREQ_DEBUG, HUBP, id),\
0038     SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
0039     SRI(DCSURF_TILING_CONFIG, HUBP, id),\
0040     SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
0041     SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
0042     SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
0043     SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
0044     SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
0045     SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
0046     SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
0047     SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
0048     SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
0049     SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
0050     SRI(DCSURF_SEC_VIEWPORT_DIMENSION_C, HUBP, id), \
0051     SRI(DCSURF_SEC_VIEWPORT_START_C, HUBP, id), \
0052     SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
0053     SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
0054     SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
0055     SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
0056     SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
0057     SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
0058     SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
0059     SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
0060     SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
0061     SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
0062     SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
0063     SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
0064     SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
0065     SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
0066     SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
0067     SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
0068     SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
0069     SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
0070     SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
0071     SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
0072     SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
0073     SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
0074     SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
0075     SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
0076     SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
0077     SRI(DCSURF_SURFACE_FLIP_INTERRUPT, HUBPREQ, id),\
0078     SRI(HUBPRET_CONTROL, HUBPRET, id),\
0079     SRI(HUBPRET_READ_LINE_STATUS, HUBPRET, id),\
0080     SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
0081     SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
0082     SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
0083     SRI(BLANK_OFFSET_0, HUBPREQ, id),\
0084     SRI(BLANK_OFFSET_1, HUBPREQ, id),\
0085     SRI(DST_DIMENSIONS, HUBPREQ, id),\
0086     SRI(DST_AFTER_SCALER, HUBPREQ, id),\
0087     SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
0088     SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
0089     SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
0090     SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
0091     SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
0092     SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
0093     SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
0094     SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
0095     SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
0096     SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
0097     SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
0098     SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
0099     SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
0100     SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
0101     SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
0102     SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
0103     SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
0104     SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
0105     SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
0106     SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
0107     SRI(HUBP_CLK_CNTL, HUBP, id)
0108 
0109 /* Register address initialization macro for ASICs with VM */
0110 #define HUBP_REG_LIST_DCN_VM(id)\
0111     SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
0112     SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
0113     SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
0114     SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
0115     SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
0116 
0117 #define HUBP_REG_LIST_DCN10(id)\
0118     HUBP_REG_LIST_DCN(id),\
0119     HUBP_REG_LIST_DCN_VM(id),\
0120     SRI(PREFETCH_SETTINS, HUBPREQ, id),\
0121     SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
0122     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
0123     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
0124     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
0125     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
0126     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
0127     SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
0128     SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
0129     SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
0130     SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, HUBPREQ, id),\
0131     SRI(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, HUBPREQ, id),\
0132     SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, HUBPREQ, id),\
0133     SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
0134     SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
0135     SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
0136     SRI(CURSOR_SETTINS, HUBPREQ, id), \
0137     SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
0138     SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
0139     SRI(CURSOR_SIZE, CURSOR, id), \
0140     SRI(CURSOR_CONTROL, CURSOR, id), \
0141     SRI(CURSOR_POSITION, CURSOR, id), \
0142     SRI(CURSOR_HOT_SPOT, CURSOR, id), \
0143     SRI(CURSOR_DST_OFFSET, CURSOR, id)
0144 
0145 #define HUBP_COMMON_REG_VARIABLE_LIST \
0146     uint32_t DCHUBP_CNTL; \
0147     uint32_t HUBPREQ_DEBUG_DB; \
0148     uint32_t HUBPREQ_DEBUG; \
0149     uint32_t DCSURF_ADDR_CONFIG; \
0150     uint32_t DCSURF_TILING_CONFIG; \
0151     uint32_t DCSURF_SURFACE_PITCH; \
0152     uint32_t DCSURF_SURFACE_PITCH_C; \
0153     uint32_t DCSURF_SURFACE_CONFIG; \
0154     uint32_t DCSURF_FLIP_CONTROL; \
0155     uint32_t DCSURF_PRI_VIEWPORT_DIMENSION; \
0156     uint32_t DCSURF_PRI_VIEWPORT_START; \
0157     uint32_t DCSURF_SEC_VIEWPORT_DIMENSION; \
0158     uint32_t DCSURF_SEC_VIEWPORT_START; \
0159     uint32_t DCSURF_PRI_VIEWPORT_DIMENSION_C; \
0160     uint32_t DCSURF_PRI_VIEWPORT_START_C; \
0161     uint32_t DCSURF_SEC_VIEWPORT_DIMENSION_C; \
0162     uint32_t DCSURF_SEC_VIEWPORT_START_C; \
0163     uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; \
0164     uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; \
0165     uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH; \
0166     uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS; \
0167     uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH; \
0168     uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS; \
0169     uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH; \
0170     uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS; \
0171     uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; \
0172     uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; \
0173     uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C; \
0174     uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_C; \
0175     uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C; \
0176     uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C; \
0177     uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C; \
0178     uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_C; \
0179     uint32_t DCSURF_SURFACE_INUSE; \
0180     uint32_t DCSURF_SURFACE_INUSE_HIGH; \
0181     uint32_t DCSURF_SURFACE_INUSE_C; \
0182     uint32_t DCSURF_SURFACE_INUSE_HIGH_C; \
0183     uint32_t DCSURF_SURFACE_EARLIEST_INUSE; \
0184     uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH; \
0185     uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C; \
0186     uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C; \
0187     uint32_t DCSURF_SURFACE_CONTROL; \
0188     uint32_t DCSURF_SURFACE_FLIP_INTERRUPT; \
0189     uint32_t HUBPRET_CONTROL; \
0190     uint32_t HUBPRET_READ_LINE_STATUS; \
0191     uint32_t DCN_EXPANSION_MODE; \
0192     uint32_t DCHUBP_REQ_SIZE_CONFIG; \
0193     uint32_t DCHUBP_REQ_SIZE_CONFIG_C; \
0194     uint32_t BLANK_OFFSET_0; \
0195     uint32_t BLANK_OFFSET_1; \
0196     uint32_t DST_DIMENSIONS; \
0197     uint32_t DST_AFTER_SCALER; \
0198     uint32_t PREFETCH_SETTINS; \
0199     uint32_t PREFETCH_SETTINGS; \
0200     uint32_t VBLANK_PARAMETERS_0; \
0201     uint32_t REF_FREQ_TO_PIX_FREQ; \
0202     uint32_t VBLANK_PARAMETERS_1; \
0203     uint32_t VBLANK_PARAMETERS_3; \
0204     uint32_t NOM_PARAMETERS_0; \
0205     uint32_t NOM_PARAMETERS_1; \
0206     uint32_t NOM_PARAMETERS_4; \
0207     uint32_t NOM_PARAMETERS_5; \
0208     uint32_t PER_LINE_DELIVERY_PRE; \
0209     uint32_t PER_LINE_DELIVERY; \
0210     uint32_t PREFETCH_SETTINS_C; \
0211     uint32_t PREFETCH_SETTINGS_C; \
0212     uint32_t VBLANK_PARAMETERS_2; \
0213     uint32_t VBLANK_PARAMETERS_4; \
0214     uint32_t NOM_PARAMETERS_2; \
0215     uint32_t NOM_PARAMETERS_3; \
0216     uint32_t NOM_PARAMETERS_6; \
0217     uint32_t NOM_PARAMETERS_7; \
0218     uint32_t DCN_TTU_QOS_WM; \
0219     uint32_t DCN_GLOBAL_TTU_CNTL; \
0220     uint32_t DCN_SURF0_TTU_CNTL0; \
0221     uint32_t DCN_SURF0_TTU_CNTL1; \
0222     uint32_t DCN_SURF1_TTU_CNTL0; \
0223     uint32_t DCN_SURF1_TTU_CNTL1; \
0224     uint32_t DCN_CUR0_TTU_CNTL0; \
0225     uint32_t DCN_CUR0_TTU_CNTL1; \
0226     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
0227     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
0228     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
0229     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB; \
0230     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB; \
0231     uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB; \
0232     uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB; \
0233     uint32_t DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB; \
0234     uint32_t DCN_VM_MX_L1_TLB_CNTL; \
0235     uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; \
0236     uint32_t DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; \
0237     uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB; \
0238     uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB; \
0239     uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB; \
0240     uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
0241     uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
0242     uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
0243     uint32_t CURSOR_SETTINS; \
0244     uint32_t CURSOR_SETTINGS; \
0245     uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
0246     uint32_t CURSOR_SURFACE_ADDRESS; \
0247     uint32_t CURSOR_SIZE; \
0248     uint32_t CURSOR_CONTROL; \
0249     uint32_t CURSOR_POSITION; \
0250     uint32_t CURSOR_HOT_SPOT; \
0251     uint32_t CURSOR_DST_OFFSET; \
0252     uint32_t HUBP_CLK_CNTL
0253 
0254 #define HUBP_SF(reg_name, field_name, post_fix)\
0255     .field_name = reg_name ## __ ## field_name ## post_fix
0256 
0257 /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
0258 /*1.x, 2.x, and 3.x*/
0259 #define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
0260     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
0261     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
0262     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
0263     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
0264     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
0265     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
0266     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
0267     HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
0268     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
0269     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
0270     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
0271     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\
0272     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\
0273     HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
0274     HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
0275     HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
0276     HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
0277     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
0278     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
0279     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
0280     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
0281     HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
0282     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
0283     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
0284     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
0285     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
0286     HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
0287     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
0288     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
0289     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
0290     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
0291     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
0292     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
0293     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
0294     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
0295     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
0296     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
0297     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
0298     HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
0299     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
0300     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
0301     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
0302     HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
0303     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0304     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
0305     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0306     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
0307     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
0308     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
0309     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
0310     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
0311     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
0312     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
0313     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
0314     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
0315     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
0316     HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
0317     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
0318     HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
0319     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
0320     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
0321     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
0322     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
0323     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
0324     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
0325     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
0326     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
0327     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
0328     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
0329     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
0330     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
0331     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
0332     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
0333     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
0334     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
0335     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
0336     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
0337     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
0338     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
0339     HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
0340     HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
0341     HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
0342     HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
0343     HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_STATUS, PIPE_READ_VBLANK, mask_sh),\
0344     HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
0345     HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
0346     HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
0347     HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
0348     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
0349     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
0350     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
0351     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
0352     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
0353     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
0354     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
0355     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
0356     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
0357     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
0358     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
0359     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
0360     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
0361     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
0362     HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
0363     HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
0364     HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
0365     HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
0366     HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
0367     HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
0368     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
0369     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
0370     HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
0371     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
0372     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
0373     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
0374     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
0375     HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
0376     HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
0377     HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
0378     HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
0379     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
0380     HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
0381     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
0382     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
0383     HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
0384     HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
0385     HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
0386     HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
0387     HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
0388     HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
0389     HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
0390     HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
0391     HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
0392 /*2.x and 1.x only*/
0393 #define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
0394     HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
0395     HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
0396     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
0397     HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
0398 
0399 /*2.x and 1.x only*/
0400 #define HUBP_MASK_SH_LIST_DCN(mask_sh)\
0401     HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
0402 
0403 /* Mask/shift struct generation macro for ASICs with VM */
0404 #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
0405     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
0406     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
0407     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
0408     HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
0409     HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
0410     HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
0411     HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
0412     HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
0413     HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
0414     HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
0415 
0416 #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
0417     HUBP_MASK_SH_LIST_DCN(mask_sh),\
0418     HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
0419     HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
0420     HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
0421     HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
0422     HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
0423     HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
0424     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\
0425     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\
0426     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\
0427     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\
0428     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\
0429     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\
0430     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\
0431     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\
0432     HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\
0433     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\
0434     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
0435     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
0436     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
0437     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
0438     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
0439     HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
0440     HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \
0441     HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
0442     HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
0443     HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
0444     HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
0445     HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
0446     HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
0447     HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
0448     HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
0449     HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
0450     HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
0451     HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
0452     HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
0453     HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
0454     HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
0455     HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
0456 
0457 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
0458     type HUBP_BLANK_EN;\
0459     type HUBP_DISABLE;\
0460     type HUBP_TTU_DISABLE;\
0461     type HUBP_NO_OUTSTANDING_REQ;\
0462     type HUBP_VTG_SEL;\
0463     type HUBP_UNDERFLOW_STATUS;\
0464     type HUBP_UNDERFLOW_CLEAR;\
0465     type HUBP_IN_BLANK;\
0466     type NUM_PIPES;\
0467     type NUM_BANKS;\
0468     type PIPE_INTERLEAVE;\
0469     type NUM_SE;\
0470     type NUM_RB_PER_SE;\
0471     type MAX_COMPRESSED_FRAGS;\
0472     type SW_MODE;\
0473     type META_LINEAR;\
0474     type RB_ALIGNED;\
0475     type PIPE_ALIGNED;\
0476     type PITCH;\
0477     type META_PITCH;\
0478     type PITCH_C;\
0479     type META_PITCH_C;\
0480     type ROTATION_ANGLE;\
0481     type H_MIRROR_EN;\
0482     type SURFACE_PIXEL_FORMAT;\
0483     type SURFACE_FLIP_TYPE;\
0484     type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
0485     type SURFACE_FLIP_IN_STEREOSYNC;\
0486     type SURFACE_UPDATE_LOCK;\
0487     type SURFACE_FLIP_PENDING;\
0488     type PRI_VIEWPORT_WIDTH; \
0489     type PRI_VIEWPORT_HEIGHT; \
0490     type PRI_VIEWPORT_X_START; \
0491     type PRI_VIEWPORT_Y_START; \
0492     type SEC_VIEWPORT_WIDTH; \
0493     type SEC_VIEWPORT_HEIGHT; \
0494     type SEC_VIEWPORT_X_START; \
0495     type SEC_VIEWPORT_Y_START; \
0496     type PRI_VIEWPORT_WIDTH_C; \
0497     type PRI_VIEWPORT_HEIGHT_C; \
0498     type PRI_VIEWPORT_X_START_C; \
0499     type PRI_VIEWPORT_Y_START_C; \
0500     type SEC_VIEWPORT_WIDTH_C; \
0501     type SEC_VIEWPORT_HEIGHT_C; \
0502     type SEC_VIEWPORT_X_START_C; \
0503     type SEC_VIEWPORT_Y_START_C; \
0504     type PRIMARY_SURFACE_ADDRESS_HIGH;\
0505     type PRIMARY_SURFACE_ADDRESS;\
0506     type SECONDARY_SURFACE_ADDRESS_HIGH;\
0507     type SECONDARY_SURFACE_ADDRESS;\
0508     type PRIMARY_META_SURFACE_ADDRESS_HIGH;\
0509     type PRIMARY_META_SURFACE_ADDRESS;\
0510     type SECONDARY_META_SURFACE_ADDRESS_HIGH;\
0511     type SECONDARY_META_SURFACE_ADDRESS;\
0512     type PRIMARY_SURFACE_ADDRESS_HIGH_C;\
0513     type PRIMARY_SURFACE_ADDRESS_C;\
0514     type SECONDARY_SURFACE_ADDRESS_HIGH_C;\
0515     type SECONDARY_SURFACE_ADDRESS_C;\
0516     type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
0517     type PRIMARY_META_SURFACE_ADDRESS_C;\
0518     type SECONDARY_META_SURFACE_ADDRESS_HIGH_C;\
0519     type SECONDARY_META_SURFACE_ADDRESS_C;\
0520     type SURFACE_INUSE_ADDRESS;\
0521     type SURFACE_INUSE_ADDRESS_HIGH;\
0522     type SURFACE_INUSE_ADDRESS_C;\
0523     type SURFACE_INUSE_ADDRESS_HIGH_C;\
0524     type SURFACE_EARLIEST_INUSE_ADDRESS;\
0525     type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
0526     type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
0527     type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
0528     type PRIMARY_SURFACE_TMZ;\
0529     type PRIMARY_SURFACE_TMZ_C;\
0530     type SECONDARY_SURFACE_TMZ;\
0531     type SECONDARY_SURFACE_TMZ_C;\
0532     type PRIMARY_META_SURFACE_TMZ;\
0533     type PRIMARY_META_SURFACE_TMZ_C;\
0534     type SECONDARY_META_SURFACE_TMZ;\
0535     type SECONDARY_META_SURFACE_TMZ_C;\
0536     type PRIMARY_SURFACE_DCC_EN;\
0537     type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
0538     type SECONDARY_SURFACE_DCC_EN;\
0539     type SECONDARY_SURFACE_DCC_IND_64B_BLK;\
0540     type SURFACE_FLIP_INT_MASK;\
0541     type DET_BUF_PLANE1_BASE_ADDRESS;\
0542     type CROSSBAR_SRC_CB_B;\
0543     type CROSSBAR_SRC_CR_R;\
0544     type PIPE_READ_VBLANK;\
0545     type DRQ_EXPANSION_MODE;\
0546     type PRQ_EXPANSION_MODE;\
0547     type MRQ_EXPANSION_MODE;\
0548     type CRQ_EXPANSION_MODE;\
0549     type CHUNK_SIZE;\
0550     type MIN_CHUNK_SIZE;\
0551     type META_CHUNK_SIZE;\
0552     type MIN_META_CHUNK_SIZE;\
0553     type DPTE_GROUP_SIZE;\
0554     type MPTE_GROUP_SIZE;\
0555     type SWATH_HEIGHT;\
0556     type PTE_ROW_HEIGHT_LINEAR;\
0557     type CHUNK_SIZE_C;\
0558     type MIN_CHUNK_SIZE_C;\
0559     type META_CHUNK_SIZE_C;\
0560     type MIN_META_CHUNK_SIZE_C;\
0561     type DPTE_GROUP_SIZE_C;\
0562     type MPTE_GROUP_SIZE_C;\
0563     type SWATH_HEIGHT_C;\
0564     type PTE_ROW_HEIGHT_LINEAR_C;\
0565     type REFCYC_H_BLANK_END;\
0566     type DLG_V_BLANK_END;\
0567     type MIN_DST_Y_NEXT_START;\
0568     type REFCYC_PER_HTOTAL;\
0569     type REFCYC_X_AFTER_SCALER;\
0570     type DST_Y_AFTER_SCALER;\
0571     type DST_Y_PREFETCH;\
0572     type VRATIO_PREFETCH;\
0573     type DST_Y_PER_VM_VBLANK;\
0574     type DST_Y_PER_ROW_VBLANK;\
0575     type REF_FREQ_TO_PIX_FREQ;\
0576     type REFCYC_PER_PTE_GROUP_VBLANK_L;\
0577     type REFCYC_PER_META_CHUNK_VBLANK_L;\
0578     type DST_Y_PER_PTE_ROW_NOM_L;\
0579     type REFCYC_PER_PTE_GROUP_NOM_L;\
0580     type DST_Y_PER_META_ROW_NOM_L;\
0581     type REFCYC_PER_META_CHUNK_NOM_L;\
0582     type REFCYC_PER_LINE_DELIVERY_PRE_L;\
0583     type REFCYC_PER_LINE_DELIVERY_PRE_C;\
0584     type REFCYC_PER_LINE_DELIVERY_L;\
0585     type REFCYC_PER_LINE_DELIVERY_C;\
0586     type VRATIO_PREFETCH_C;\
0587     type REFCYC_PER_PTE_GROUP_VBLANK_C;\
0588     type REFCYC_PER_META_CHUNK_VBLANK_C;\
0589     type DST_Y_PER_PTE_ROW_NOM_C;\
0590     type REFCYC_PER_PTE_GROUP_NOM_C;\
0591     type DST_Y_PER_META_ROW_NOM_C;\
0592     type REFCYC_PER_META_CHUNK_NOM_C;\
0593     type QoS_LEVEL_LOW_WM;\
0594     type QoS_LEVEL_HIGH_WM;\
0595     type MIN_TTU_VBLANK;\
0596     type QoS_LEVEL_FLIP;\
0597     type REFCYC_PER_REQ_DELIVERY;\
0598     type QoS_LEVEL_FIXED;\
0599     type QoS_RAMP_DISABLE;\
0600     type REFCYC_PER_REQ_DELIVERY_PRE;\
0601     type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB;\
0602     type VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB;\
0603     type VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB;\
0604     type VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB;\
0605     type VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB;\
0606     type VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB;\
0607     type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
0608     type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM;\
0609     type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\
0610     type ENABLE_L1_TLB;\
0611     type SYSTEM_ACCESS_MODE;\
0612     type HUBP_CLOCK_ENABLE;\
0613     type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
0614     type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
0615     type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
0616     type MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB;\
0617     type MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB;\
0618     type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB;\
0619     type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
0620     type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
0621     type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
0622     type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
0623     type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
0624     type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
0625     /* todo:  get these from GVM instead of reading registers ourselves */\
0626     type PAGE_DIRECTORY_ENTRY_HI32;\
0627     type PAGE_DIRECTORY_ENTRY_LO32;\
0628     type LOGICAL_PAGE_NUMBER_HI4;\
0629     type LOGICAL_PAGE_NUMBER_LO32;\
0630     type PHYSICAL_PAGE_ADDR_HI4;\
0631     type PHYSICAL_PAGE_ADDR_LO32;\
0632     type PHYSICAL_PAGE_NUMBER_MSB;\
0633     type PHYSICAL_PAGE_NUMBER_LSB;\
0634     type LOGICAL_ADDR;\
0635     type CURSOR0_DST_Y_OFFSET; \
0636     type CURSOR0_CHUNK_HDL_ADJUST; \
0637     type CURSOR_SURFACE_ADDRESS_HIGH; \
0638     type CURSOR_SURFACE_ADDRESS; \
0639     type CURSOR_WIDTH; \
0640     type CURSOR_HEIGHT; \
0641     type CURSOR_MODE; \
0642     type CURSOR_2X_MAGNIFY; \
0643     type CURSOR_PITCH; \
0644     type CURSOR_LINES_PER_CHUNK; \
0645     type CURSOR_ENABLE; \
0646     type CURSOR_X_POSITION; \
0647     type CURSOR_Y_POSITION; \
0648     type CURSOR_HOT_SPOT_X; \
0649     type CURSOR_HOT_SPOT_Y; \
0650     type CURSOR_DST_X_OFFSET; \
0651     type OUTPUT_FP
0652 
0653 #define DCN_HUBP_REG_FIELD_LIST(type) \
0654     DCN_HUBP_REG_FIELD_BASE_LIST(type);\
0655     type ALPHA_PLANE_EN
0656 
0657 struct dcn_mi_registers {
0658     HUBP_COMMON_REG_VARIABLE_LIST;
0659 };
0660 
0661 struct dcn_mi_shift {
0662     DCN_HUBP_REG_FIELD_LIST(uint8_t);
0663 };
0664 
0665 struct dcn_mi_mask {
0666     DCN_HUBP_REG_FIELD_LIST(uint32_t);
0667 };
0668 
0669 struct dcn_hubp_state {
0670     struct _vcs_dpi_display_dlg_regs_st dlg_attr;
0671     struct _vcs_dpi_display_ttu_regs_st ttu_attr;
0672     struct _vcs_dpi_display_rq_regs_st rq_regs;
0673     uint32_t pixel_format;
0674     uint32_t inuse_addr_hi;
0675     uint32_t inuse_addr_lo;
0676     uint32_t viewport_width;
0677     uint32_t viewport_height;
0678     uint32_t rotation_angle;
0679     uint32_t h_mirror_en;
0680     uint32_t sw_mode;
0681     uint32_t dcc_en;
0682     uint32_t blank_en;
0683     uint32_t clock_en;
0684     uint32_t underflow_status;
0685     uint32_t ttu_disable;
0686     uint32_t min_ttu_vblank;
0687     uint32_t qos_level_low_wm;
0688     uint32_t qos_level_high_wm;
0689     uint32_t primary_surface_addr_lo;
0690     uint32_t primary_surface_addr_hi;
0691     uint32_t primary_meta_addr_lo;
0692     uint32_t primary_meta_addr_hi;
0693 };
0694 
0695 struct dcn10_hubp {
0696     struct hubp base;
0697     struct dcn_hubp_state state;
0698     const struct dcn_mi_registers *hubp_regs;
0699     const struct dcn_mi_shift *hubp_shift;
0700     const struct dcn_mi_mask *hubp_mask;
0701 };
0702 
0703 void hubp1_program_surface_config(
0704     struct hubp *hubp,
0705     enum surface_pixel_format format,
0706     union dc_tiling_info *tiling_info,
0707     struct plane_size *plane_size,
0708     enum dc_rotation_angle rotation,
0709     struct dc_plane_dcc_param *dcc,
0710     bool horizontal_mirror,
0711     unsigned int compat_level);
0712 
0713 void hubp1_program_deadline(
0714         struct hubp *hubp,
0715         struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
0716         struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
0717 
0718 void hubp1_program_requestor(
0719         struct hubp *hubp,
0720         struct _vcs_dpi_display_rq_regs_st *rq_regs);
0721 
0722 void hubp1_program_pixel_format(
0723     struct hubp *hubp,
0724     enum surface_pixel_format format);
0725 
0726 void hubp1_program_size(
0727     struct hubp *hubp,
0728     enum surface_pixel_format format,
0729     const struct plane_size *plane_size,
0730     struct dc_plane_dcc_param *dcc);
0731 
0732 void hubp1_program_rotation(
0733     struct hubp *hubp,
0734     enum dc_rotation_angle rotation,
0735     bool horizontal_mirror);
0736 
0737 void hubp1_program_tiling(
0738     struct hubp *hubp,
0739     const union dc_tiling_info *info,
0740     const enum surface_pixel_format pixel_format);
0741 
0742 void hubp1_dcc_control(struct hubp *hubp,
0743         bool enable,
0744         enum hubp_ind_block_size independent_64b_blks);
0745 
0746 bool hubp1_program_surface_flip_and_addr(
0747     struct hubp *hubp,
0748     const struct dc_plane_address *address,
0749     bool flip_immediate);
0750 
0751 bool hubp1_is_flip_pending(struct hubp *hubp);
0752 
0753 void hubp1_cursor_set_attributes(
0754         struct hubp *hubp,
0755         const struct dc_cursor_attributes *attr);
0756 
0757 void hubp1_cursor_set_position(
0758         struct hubp *hubp,
0759         const struct dc_cursor_position *pos,
0760         const struct dc_cursor_mi_param *param);
0761 
0762 void hubp1_set_blank(struct hubp *hubp, bool blank);
0763 
0764 void min_set_viewport(struct hubp *hubp,
0765         const struct rect *viewport,
0766         const struct rect *viewport_c);
0767 
0768 void hubp1_clk_cntl(struct hubp *hubp, bool enable);
0769 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
0770 
0771 void dcn10_hubp_construct(
0772     struct dcn10_hubp *hubp1,
0773     struct dc_context *ctx,
0774     uint32_t inst,
0775     const struct dcn_mi_registers *hubp_regs,
0776     const struct dcn_mi_shift *hubp_shift,
0777     const struct dcn_mi_mask *hubp_mask);
0778 
0779 void hubp1_read_state(struct hubp *hubp);
0780 void hubp1_clear_underflow(struct hubp *hubp);
0781 
0782 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
0783 
0784 void hubp1_vready_workaround(struct hubp *hubp,
0785         struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
0786 
0787 void hubp1_init(struct hubp *hubp);
0788 void hubp1_read_state_common(struct hubp *hubp);
0789 bool hubp1_in_blank(struct hubp *hubp);
0790 void hubp1_soft_reset(struct hubp *hubp, bool reset);
0791 
0792 void hubp1_set_flip_int(struct hubp *hubp);
0793 
0794 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!