dc/dcn10/dcn10_dwb.h

0001 /* Copyright 2012-17 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 #ifndef __DC_DWBC_DCN10_H__
0025 #define __DC_DWBC_DCN10_H__
0026
0027 #if defined(CONFIG_DRM_AMD_DC_DCN)
0028
0029 /* DCN */
0030 #define BASE_INNER(seg) \
0031     DCE_BASE__INST0_SEG ## seg
0032
0033 #define BASE(seg) \
0034     BASE_INNER(seg)
0035
0036 #define SR(reg_name)\
0037         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
0038                     mm ## reg_name
0039
0040 #define SRI(reg_name, block, id)\
0041     .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0042                     mm ## block ## id ## _ ## reg_name
0043
0044
0045 #define SRII(reg_name, block, id)\
0046     .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0047                     mm ## block ## id ## _ ## reg_name
0048
0049 #define SF(reg_name, field_name, post_fix)\
0050     .field_name = reg_name ## __ ## field_name ## post_fix
0051
0052
0053 #define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
0054     SRI(WB_ENABLE, CNV, inst),\
0055     SRI(WB_EC_CONFIG, CNV, inst),\
0056     SRI(CNV_MODE, CNV, inst),\
0057     SRI(WB_SOFT_RESET, CNV, inst),\
0058     SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
0059     SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
0060     SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
0061     SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
0062     SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
0063     SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
0064     SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
0065     SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
0066     SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
0067     SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
0068     SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
0069     SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
0070     SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
0071     SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
0072     SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
0073     SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
0074     SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
0075     SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
0076     SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
0077     SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
0078     SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
0079     SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
0080     SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
0081     SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
0082     SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
0083     SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
0084     SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst)
0085
0086 #define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
0087     SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
0088     SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
0089     SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
0090     SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
0091     SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
0092     SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
0093     SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
0094     SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
0095     SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
0096     SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
0097     SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
0098     SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
0099     SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
0100     SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
0101     SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
0102     SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
0103     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
0104     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
0105     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
0106     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
0107     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
0108     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
0109     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
0110     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
0111     SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
0112     SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
0113     SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
0114     SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
0115     SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
0116     SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
0117     SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
0118     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
0119     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
0120     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
0121     SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
0122     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
0123     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
0124     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
0125     SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
0126     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
0127     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
0128     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
0129     SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
0130     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
0131     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
0132     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
0133     SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
0134     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
0135     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
0136     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
0137     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
0138     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
0139     SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
0140     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
0141     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
0142     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
0143     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
0144     SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
0145     SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
0146     SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
0147     SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
0148     SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh)
0149
0150 #define DWBC_REG_FIELD_LIST(type) \
0151     type WB_ENABLE;\
0152     type DISPCLK_R_WB_GATE_DIS;\
0153     type DISPCLK_G_WB_GATE_DIS;\
0154     type DISPCLK_G_WBSCL_GATE_DIS;\
0155     type WB_LB_LS_DIS;\
0156     type WB_LB_SD_DIS;\
0157     type WB_LUT_LS_DIS;\
0158     type CNV_WINDOW_CROP_EN;\
0159     type CNV_STEREO_TYPE;\
0160     type CNV_INTERLACED_MODE;\
0161     type CNV_EYE_SELECTION;\
0162     type CNV_STEREO_POLARITY;\
0163     type CNV_INTERLACED_FIELD_ORDER;\
0164     type CNV_STEREO_SPLIT;\
0165     type CNV_NEW_CONTENT;\
0166     type CNV_FRAME_CAPTURE_EN;\
0167     type WB_SOFT_RESET;\
0168     type MCIF_WB_BUFMGR_ENABLE;\
0169     type MCIF_WB_BUF_DUALSIZE_REQ;\
0170     type MCIF_WB_BUFMGR_SW_INT_EN;\
0171     type MCIF_WB_BUFMGR_SW_INT_ACK;\
0172     type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
0173     type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
0174     type MCIF_WB_BUFMGR_SW_LOCK;\
0175     type MCIF_WB_P_VMID;\
0176     type MCIF_WB_BUF_ADDR_FENCE_EN;\
0177     type MCIF_WB_BUF_LUMA_PITCH;\
0178     type MCIF_WB_BUF_CHROMA_PITCH;\
0179     type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
0180     type MCIF_WB_TIME_PER_PIXEL;\
0181     type WM_CHANGE_ACK_FORCE_ON;\
0182     type MCIF_WB_CLI_WATERMARK_MASK;\
0183     type MCIF_WB_BUF_1_ADDR_Y;\
0184     type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
0185     type MCIF_WB_BUF_1_ADDR_C;\
0186     type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
0187     type MCIF_WB_BUF_2_ADDR_Y;\
0188     type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
0189     type MCIF_WB_BUF_2_ADDR_C;\
0190     type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
0191     type MCIF_WB_BUF_3_ADDR_Y;\
0192     type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
0193     type MCIF_WB_BUF_3_ADDR_C;\
0194     type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
0195     type MCIF_WB_BUF_4_ADDR_Y;\
0196     type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
0197     type MCIF_WB_BUF_4_ADDR_C;\
0198     type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
0199     type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
0200     type MCIF_WB_BUFMGR_VCE_INT_EN;\
0201     type MCIF_WB_BUFMGR_VCE_INT_ACK;\
0202     type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
0203     type MCIF_WB_BUFMGR_VCE_LOCK;\
0204     type MCIF_WB_BUFMGR_SLICE_SIZE;\
0205     type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
0206     type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
0207     type NB_PSTATE_CHANGE_FORCE_ON;\
0208     type NB_PSTATE_ALLOW_FOR_URGENT;\
0209     type NB_PSTATE_CHANGE_WATERMARK_MASK;\
0210     type MCIF_WB_CLI_WATERMARK;\
0211     type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
0212     type MCIF_WB_PITCH_SIZE_WARMUP;\
0213     type MCIF_WB_BUF_LUMA_SIZE;\
0214     type MCIF_WB_BUF_CHROMA_SIZE;\
0215
0216 struct dcn10_dwbc_registers {
0217     uint32_t WB_ENABLE;
0218     uint32_t WB_EC_CONFIG;
0219     uint32_t CNV_MODE;
0220     uint32_t WB_SOFT_RESET;
0221     uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
0222     uint32_t MCIF_WB_BUF_PITCH;
0223     uint32_t MCIF_WB_ARBITRATION_CONTROL;
0224     uint32_t MCIF_WB_SCLK_CHANGE;
0225     uint32_t MCIF_WB_BUF_1_ADDR_Y;
0226     uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
0227     uint32_t MCIF_WB_BUF_1_ADDR_C;
0228     uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
0229     uint32_t MCIF_WB_BUF_2_ADDR_Y;
0230     uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
0231     uint32_t MCIF_WB_BUF_2_ADDR_C;
0232     uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
0233     uint32_t MCIF_WB_BUF_3_ADDR_Y;
0234     uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
0235     uint32_t MCIF_WB_BUF_3_ADDR_C;
0236     uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
0237     uint32_t MCIF_WB_BUF_4_ADDR_Y;
0238     uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
0239     uint32_t MCIF_WB_BUF_4_ADDR_C;
0240     uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
0241     uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
0242     uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
0243     uint32_t MCIF_WB_NB_PSTATE_CONTROL;
0244     uint32_t MCIF_WB_WATERMARK;
0245     uint32_t MCIF_WB_WARM_UP_CNTL;
0246     uint32_t MCIF_WB_BUF_LUMA_SIZE;
0247     uint32_t MCIF_WB_BUF_CHROMA_SIZE;
0248 };
0249 struct dcn10_dwbc_mask {
0250     DWBC_REG_FIELD_LIST(uint32_t)
0251 };
0252 struct dcn10_dwbc_shift {
0253     DWBC_REG_FIELD_LIST(uint8_t)
0254 };
0255 struct dcn10_dwbc {
0256     struct dwbc base;
0257     const struct dcn10_dwbc_registers *dwbc_regs;
0258     const struct dcn10_dwbc_shift *dwbc_shift;
0259     const struct dcn10_dwbc_mask *dwbc_mask;
0260 };
0261
0262 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
0263         struct dc_context *ctx,
0264         const struct dcn10_dwbc_registers *dwbc_regs,
0265         const struct dcn10_dwbc_shift *dwbc_shift,
0266         const struct dcn10_dwbc_mask *dwbc_mask,
0267         int inst);
0268
0269 #endif
0270
0271 #endif