dc/dcn10/dcn10_dwb.c

0001 /*
0002  * Copyright 2012-17 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #if defined(CONFIG_DRM_AMD_DC_DCN)
0027
0028 #include "reg_helper.h"
0029 #include "resource.h"
0030 #include "dwb.h"
0031 #include "dcn10_dwb.h"
0032
0033
0034 #define REG(reg)\
0035     dwbc10->dwbc_regs->reg
0036
0037 #define CTX \
0038     dwbc10->base.ctx
0039
0040 #undef FN
0041 #define FN(reg_name, field_name) \
0042     dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
0043
0044 #define TO_DCN10_DWBC(dwbc_base) \
0045     container_of(dwbc_base, struct dcn10_dwbc, base)
0046
0047 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
0048 {
0049     if (caps) {
0050         caps->adapter_id = 0;   /* we only support 1 adapter currently */
0051         caps->hw_version = DCN_VERSION_1_0;
0052         caps->num_pipes = 2;
0053         memset(&caps->reserved, 0, sizeof(caps->reserved));
0054         memset(&caps->reserved2, 0, sizeof(caps->reserved2));
0055         caps->sw_version = dwb_ver_1_0;
0056         caps->caps.support_dwb = true;
0057         caps->caps.support_ogam = false;
0058         caps->caps.support_wbscl = true;
0059         caps->caps.support_ocsc = false;
0060         return true;
0061     } else {
0062         return false;
0063     }
0064 }
0065
0066 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)
0067 {
0068     struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
0069
0070     /* disable first. */
0071     dwbc->funcs->disable(dwbc);
0072
0073     /* disable power gating */
0074     REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
0075          DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1,
0076          WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1);
0077
0078     REG_UPDATE(WB_ENABLE, WB_ENABLE, 1);
0079
0080     return true;
0081 }
0082
0083 static bool dwb1_disable(struct dwbc *dwbc)
0084 {
0085     struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);
0086
0087     /* disable CNV */
0088     REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0);
0089
0090     /* disable WB */
0091     REG_UPDATE(WB_ENABLE, WB_ENABLE, 0);
0092
0093     /* soft reset */
0094     REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1);
0095     REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0);
0096
0097     /* enable power gating */
0098     REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
0099          DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0,
0100          WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0);
0101
0102     return true;
0103 }
0104
0105 const struct dwbc_funcs dcn10_dwbc_funcs = {
0106     .get_caps           = dwb1_get_caps,
0107     .enable             = dwb1_enable,
0108     .disable            = dwb1_disable,
0109     .update             = NULL,
0110     .set_stereo         = NULL,
0111     .set_new_content        = NULL,
0112     .set_warmup         = NULL,
0113     .dwb_set_scaler         = NULL,
0114 };
0115
0116 void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
0117         struct dc_context *ctx,
0118         const struct dcn10_dwbc_registers *dwbc_regs,
0119         const struct dcn10_dwbc_shift *dwbc_shift,
0120         const struct dcn10_dwbc_mask *dwbc_mask,
0121         int inst)
0122 {
0123     dwbc10->base.ctx = ctx;
0124
0125     dwbc10->base.inst = inst;
0126     dwbc10->base.funcs = &dcn10_dwbc_funcs;
0127
0128     dwbc10->dwbc_regs = dwbc_regs;
0129     dwbc10->dwbc_shift = dwbc_shift;
0130     dwbc10->dwbc_mask = dwbc_mask;
0131 }
0132
0133
0134 #endif