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OSCL-LXR
 
 

     

0001 /* Copyright 2016 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024 
0025 #ifndef __DAL_DPP_DCN10_H__
0026 #define __DAL_DPP_DCN10_H__
0027 
0028 #include "dpp.h"
0029 
0030 #define TO_DCN10_DPP(dpp)\
0031     container_of(dpp, struct dcn10_dpp, base)
0032 
0033 /* TODO: Use correct number of taps. Using polaris values for now */
0034 #define LB_TOTAL_NUMBER_OF_ENTRIES 5124
0035 #define LB_BITS_PER_ENTRY 144
0036 
0037 #define TF_SF(reg_name, field_name, post_fix)\
0038     .field_name = reg_name ## __ ## field_name ## post_fix
0039 
0040 //Used to resolve corner case
0041 #define TF2_SF(reg_name, field_name, post_fix)\
0042     .field_name = reg_name ## _ ## field_name ## post_fix
0043 
0044 #define TF_REG_LIST_DCN(id) \
0045     SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
0046     SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
0047     SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
0048     SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
0049     SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
0050     SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
0051     SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
0052     SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
0053     SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
0054     SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
0055     SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \
0056     SRI(OTG_H_BLANK, DSCL, id), \
0057     SRI(OTG_V_BLANK, DSCL, id), \
0058     SRI(SCL_MODE, DSCL, id), \
0059     SRI(LB_DATA_FORMAT, DSCL, id), \
0060     SRI(LB_MEMORY_CTRL, DSCL, id), \
0061     SRI(DSCL_AUTOCAL, DSCL, id), \
0062     SRI(SCL_BLACK_OFFSET, DSCL, id), \
0063     SRI(SCL_TAP_CONTROL, DSCL, id), \
0064     SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
0065     SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
0066     SRI(DSCL_2TAP_CONTROL, DSCL, id), \
0067     SRI(MPC_SIZE, DSCL, id), \
0068     SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
0069     SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
0070     SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
0071     SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
0072     SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
0073     SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
0074     SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
0075     SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
0076     SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
0077     SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
0078     SRI(RECOUT_START, DSCL, id), \
0079     SRI(RECOUT_SIZE, DSCL, id), \
0080     SRI(CM_ICSC_CONTROL, CM, id), \
0081     SRI(CM_ICSC_C11_C12, CM, id), \
0082     SRI(CM_ICSC_C33_C34, CM, id), \
0083     SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
0084     SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
0085     SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
0086     SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
0087     SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
0088     SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
0089     SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
0090     SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
0091     SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
0092     SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
0093     SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
0094     SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
0095     SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
0096     SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
0097     SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
0098     SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
0099     SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
0100     SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
0101     SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
0102     SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
0103     SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
0104     SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
0105     SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
0106     SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
0107     SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
0108     SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
0109     SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
0110     SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
0111     SRI(CM_MEM_PWR_CTRL, CM, id), \
0112     SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
0113     SRI(CM_DGAM_LUT_INDEX, CM, id), \
0114     SRI(CM_DGAM_LUT_DATA, CM, id), \
0115     SRI(CM_CONTROL, CM, id), \
0116     SRI(CM_DGAM_CONTROL, CM, id), \
0117     SRI(CM_TEST_DEBUG_INDEX, CM, id), \
0118     SRI(CM_TEST_DEBUG_DATA, CM, id), \
0119     SRI(FORMAT_CONTROL, CNVC_CFG, id), \
0120     SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
0121     SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
0122     SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
0123     SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
0124     SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
0125     SRI(DPP_CONTROL, DPP_TOP, id), \
0126     SRI(CM_HDR_MULT_COEF, CM, id)
0127 
0128 
0129 
0130 #define TF_REG_LIST_DCN10(id) \
0131     TF_REG_LIST_DCN(id), \
0132     SRI(CM_COMA_C11_C12, CM, id),\
0133     SRI(CM_COMA_C33_C34, CM, id),\
0134     SRI(CM_COMB_C11_C12, CM, id),\
0135     SRI(CM_COMB_C33_C34, CM, id),\
0136     SRI(CM_OCSC_CONTROL, CM, id), \
0137     SRI(CM_OCSC_C11_C12, CM, id), \
0138     SRI(CM_OCSC_C33_C34, CM, id), \
0139     SRI(CM_BNS_VALUES_R, CM, id), \
0140     SRI(CM_BNS_VALUES_G, CM, id), \
0141     SRI(CM_BNS_VALUES_B, CM, id), \
0142     SRI(CM_MEM_PWR_CTRL, CM, id), \
0143     SRI(CM_RGAM_LUT_DATA, CM, id), \
0144     SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
0145     SRI(CM_RGAM_LUT_INDEX, CM, id), \
0146     SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
0147     SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
0148     SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
0149     SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
0150     SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
0151     SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
0152     SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
0153     SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
0154     SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
0155     SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
0156     SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
0157     SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
0158     SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
0159     SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
0160     SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
0161     SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
0162     SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
0163     SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
0164     SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
0165     SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
0166     SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
0167     SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
0168     SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
0169     SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
0170     SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
0171     SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
0172     SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
0173     SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
0174     SRI(CM_RGAM_CONTROL, CM, id), \
0175     SRI(CM_IGAM_CONTROL, CM, id), \
0176     SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
0177     SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
0178     SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
0179     SRI(CURSOR_CONTROL, CURSOR, id), \
0180     SRI(CM_CMOUT_CONTROL, CM, id)
0181 
0182 
0183 #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
0184     TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
0185     TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
0186     TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
0187     TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
0188     TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
0189     TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
0190     TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
0191     TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
0192     TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
0193     TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
0194     TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
0195     TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
0196     TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
0197     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
0198     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
0199     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
0200     TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
0201     TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
0202     TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
0203     TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
0204     TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
0205     TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
0206     TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
0207     TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
0208     TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
0209     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
0210     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
0211     TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
0212     TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
0213     TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
0214     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
0215     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
0216     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
0217     TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
0218     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
0219     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
0220     TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
0221     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
0222     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
0223     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
0224     TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
0225     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
0226     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
0227     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
0228     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
0229     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
0230     TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
0231     TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
0232     TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
0233     TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
0234     TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
0235     TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
0236     TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
0237     TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
0238     TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
0239     TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
0240     TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
0241     TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
0242     TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
0243     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
0244     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
0245     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
0246     TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
0247     TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
0248     TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
0249     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
0250     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
0251     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
0252     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
0253     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
0254     TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
0255     TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
0256     TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
0257     TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \
0258     TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \
0259     TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
0260     TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
0261     TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
0262     TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
0263     TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
0264     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
0265     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
0266     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
0267     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
0268     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
0269     TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
0270     TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
0271     TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
0272     TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
0273     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
0274     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
0275     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
0276     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
0277     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
0278     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
0279     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
0280     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
0281     TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
0282     TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
0283     TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
0284     TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
0285     TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
0286     TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
0287     TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
0288     TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
0289     TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
0290     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
0291     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
0292     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
0293     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
0294     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
0295     TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
0296     TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
0297     TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
0298     TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
0299     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
0300     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
0301     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
0302     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
0303     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
0304     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
0305     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
0306     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
0307     TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
0308     TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
0309     TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
0310     TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
0311     TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
0312     TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
0313     TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
0314     TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
0315     TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
0316     TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
0317     TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
0318     TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
0319     TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
0320     TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
0321     TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
0322     TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
0323     TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
0324     TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
0325     TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
0326     TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
0327     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
0328     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
0329     TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
0330     TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
0331     TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
0332     TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
0333     TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
0334     TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
0335     TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
0336 
0337 #define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
0338     TF_REG_LIST_SH_MASK_DCN(mask_sh),\
0339     TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
0340     TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
0341     TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
0342     TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
0343     TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
0344     TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
0345     TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
0346     TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
0347     TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
0348     TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
0349     TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
0350     TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
0351     TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
0352     TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
0353     TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
0354     TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
0355     TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
0356     TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
0357     TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
0358     TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
0359     TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
0360     TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
0361     TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
0362     TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
0363     TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
0364     TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
0365     TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
0366     TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
0367     TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
0368     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
0369     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
0370     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
0371     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
0372     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
0373     TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
0374     TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
0375     TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
0376     TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
0377     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
0378     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
0379     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
0380     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
0381     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
0382     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
0383     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
0384     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
0385     TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
0386     TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
0387     TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
0388     TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
0389     TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
0390     TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
0391     TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
0392     TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
0393     TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
0394     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
0395     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
0396     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
0397     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
0398     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
0399     TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
0400     TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
0401     TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
0402     TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
0403     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
0404     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
0405     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
0406     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
0407     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
0408     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
0409     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
0410     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
0411     TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
0412     TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
0413     TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
0414     TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
0415     TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
0416     TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
0417     TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
0418     TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
0419     TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
0420     TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
0421     TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
0422     TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
0423     TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
0424     TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
0425     TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
0426     TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
0427     TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
0428     TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
0429     TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
0430     TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
0431     TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
0432     TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
0433     TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
0434     TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
0435     TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
0436     TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
0437     TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
0438     TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
0439     TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
0440     TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
0441 
0442 /*
0443  *
0444     DCN1 CM debug status register definition
0445 
0446     register :ID9_CM_STATUS do
0447     implement_ref :cm
0448     map to:  :cmdebugind, at: j
0449     width 32
0450     disclosure   NEVER
0451 
0452         field :ID9_VUPDATE_CFG, [0], R
0453         field :ID9_IGAM_LUT_MODE, [2..1], R
0454         field :ID9_BNS_BYPASS, [3], R
0455         field :ID9_ICSC_MODE, [5..4], R
0456         field :ID9_DGAM_LUT_MODE, [8..6], R
0457         field :ID9_HDR_BYPASS, [9], R
0458         field :ID9_GAMUT_REMAP_MODE, [11..10], R
0459         field :ID9_RGAM_LUT_MODE, [14..12], R
0460         #1 free bit
0461         field :ID9_OCSC_MODE, [18..16], R
0462         field :ID9_DENORM_MODE, [21..19], R
0463         field :ID9_ROUND_TRUNC_MODE, [25..22], R
0464         field :ID9_DITHER_EN, [26], R
0465         field :ID9_DITHER_MODE, [28..27], R
0466     end
0467 */
0468 
0469 #define TF_DEBUG_REG_LIST_SH_DCN10 \
0470     .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
0471     .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
0472 
0473 #define TF_DEBUG_REG_LIST_MASK_DCN10 \
0474     .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
0475     .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
0476 
0477 #define TF_REG_FIELD_LIST(type) \
0478     type EXT_OVERSCAN_LEFT; \
0479     type EXT_OVERSCAN_RIGHT; \
0480     type EXT_OVERSCAN_BOTTOM; \
0481     type EXT_OVERSCAN_TOP; \
0482     type OTG_H_BLANK_START; \
0483     type OTG_H_BLANK_END; \
0484     type OTG_V_BLANK_START; \
0485     type OTG_V_BLANK_END; \
0486     type PIXEL_DEPTH; \
0487     type PIXEL_EXPAN_MODE; \
0488     type PIXEL_REDUCE_MODE; \
0489     type DYNAMIC_PIXEL_DEPTH; \
0490     type DITHER_EN; \
0491     type INTERLEAVE_EN; \
0492     type LB_DATA_FORMAT__ALPHA_EN; \
0493     type MEMORY_CONFIG; \
0494     type LB_MAX_PARTITIONS; \
0495     type AUTOCAL_MODE; \
0496     type AUTOCAL_NUM_PIPE; \
0497     type AUTOCAL_PIPE_ID; \
0498     type SCL_BLACK_OFFSET_RGB_Y; \
0499     type SCL_BLACK_OFFSET_CBCR; \
0500     type SCL_V_NUM_TAPS; \
0501     type SCL_H_NUM_TAPS; \
0502     type SCL_V_NUM_TAPS_C; \
0503     type SCL_H_NUM_TAPS_C; \
0504     type SCL_COEF_RAM_TAP_PAIR_IDX; \
0505     type SCL_COEF_RAM_PHASE; \
0506     type SCL_COEF_RAM_FILTER_TYPE; \
0507     type SCL_COEF_RAM_EVEN_TAP_COEF; \
0508     type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
0509     type SCL_COEF_RAM_ODD_TAP_COEF; \
0510     type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
0511     type SCL_H_2TAP_HARDCODE_COEF_EN; \
0512     type SCL_H_2TAP_SHARP_EN; \
0513     type SCL_H_2TAP_SHARP_FACTOR; \
0514     type SCL_V_2TAP_HARDCODE_COEF_EN; \
0515     type SCL_V_2TAP_SHARP_EN; \
0516     type SCL_V_2TAP_SHARP_FACTOR; \
0517     type SCL_COEF_RAM_SELECT; \
0518     type DSCL_MODE; \
0519     type RECOUT_START_X; \
0520     type RECOUT_START_Y; \
0521     type RECOUT_WIDTH; \
0522     type RECOUT_HEIGHT; \
0523     type MPC_WIDTH; \
0524     type MPC_HEIGHT; \
0525     type SCL_H_SCALE_RATIO; \
0526     type SCL_V_SCALE_RATIO; \
0527     type SCL_H_SCALE_RATIO_C; \
0528     type SCL_V_SCALE_RATIO_C; \
0529     type SCL_H_INIT_FRAC; \
0530     type SCL_H_INIT_INT; \
0531     type SCL_H_INIT_FRAC_C; \
0532     type SCL_H_INIT_INT_C; \
0533     type SCL_V_INIT_FRAC; \
0534     type SCL_V_INIT_INT; \
0535     type SCL_V_INIT_FRAC_BOT; \
0536     type SCL_V_INIT_INT_BOT; \
0537     type SCL_V_INIT_FRAC_C; \
0538     type SCL_V_INIT_INT_C; \
0539     type SCL_V_INIT_FRAC_BOT_C; \
0540     type SCL_V_INIT_INT_BOT_C; \
0541     type SCL_CHROMA_COEF_MODE; \
0542     type SCL_COEF_RAM_SELECT_CURRENT; \
0543     type LUT_MEM_PWR_FORCE; \
0544     type LUT_MEM_PWR_STATE; \
0545     type CM_GAMUT_REMAP_MODE; \
0546     type CM_GAMUT_REMAP_C11; \
0547     type CM_GAMUT_REMAP_C12; \
0548     type CM_GAMUT_REMAP_C13; \
0549     type CM_GAMUT_REMAP_C14; \
0550     type CM_GAMUT_REMAP_C21; \
0551     type CM_GAMUT_REMAP_C22; \
0552     type CM_GAMUT_REMAP_C23; \
0553     type CM_GAMUT_REMAP_C24; \
0554     type CM_GAMUT_REMAP_C31; \
0555     type CM_GAMUT_REMAP_C32; \
0556     type CM_GAMUT_REMAP_C33; \
0557     type CM_GAMUT_REMAP_C34; \
0558     type CM_COMA_C11; \
0559     type CM_COMA_C12; \
0560     type CM_COMA_C33; \
0561     type CM_COMA_C34; \
0562     type CM_COMB_C11; \
0563     type CM_COMB_C12; \
0564     type CM_COMB_C33; \
0565     type CM_COMB_C34; \
0566     type CM_OCSC_MODE; \
0567     type CM_OCSC_C11; \
0568     type CM_OCSC_C12; \
0569     type CM_OCSC_C33; \
0570     type CM_OCSC_C34; \
0571     type RGAM_MEM_PWR_FORCE; \
0572     type CM_RGAM_LUT_DATA; \
0573     type CM_RGAM_LUT_WRITE_EN_MASK; \
0574     type CM_RGAM_LUT_WRITE_SEL; \
0575     type CM_RGAM_LUT_INDEX; \
0576     type CM_RGAM_RAMB_EXP_REGION_START_B; \
0577     type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
0578     type CM_RGAM_RAMB_EXP_REGION_START_G; \
0579     type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
0580     type CM_RGAM_RAMB_EXP_REGION_START_R; \
0581     type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
0582     type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
0583     type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
0584     type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
0585     type CM_RGAM_RAMB_EXP_REGION_END_B; \
0586     type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
0587     type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
0588     type CM_RGAM_RAMB_EXP_REGION_END_G; \
0589     type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
0590     type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
0591     type CM_RGAM_RAMB_EXP_REGION_END_R; \
0592     type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
0593     type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
0594     type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
0595     type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
0596     type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
0597     type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
0598     type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
0599     type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
0600     type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
0601     type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
0602     type CM_RGAM_RAMA_EXP_REGION_START_B; \
0603     type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
0604     type CM_RGAM_RAMA_EXP_REGION_START_G; \
0605     type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
0606     type CM_RGAM_RAMA_EXP_REGION_START_R; \
0607     type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
0608     type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
0609     type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
0610     type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
0611     type CM_RGAM_RAMA_EXP_REGION_END_B; \
0612     type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
0613     type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
0614     type CM_RGAM_RAMA_EXP_REGION_END_G; \
0615     type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
0616     type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
0617     type CM_RGAM_RAMA_EXP_REGION_END_R; \
0618     type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
0619     type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
0620     type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
0621     type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
0622     type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
0623     type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
0624     type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
0625     type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
0626     type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
0627     type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
0628     type CM_RGAM_LUT_MODE; \
0629     type CM_CMOUT_ROUND_TRUNC_MODE; \
0630     type CM_BLNDGAM_LUT_MODE; \
0631     type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
0632     type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
0633     type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \
0634     type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
0635     type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \
0636     type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
0637     type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
0638     type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
0639     type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
0640     type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \
0641     type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \
0642     type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \
0643     type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \
0644     type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \
0645     type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \
0646     type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \
0647     type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \
0648     type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \
0649     type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
0650     type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
0651     type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
0652     type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
0653     type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
0654     type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
0655     type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
0656     type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
0657     type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
0658     type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
0659     type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
0660     type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
0661     type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
0662     type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
0663     type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
0664     type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
0665     type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
0666     type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
0667     type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
0668     type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
0669     type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
0670     type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
0671     type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
0672     type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
0673     type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
0674     type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
0675     type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
0676     type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
0677     type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
0678     type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
0679     type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
0680     type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
0681     type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
0682     type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
0683     type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
0684     type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
0685     type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
0686     type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
0687     type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
0688     type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
0689     type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
0690     type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
0691     type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
0692     type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
0693     type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
0694     type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
0695     type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
0696     type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
0697     type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
0698     type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
0699     type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
0700     type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
0701     type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
0702     type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
0703     type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
0704     type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
0705     type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
0706     type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
0707     type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
0708     type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
0709     type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
0710     type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
0711     type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
0712     type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
0713     type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
0714     type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
0715     type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
0716     type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
0717     type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \
0718     type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
0719     type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \
0720     type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
0721     type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \
0722     type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
0723     type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
0724     type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
0725     type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
0726     type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \
0727     type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \
0728     type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \
0729     type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \
0730     type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \
0731     type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \
0732     type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \
0733     type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \
0734     type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \
0735     type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
0736     type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
0737     type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
0738     type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
0739     type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
0740     type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
0741     type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
0742     type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
0743     type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
0744     type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
0745     type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
0746     type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
0747     type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
0748     type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
0749     type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
0750     type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
0751     type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
0752     type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
0753     type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
0754     type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
0755     type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
0756     type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
0757     type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
0758     type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
0759     type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
0760     type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
0761     type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
0762     type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
0763     type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
0764     type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
0765     type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
0766     type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
0767     type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
0768     type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
0769     type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
0770     type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
0771     type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
0772     type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
0773     type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
0774     type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
0775     type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
0776     type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
0777     type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
0778     type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
0779     type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
0780     type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
0781     type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
0782     type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
0783     type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
0784     type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
0785     type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
0786     type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
0787     type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
0788     type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
0789     type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
0790     type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
0791     type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
0792     type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
0793     type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
0794     type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
0795     type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
0796     type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
0797     type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
0798     type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
0799     type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
0800     type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
0801     type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
0802     type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
0803     type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
0804     type CM_BLNDGAM_LUT_WRITE_SEL; \
0805     type CM_BLNDGAM_CONFIG_STATUS; \
0806     type CM_BLNDGAM_LUT_INDEX; \
0807     type BLNDGAM_MEM_PWR_FORCE; \
0808     type CM_3DLUT_MODE; \
0809     type CM_3DLUT_SIZE; \
0810     type CM_3DLUT_INDEX; \
0811     type CM_3DLUT_DATA0; \
0812     type CM_3DLUT_DATA1; \
0813     type CM_3DLUT_DATA_30BIT; \
0814     type CM_3DLUT_WRITE_EN_MASK; \
0815     type CM_3DLUT_RAM_SEL; \
0816     type CM_3DLUT_30BIT_EN; \
0817     type CM_3DLUT_CONFIG_STATUS; \
0818     type CM_3DLUT_READ_SEL; \
0819     type CM_SHAPER_LUT_MODE; \
0820     type CM_SHAPER_RAMB_EXP_REGION_START_B; \
0821     type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \
0822     type CM_SHAPER_RAMB_EXP_REGION_START_G; \
0823     type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \
0824     type CM_SHAPER_RAMB_EXP_REGION_START_R; \
0825     type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \
0826     type CM_SHAPER_RAMB_EXP_REGION_END_B; \
0827     type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \
0828     type CM_SHAPER_RAMB_EXP_REGION_END_G; \
0829     type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \
0830     type CM_SHAPER_RAMB_EXP_REGION_END_R; \
0831     type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \
0832     type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \
0833     type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
0834     type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \
0835     type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \
0836     type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \
0837     type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \
0838     type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \
0839     type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \
0840     type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \
0841     type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \
0842     type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \
0843     type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \
0844     type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \
0845     type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \
0846     type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \
0847     type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \
0848     type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \
0849     type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \
0850     type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \
0851     type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \
0852     type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \
0853     type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \
0854     type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \
0855     type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \
0856     type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \
0857     type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \
0858     type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \
0859     type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \
0860     type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \
0861     type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \
0862     type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \
0863     type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \
0864     type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \
0865     type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \
0866     type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \
0867     type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \
0868     type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \
0869     type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \
0870     type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \
0871     type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \
0872     type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \
0873     type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \
0874     type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \
0875     type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \
0876     type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \
0877     type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \
0878     type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \
0879     type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \
0880     type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \
0881     type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \
0882     type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \
0883     type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \
0884     type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \
0885     type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \
0886     type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \
0887     type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \
0888     type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \
0889     type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \
0890     type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \
0891     type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \
0892     type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \
0893     type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \
0894     type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \
0895     type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \
0896     type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \
0897     type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \
0898     type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \
0899     type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \
0900     type CM_SHAPER_RAMA_EXP_REGION_START_B; \
0901     type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \
0902     type CM_SHAPER_RAMA_EXP_REGION_START_G; \
0903     type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \
0904     type CM_SHAPER_RAMA_EXP_REGION_START_R; \
0905     type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \
0906     type CM_SHAPER_RAMA_EXP_REGION_END_B; \
0907     type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \
0908     type CM_SHAPER_RAMA_EXP_REGION_END_G; \
0909     type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \
0910     type CM_SHAPER_RAMA_EXP_REGION_END_R; \
0911     type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \
0912     type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \
0913     type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
0914     type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \
0915     type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
0916     type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \
0917     type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \
0918     type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \
0919     type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \
0920     type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \
0921     type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \
0922     type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \
0923     type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \
0924     type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \
0925     type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \
0926     type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \
0927     type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \
0928     type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \
0929     type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \
0930     type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \
0931     type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \
0932     type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \
0933     type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \
0934     type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \
0935     type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \
0936     type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \
0937     type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \
0938     type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \
0939     type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \
0940     type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \
0941     type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \
0942     type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \
0943     type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \
0944     type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \
0945     type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \
0946     type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \
0947     type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \
0948     type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \
0949     type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \
0950     type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \
0951     type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \
0952     type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \
0953     type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \
0954     type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \
0955     type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \
0956     type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \
0957     type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \
0958     type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \
0959     type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \
0960     type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \
0961     type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \
0962     type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \
0963     type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \
0964     type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \
0965     type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \
0966     type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \
0967     type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \
0968     type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \
0969     type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \
0970     type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \
0971     type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \
0972     type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \
0973     type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \
0974     type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \
0975     type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \
0976     type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \
0977     type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \
0978     type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
0979     type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
0980     type CM_SHAPER_LUT_WRITE_EN_MASK; \
0981     type CM_SHAPER_CONFIG_STATUS; \
0982     type CM_SHAPER_LUT_WRITE_SEL; \
0983     type CM_SHAPER_LUT_INDEX; \
0984     type CM_SHAPER_LUT_DATA; \
0985     type CM_DGAM_CONFIG_STATUS; \
0986     type CM_ICSC_MODE; \
0987     type CM_ICSC_C11; \
0988     type CM_ICSC_C12; \
0989     type CM_ICSC_C33; \
0990     type CM_ICSC_C34; \
0991     type CM_BNS_BIAS_R; \
0992     type CM_BNS_BIAS_G; \
0993     type CM_BNS_BIAS_B; \
0994     type CM_BNS_SCALE_R; \
0995     type CM_BNS_SCALE_G; \
0996     type CM_BNS_SCALE_B; \
0997     type CM_DGAM_RAMB_EXP_REGION_START_B; \
0998     type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
0999     type CM_DGAM_RAMB_EXP_REGION_START_G; \
1000     type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
1001     type CM_DGAM_RAMB_EXP_REGION_START_R; \
1002     type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
1003     type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
1004     type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
1005     type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
1006     type CM_DGAM_RAMB_EXP_REGION_END_B; \
1007     type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
1008     type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
1009     type CM_DGAM_RAMB_EXP_REGION_END_G; \
1010     type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
1011     type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
1012     type CM_DGAM_RAMB_EXP_REGION_END_R; \
1013     type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
1014     type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
1015     type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
1016     type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
1017     type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
1018     type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
1019     type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
1020     type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
1021     type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
1022     type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
1023     type CM_DGAM_RAMA_EXP_REGION_START_B; \
1024     type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
1025     type CM_DGAM_RAMA_EXP_REGION_START_G; \
1026     type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
1027     type CM_DGAM_RAMA_EXP_REGION_START_R; \
1028     type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
1029     type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
1030     type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
1031     type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
1032     type CM_DGAM_RAMA_EXP_REGION_END_B; \
1033     type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
1034     type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
1035     type CM_DGAM_RAMA_EXP_REGION_END_G; \
1036     type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
1037     type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
1038     type CM_DGAM_RAMA_EXP_REGION_END_R; \
1039     type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
1040     type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
1041     type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
1042     type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
1043     type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
1044     type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
1045     type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
1046     type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
1047     type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
1048     type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
1049     type SHARED_MEM_PWR_DIS; \
1050     type CM_IGAM_LUT_FORMAT_R; \
1051     type CM_IGAM_LUT_FORMAT_G; \
1052     type CM_IGAM_LUT_FORMAT_B; \
1053     type CM_IGAM_LUT_HOST_EN; \
1054     type CM_IGAM_LUT_RW_MODE; \
1055     type CM_IGAM_LUT_WRITE_EN_MASK; \
1056     type CM_IGAM_LUT_SEL; \
1057     type CM_IGAM_LUT_SEQ_COLOR; \
1058     type CM_IGAM_DGAM_CONFIG_STATUS; \
1059     type CM_DGAM_LUT_WRITE_EN_MASK; \
1060     type CM_DGAM_LUT_WRITE_SEL; \
1061     type CM_DGAM_LUT_INDEX; \
1062     type CM_DGAM_LUT_DATA; \
1063     type CM_DGAM_LUT_MODE; \
1064     type CM_IGAM_LUT_MODE; \
1065     type CM_IGAM_INPUT_FORMAT; \
1066     type CM_IGAM_LUT_RW_INDEX; \
1067     type CM_BYPASS_EN; \
1068     type FORMAT_EXPANSION_MODE; \
1069     type CNVC_BYPASS; \
1070     type OUTPUT_FP; \
1071     type CNVC_SURFACE_PIXEL_FORMAT; \
1072     type CURSOR_MODE; \
1073     type CURSOR_PITCH; \
1074     type CURSOR_LINES_PER_CHUNK; \
1075     type CURSOR_ENABLE; \
1076     type CUR0_MODE; \
1077     type CUR0_EXPANSION_MODE; \
1078     type CUR0_ENABLE; \
1079     type CM_BYPASS; \
1080     type CM_TEST_DEBUG_INDEX; \
1081     type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
1082     type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
1083     type FORMAT_CONTROL__ALPHA_EN; \
1084     type CUR0_COLOR0; \
1085     type CUR0_COLOR1; \
1086     type DPPCLK_RATE_CONTROL; \
1087     type DPP_CLOCK_ENABLE; \
1088     type CM_HDR_MULT_COEF; \
1089     type CUR0_FP_BIAS; \
1090     type CUR0_FP_SCALE;
1091 
1092 struct dcn_dpp_shift {
1093     TF_REG_FIELD_LIST(uint8_t)
1094 };
1095 
1096 struct dcn_dpp_mask {
1097     TF_REG_FIELD_LIST(uint32_t)
1098 };
1099 
1100 #define DPP_COMMON_REG_VARIABLE_LIST \
1101     uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
1102     uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
1103     uint32_t OTG_H_BLANK; \
1104     uint32_t OTG_V_BLANK; \
1105     uint32_t DSCL_MEM_PWR_CTRL; \
1106     uint32_t DSCL_MEM_PWR_STATUS; \
1107     uint32_t SCL_MODE; \
1108     uint32_t LB_DATA_FORMAT; \
1109     uint32_t LB_MEMORY_CTRL; \
1110     uint32_t DSCL_AUTOCAL; \
1111     uint32_t SCL_BLACK_OFFSET; \
1112     uint32_t SCL_TAP_CONTROL; \
1113     uint32_t SCL_COEF_RAM_TAP_SELECT; \
1114     uint32_t SCL_COEF_RAM_TAP_DATA; \
1115     uint32_t DSCL_2TAP_CONTROL; \
1116     uint32_t MPC_SIZE; \
1117     uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
1118     uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
1119     uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
1120     uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
1121     uint32_t SCL_HORZ_FILTER_INIT; \
1122     uint32_t SCL_HORZ_FILTER_INIT_C; \
1123     uint32_t SCL_VERT_FILTER_INIT; \
1124     uint32_t SCL_VERT_FILTER_INIT_BOT; \
1125     uint32_t SCL_VERT_FILTER_INIT_C; \
1126     uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
1127     uint32_t RECOUT_START; \
1128     uint32_t RECOUT_SIZE; \
1129     uint32_t CM_GAMUT_REMAP_CONTROL; \
1130     uint32_t CM_GAMUT_REMAP_C11_C12; \
1131     uint32_t CM_GAMUT_REMAP_C13_C14; \
1132     uint32_t CM_GAMUT_REMAP_C21_C22; \
1133     uint32_t CM_GAMUT_REMAP_C23_C24; \
1134     uint32_t CM_GAMUT_REMAP_C31_C32; \
1135     uint32_t CM_GAMUT_REMAP_C33_C34; \
1136     uint32_t CM_COMA_C11_C12; \
1137     uint32_t CM_COMA_C33_C34; \
1138     uint32_t CM_COMB_C11_C12; \
1139     uint32_t CM_COMB_C33_C34; \
1140     uint32_t CM_OCSC_CONTROL; \
1141     uint32_t CM_OCSC_C11_C12; \
1142     uint32_t CM_OCSC_C33_C34; \
1143     uint32_t CM_MEM_PWR_CTRL; \
1144     uint32_t CM_RGAM_LUT_DATA; \
1145     uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
1146     uint32_t CM_RGAM_LUT_INDEX; \
1147     uint32_t CM_RGAM_RAMB_START_CNTL_B; \
1148     uint32_t CM_RGAM_RAMB_START_CNTL_G; \
1149     uint32_t CM_RGAM_RAMB_START_CNTL_R; \
1150     uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
1151     uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
1152     uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
1153     uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
1154     uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
1155     uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
1156     uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
1157     uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
1158     uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
1159     uint32_t CM_RGAM_RAMB_REGION_0_1; \
1160     uint32_t CM_RGAM_RAMB_REGION_32_33; \
1161     uint32_t CM_RGAM_RAMA_START_CNTL_B; \
1162     uint32_t CM_RGAM_RAMA_START_CNTL_G; \
1163     uint32_t CM_RGAM_RAMA_START_CNTL_R; \
1164     uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
1165     uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
1166     uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
1167     uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
1168     uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
1169     uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
1170     uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
1171     uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
1172     uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
1173     uint32_t CM_RGAM_RAMA_REGION_0_1; \
1174     uint32_t CM_RGAM_RAMA_REGION_32_33; \
1175     uint32_t CM_RGAM_CONTROL; \
1176     uint32_t CM_CMOUT_CONTROL; \
1177     uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
1178     uint32_t CM_BLNDGAM_CONTROL; \
1179     uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
1180     uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \
1181     uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \
1182     uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \
1183     uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \
1184     uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \
1185     uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \
1186     uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \
1187     uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \
1188     uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \
1189     uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \
1190     uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \
1191     uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \
1192     uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \
1193     uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \
1194     uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \
1195     uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \
1196     uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \
1197     uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \
1198     uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \
1199     uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \
1200     uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \
1201     uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \
1202     uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \
1203     uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \
1204     uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \
1205     uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \
1206     uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \
1207     uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \
1208     uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \
1209     uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \
1210     uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \
1211     uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \
1212     uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \
1213     uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \
1214     uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \
1215     uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \
1216     uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \
1217     uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \
1218     uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \
1219     uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \
1220     uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \
1221     uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \
1222     uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \
1223     uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \
1224     uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \
1225     uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \
1226     uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \
1227     uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \
1228     uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \
1229     uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \
1230     uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \
1231     uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \
1232     uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \
1233     uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \
1234     uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \
1235     uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
1236     uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
1237     uint32_t CM_BLNDGAM_LUT_INDEX; \
1238     uint32_t CM_3DLUT_MODE; \
1239     uint32_t CM_3DLUT_INDEX; \
1240     uint32_t CM_3DLUT_DATA; \
1241     uint32_t CM_3DLUT_DATA_30BIT; \
1242     uint32_t CM_3DLUT_READ_WRITE_CONTROL; \
1243     uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
1244     uint32_t CM_SHAPER_CONTROL; \
1245     uint32_t CM_SHAPER_RAMB_START_CNTL_B; \
1246     uint32_t CM_SHAPER_RAMB_START_CNTL_G; \
1247     uint32_t CM_SHAPER_RAMB_START_CNTL_R; \
1248     uint32_t CM_SHAPER_RAMB_END_CNTL_B; \
1249     uint32_t CM_SHAPER_RAMB_END_CNTL_G; \
1250     uint32_t CM_SHAPER_RAMB_END_CNTL_R; \
1251     uint32_t CM_SHAPER_RAMB_REGION_0_1; \
1252     uint32_t CM_SHAPER_RAMB_REGION_2_3; \
1253     uint32_t CM_SHAPER_RAMB_REGION_4_5; \
1254     uint32_t CM_SHAPER_RAMB_REGION_6_7; \
1255     uint32_t CM_SHAPER_RAMB_REGION_8_9; \
1256     uint32_t CM_SHAPER_RAMB_REGION_10_11; \
1257     uint32_t CM_SHAPER_RAMB_REGION_12_13; \
1258     uint32_t CM_SHAPER_RAMB_REGION_14_15; \
1259     uint32_t CM_SHAPER_RAMB_REGION_16_17; \
1260     uint32_t CM_SHAPER_RAMB_REGION_18_19; \
1261     uint32_t CM_SHAPER_RAMB_REGION_20_21; \
1262     uint32_t CM_SHAPER_RAMB_REGION_22_23; \
1263     uint32_t CM_SHAPER_RAMB_REGION_24_25; \
1264     uint32_t CM_SHAPER_RAMB_REGION_26_27; \
1265     uint32_t CM_SHAPER_RAMB_REGION_28_29; \
1266     uint32_t CM_SHAPER_RAMB_REGION_30_31; \
1267     uint32_t CM_SHAPER_RAMB_REGION_32_33; \
1268     uint32_t CM_SHAPER_RAMA_START_CNTL_B; \
1269     uint32_t CM_SHAPER_RAMA_START_CNTL_G; \
1270     uint32_t CM_SHAPER_RAMA_START_CNTL_R; \
1271     uint32_t CM_SHAPER_RAMA_END_CNTL_B; \
1272     uint32_t CM_SHAPER_RAMA_END_CNTL_G; \
1273     uint32_t CM_SHAPER_RAMA_END_CNTL_R; \
1274     uint32_t CM_SHAPER_RAMA_REGION_0_1; \
1275     uint32_t CM_SHAPER_RAMA_REGION_2_3; \
1276     uint32_t CM_SHAPER_RAMA_REGION_4_5; \
1277     uint32_t CM_SHAPER_RAMA_REGION_6_7; \
1278     uint32_t CM_SHAPER_RAMA_REGION_8_9; \
1279     uint32_t CM_SHAPER_RAMA_REGION_10_11; \
1280     uint32_t CM_SHAPER_RAMA_REGION_12_13; \
1281     uint32_t CM_SHAPER_RAMA_REGION_14_15; \
1282     uint32_t CM_SHAPER_RAMA_REGION_16_17; \
1283     uint32_t CM_SHAPER_RAMA_REGION_18_19; \
1284     uint32_t CM_SHAPER_RAMA_REGION_20_21; \
1285     uint32_t CM_SHAPER_RAMA_REGION_22_23; \
1286     uint32_t CM_SHAPER_RAMA_REGION_24_25; \
1287     uint32_t CM_SHAPER_RAMA_REGION_26_27; \
1288     uint32_t CM_SHAPER_RAMA_REGION_28_29; \
1289     uint32_t CM_SHAPER_RAMA_REGION_30_31; \
1290     uint32_t CM_SHAPER_RAMA_REGION_32_33; \
1291     uint32_t CM_SHAPER_LUT_INDEX; \
1292     uint32_t CM_SHAPER_LUT_DATA; \
1293     uint32_t CM_ICSC_CONTROL; \
1294     uint32_t CM_ICSC_C11_C12; \
1295     uint32_t CM_ICSC_C33_C34; \
1296     uint32_t CM_BNS_VALUES_R; \
1297     uint32_t CM_BNS_VALUES_G; \
1298     uint32_t CM_BNS_VALUES_B; \
1299     uint32_t CM_DGAM_RAMB_START_CNTL_B; \
1300     uint32_t CM_DGAM_RAMB_START_CNTL_G; \
1301     uint32_t CM_DGAM_RAMB_START_CNTL_R; \
1302     uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \
1303     uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \
1304     uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \
1305     uint32_t CM_DGAM_RAMB_END_CNTL1_B; \
1306     uint32_t CM_DGAM_RAMB_END_CNTL2_B; \
1307     uint32_t CM_DGAM_RAMB_END_CNTL1_G; \
1308     uint32_t CM_DGAM_RAMB_END_CNTL2_G; \
1309     uint32_t CM_DGAM_RAMB_END_CNTL1_R; \
1310     uint32_t CM_DGAM_RAMB_END_CNTL2_R; \
1311     uint32_t CM_DGAM_RAMB_REGION_0_1; \
1312     uint32_t CM_DGAM_RAMB_REGION_14_15; \
1313     uint32_t CM_DGAM_RAMA_START_CNTL_B; \
1314     uint32_t CM_DGAM_RAMA_START_CNTL_G; \
1315     uint32_t CM_DGAM_RAMA_START_CNTL_R; \
1316     uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \
1317     uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \
1318     uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \
1319     uint32_t CM_DGAM_RAMA_END_CNTL1_B; \
1320     uint32_t CM_DGAM_RAMA_END_CNTL2_B; \
1321     uint32_t CM_DGAM_RAMA_END_CNTL1_G; \
1322     uint32_t CM_DGAM_RAMA_END_CNTL2_G; \
1323     uint32_t CM_DGAM_RAMA_END_CNTL1_R; \
1324     uint32_t CM_DGAM_RAMA_END_CNTL2_R; \
1325     uint32_t CM_DGAM_RAMA_REGION_0_1; \
1326     uint32_t CM_DGAM_RAMA_REGION_14_15; \
1327     uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
1328     uint32_t CM_DGAM_LUT_INDEX; \
1329     uint32_t CM_DGAM_LUT_DATA; \
1330     uint32_t CM_CONTROL; \
1331     uint32_t CM_DGAM_CONTROL; \
1332     uint32_t CM_IGAM_CONTROL; \
1333     uint32_t CM_IGAM_LUT_RW_CONTROL; \
1334     uint32_t CM_IGAM_LUT_RW_INDEX; \
1335     uint32_t CM_IGAM_LUT_SEQ_COLOR; \
1336     uint32_t CM_TEST_DEBUG_INDEX; \
1337     uint32_t CM_TEST_DEBUG_DATA; \
1338     uint32_t FORMAT_CONTROL; \
1339     uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
1340     uint32_t CURSOR_CONTROL; \
1341     uint32_t CURSOR0_CONTROL; \
1342     uint32_t CURSOR0_COLOR0; \
1343     uint32_t CURSOR0_COLOR1; \
1344     uint32_t DPP_CONTROL; \
1345     uint32_t CM_HDR_MULT_COEF; \
1346     uint32_t CURSOR0_FP_SCALE_BIAS;
1347 
1348 struct dcn_dpp_registers {
1349     DPP_COMMON_REG_VARIABLE_LIST
1350 };
1351 
1352 struct dcn10_dpp {
1353     struct dpp base;
1354 
1355     const struct dcn_dpp_registers *tf_regs;
1356     const struct dcn_dpp_shift *tf_shift;
1357     const struct dcn_dpp_mask *tf_mask;
1358 
1359     const uint16_t *filter_v;
1360     const uint16_t *filter_h;
1361     const uint16_t *filter_v_c;
1362     const uint16_t *filter_h_c;
1363     int lb_pixel_depth_supported;
1364     int lb_memory_size;
1365     int lb_bits_per_entry;
1366     bool is_write_to_ram_a_safe;
1367     struct scaler_data scl_data;
1368     struct pwl_params pwl_data;
1369 };
1370 
1371 enum dcn10_input_csc_select {
1372     INPUT_CSC_SELECT_BYPASS = 0,
1373     INPUT_CSC_SELECT_ICSC = 1,
1374     INPUT_CSC_SELECT_COMA = 2
1375 };
1376 
1377 void dpp1_set_cursor_attributes(
1378         struct dpp *dpp_base,
1379         struct dc_cursor_attributes *cursor_attributes);
1380 
1381 void dpp1_set_cursor_position(
1382         struct dpp *dpp_base,
1383         const struct dc_cursor_position *pos,
1384         const struct dc_cursor_mi_param *param,
1385         uint32_t width,
1386         uint32_t height);
1387 
1388 void dpp1_cnv_set_optional_cursor_attributes(
1389             struct dpp *dpp_base,
1390             struct dpp_cursor_attributes *attr);
1391 
1392 bool dpp1_dscl_is_lb_conf_valid(
1393         int ceil_vratio,
1394         int num_partitions,
1395         int vtaps);
1396 
1397 void dpp1_dscl_calc_lb_num_partitions(
1398         const struct scaler_data *scl_data,
1399         enum lb_memory_config lb_config,
1400         int *num_part_y,
1401         int *num_part_c);
1402 
1403 void dpp1_degamma_ram_select(
1404         struct dpp *dpp_base,
1405                             bool use_ram_a);
1406 
1407 void dpp1_program_degamma_luta_settings(
1408         struct dpp *dpp_base,
1409         const struct pwl_params *params);
1410 
1411 void dpp1_program_degamma_lutb_settings(
1412         struct dpp *dpp_base,
1413         const struct pwl_params *params);
1414 
1415 void dpp1_program_degamma_lut(
1416         struct dpp *dpp_base,
1417         const struct pwl_result_data *rgb,
1418         uint32_t num,
1419         bool is_ram_a);
1420 
1421 void dpp1_power_on_degamma_lut(
1422         struct dpp *dpp_base,
1423     bool power_on);
1424 
1425 void dpp1_program_input_csc(
1426         struct dpp *dpp_base,
1427         enum dc_color_space color_space,
1428         enum dcn10_input_csc_select select,
1429         const struct out_csc_color_matrix *tbl_entry);
1430 
1431 void dpp1_program_bias_and_scale(
1432         struct dpp *dpp_base,
1433         struct dc_bias_and_scale *params);
1434 
1435 void dpp1_program_input_lut(
1436         struct dpp *dpp_base,
1437         const struct dc_gamma *gamma);
1438 
1439 void dpp1_full_bypass(struct dpp *dpp_base);
1440 
1441 void dpp1_set_degamma(
1442         struct dpp *dpp_base,
1443         enum ipp_degamma_mode mode);
1444 
1445 void dpp1_set_degamma_pwl(struct dpp *dpp_base,
1446         const struct pwl_params *params);
1447 
1448 
1449 void dpp_read_state(struct dpp *dpp_base,
1450         struct dcn_dpp_state *s);
1451 
1452 void dpp_reset(struct dpp *dpp_base);
1453 
1454 void dpp1_cm_program_regamma_lut(
1455         struct dpp *dpp_base,
1456         const struct pwl_result_data *rgb,
1457         uint32_t num);
1458 
1459 void dpp1_cm_power_on_regamma_lut(
1460     struct dpp *dpp_base,
1461     bool power_on);
1462 
1463 void dpp1_cm_configure_regamma_lut(
1464         struct dpp *dpp_base,
1465         bool is_ram_a);
1466 
1467 /*program re gamma RAM A*/
1468 void dpp1_cm_program_regamma_luta_settings(
1469         struct dpp *dpp_base,
1470         const struct pwl_params *params);
1471 
1472 /*program re gamma RAM B*/
1473 void dpp1_cm_program_regamma_lutb_settings(
1474         struct dpp *dpp_base,
1475         const struct pwl_params *params);
1476 void dpp1_cm_set_output_csc_adjustment(
1477         struct dpp *dpp_base,
1478         const uint16_t *regval);
1479 
1480 void dpp1_cm_set_output_csc_default(
1481         struct dpp *dpp_base,
1482         enum dc_color_space colorspace);
1483 
1484 void dpp1_cm_set_gamut_remap(
1485     struct dpp *dpp,
1486     const struct dpp_grph_csc_adjustment *adjust);
1487 
1488 void dpp1_dscl_set_scaler_manual_scale(
1489     struct dpp *dpp_base,
1490     const struct scaler_data *scl_data);
1491 
1492 void dpp1_cnv_setup (
1493         struct dpp *dpp_base,
1494         enum surface_pixel_format format,
1495         enum expansion_mode mode,
1496         struct dc_csc_transform input_csc_color_matrix,
1497         enum dc_color_space input_color_space,
1498         struct cnv_alpha_2bit_lut *alpha_2bit_lut);
1499 
1500 void dpp1_dppclk_control(
1501         struct dpp *dpp_base,
1502         bool dppclk_div,
1503         bool enable);
1504 
1505 void dpp1_set_hdr_multiplier(
1506         struct dpp *dpp_base,
1507         uint32_t multiplier);
1508 
1509 bool dpp1_get_optimal_number_of_taps(
1510         struct dpp *dpp,
1511         struct scaler_data *scl_data,
1512         const struct scaling_taps *in_taps);
1513 
1514 void dpp1_construct(struct dcn10_dpp *dpp1,
1515     struct dc_context *ctx,
1516     uint32_t inst,
1517     const struct dcn_dpp_registers *tf_regs,
1518     const struct dcn_dpp_shift *tf_shift,
1519     const struct dcn_dpp_mask *tf_mask);
1520 #endif
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