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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 
0028 #include "core_types.h"
0029 
0030 #include "reg_helper.h"
0031 #include "dcn10_dpp.h"
0032 #include "basics/conversion.h"
0033 
0034 #define NUM_PHASES    64
0035 #define HORZ_MAX_TAPS 8
0036 #define VERT_MAX_TAPS 8
0037 
0038 #define BLACK_OFFSET_RGB_Y 0x0
0039 #define BLACK_OFFSET_CBCR  0x8000
0040 
0041 #define REG(reg)\
0042     dpp->tf_regs->reg
0043 
0044 #define CTX \
0045     dpp->base.ctx
0046 
0047 #undef FN
0048 #define FN(reg_name, field_name) \
0049     dpp->tf_shift->field_name, dpp->tf_mask->field_name
0050 
0051 enum pixel_format_description {
0052     PIXEL_FORMAT_FIXED = 0,
0053     PIXEL_FORMAT_FIXED16,
0054     PIXEL_FORMAT_FLOAT
0055 
0056 };
0057 
0058 enum dcn10_coef_filter_type_sel {
0059     SCL_COEF_LUMA_VERT_FILTER = 0,
0060     SCL_COEF_LUMA_HORZ_FILTER = 1,
0061     SCL_COEF_CHROMA_VERT_FILTER = 2,
0062     SCL_COEF_CHROMA_HORZ_FILTER = 3,
0063     SCL_COEF_ALPHA_VERT_FILTER = 4,
0064     SCL_COEF_ALPHA_HORZ_FILTER = 5
0065 };
0066 
0067 enum dscl_autocal_mode {
0068     AUTOCAL_MODE_OFF = 0,
0069 
0070     /* Autocal calculate the scaling ratio and initial phase and the
0071      * DSCL_MODE_SEL must be set to 1
0072      */
0073     AUTOCAL_MODE_AUTOSCALE = 1,
0074     /* Autocal perform auto centering without replication and the
0075      * DSCL_MODE_SEL must be set to 0
0076      */
0077     AUTOCAL_MODE_AUTOCENTER = 2,
0078     /* Autocal perform auto centering and auto replication and the
0079      * DSCL_MODE_SEL must be set to 0
0080      */
0081     AUTOCAL_MODE_AUTOREPLICATE = 3
0082 };
0083 
0084 enum dscl_mode_sel {
0085     DSCL_MODE_SCALING_444_BYPASS = 0,
0086     DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
0087     DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
0088     DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
0089     DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
0090     DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
0091     DSCL_MODE_DSCL_BYPASS = 6
0092 };
0093 
0094 void dpp_read_state(struct dpp *dpp_base,
0095         struct dcn_dpp_state *s)
0096 {
0097     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0098 
0099     REG_GET(DPP_CONTROL,
0100             DPP_CLOCK_ENABLE, &s->is_enabled);
0101     REG_GET(CM_IGAM_CONTROL,
0102             CM_IGAM_LUT_MODE, &s->igam_lut_mode);
0103     REG_GET(CM_IGAM_CONTROL,
0104             CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
0105     REG_GET(CM_DGAM_CONTROL,
0106             CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
0107     REG_GET(CM_RGAM_CONTROL,
0108             CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
0109     REG_GET(CM_GAMUT_REMAP_CONTROL,
0110             CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
0111 
0112     if (s->gamut_remap_mode) {
0113         s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
0114         s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
0115         s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
0116         s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
0117         s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
0118         s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
0119     }
0120 }
0121 
0122 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
0123 
0124 bool dpp1_get_optimal_number_of_taps(
0125         struct dpp *dpp,
0126         struct scaler_data *scl_data,
0127         const struct scaling_taps *in_taps)
0128 {
0129     /* Some ASICs does not support  FP16 scaling, so we reject modes require this*/
0130     if (scl_data->format == PIXEL_FORMAT_FP16 &&
0131         dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
0132         scl_data->ratios.horz.value != dc_fixpt_one.value &&
0133         scl_data->ratios.vert.value != dc_fixpt_one.value)
0134         return false;
0135 
0136     if (scl_data->viewport.width > scl_data->h_active &&
0137         dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
0138         scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
0139         return false;
0140 
0141     /* TODO: add lb check */
0142 
0143     /* No support for programming ratio of 4, drop to 3.99999.. */
0144     if (scl_data->ratios.horz.value == (4ll << 32))
0145         scl_data->ratios.horz.value--;
0146     if (scl_data->ratios.vert.value == (4ll << 32))
0147         scl_data->ratios.vert.value--;
0148     if (scl_data->ratios.horz_c.value == (4ll << 32))
0149         scl_data->ratios.horz_c.value--;
0150     if (scl_data->ratios.vert_c.value == (4ll << 32))
0151         scl_data->ratios.vert_c.value--;
0152 
0153     /* Set default taps if none are provided */
0154     if (in_taps->h_taps == 0)
0155         scl_data->taps.h_taps = 4;
0156     else
0157         scl_data->taps.h_taps = in_taps->h_taps;
0158     if (in_taps->v_taps == 0)
0159         scl_data->taps.v_taps = 4;
0160     else
0161         scl_data->taps.v_taps = in_taps->v_taps;
0162     if (in_taps->v_taps_c == 0)
0163         scl_data->taps.v_taps_c = 2;
0164     else
0165         scl_data->taps.v_taps_c = in_taps->v_taps_c;
0166     if (in_taps->h_taps_c == 0)
0167         scl_data->taps.h_taps_c = 2;
0168     /* Only 1 and even h_taps_c are supported by hw */
0169     else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
0170         scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
0171     else
0172         scl_data->taps.h_taps_c = in_taps->h_taps_c;
0173 
0174     if (!dpp->ctx->dc->debug.always_scale) {
0175         if (IDENTITY_RATIO(scl_data->ratios.horz))
0176             scl_data->taps.h_taps = 1;
0177         if (IDENTITY_RATIO(scl_data->ratios.vert))
0178             scl_data->taps.v_taps = 1;
0179         if (IDENTITY_RATIO(scl_data->ratios.horz_c))
0180             scl_data->taps.h_taps_c = 1;
0181         if (IDENTITY_RATIO(scl_data->ratios.vert_c))
0182             scl_data->taps.v_taps_c = 1;
0183     }
0184 
0185     return true;
0186 }
0187 
0188 void dpp_reset(struct dpp *dpp_base)
0189 {
0190     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0191 
0192     dpp->filter_h_c = NULL;
0193     dpp->filter_v_c = NULL;
0194     dpp->filter_h = NULL;
0195     dpp->filter_v = NULL;
0196 
0197     memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
0198     memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
0199 }
0200 
0201 
0202 
0203 static void dpp1_cm_set_regamma_pwl(
0204     struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
0205 {
0206     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0207     uint32_t re_mode = 0;
0208 
0209     switch (mode) {
0210     case OPP_REGAMMA_BYPASS:
0211         re_mode = 0;
0212         break;
0213     case OPP_REGAMMA_SRGB:
0214         re_mode = 1;
0215         break;
0216     case OPP_REGAMMA_XVYCC:
0217         re_mode = 2;
0218         break;
0219     case OPP_REGAMMA_USER:
0220         re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
0221         if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
0222             break;
0223 
0224         dpp1_cm_power_on_regamma_lut(dpp_base, true);
0225         dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
0226 
0227         if (dpp->is_write_to_ram_a_safe)
0228             dpp1_cm_program_regamma_luta_settings(dpp_base, params);
0229         else
0230             dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
0231 
0232         dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
0233                         params->hw_points_num);
0234         dpp->pwl_data = *params;
0235 
0236         re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
0237         dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
0238         break;
0239     default:
0240         break;
0241     }
0242     REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
0243 }
0244 
0245 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
0246                         enum pixel_format_description *fmt)
0247 {
0248 
0249     if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
0250         input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
0251         *fmt = PIXEL_FORMAT_FLOAT;
0252     else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ||
0253         input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616)
0254         *fmt = PIXEL_FORMAT_FIXED16;
0255     else
0256         *fmt = PIXEL_FORMAT_FIXED;
0257 }
0258 
0259 static void dpp1_set_degamma_format_float(
0260         struct dpp *dpp_base,
0261         bool is_float)
0262 {
0263     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0264 
0265     if (is_float) {
0266         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
0267         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
0268     } else {
0269         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
0270         REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
0271     }
0272 }
0273 
0274 void dpp1_cnv_setup (
0275         struct dpp *dpp_base,
0276         enum surface_pixel_format format,
0277         enum expansion_mode mode,
0278         struct dc_csc_transform input_csc_color_matrix,
0279         enum dc_color_space input_color_space,
0280         struct cnv_alpha_2bit_lut *alpha_2bit_lut)
0281 {
0282     uint32_t pixel_format;
0283     uint32_t alpha_en;
0284     enum pixel_format_description fmt ;
0285     enum dc_color_space color_space;
0286     enum dcn10_input_csc_select select;
0287     bool is_float;
0288     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0289     bool force_disable_cursor = false;
0290     struct out_csc_color_matrix tbl_entry;
0291     int i = 0;
0292 
0293     dpp1_setup_format_flags(format, &fmt);
0294     alpha_en = 1;
0295     pixel_format = 0;
0296     color_space = COLOR_SPACE_SRGB;
0297     select = INPUT_CSC_SELECT_BYPASS;
0298     is_float = false;
0299 
0300     switch (fmt) {
0301     case PIXEL_FORMAT_FIXED:
0302     case PIXEL_FORMAT_FIXED16:
0303     /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/
0304         REG_SET_3(FORMAT_CONTROL, 0,
0305             CNVC_BYPASS, 0,
0306             FORMAT_EXPANSION_MODE, mode,
0307             OUTPUT_FP, 0);
0308         break;
0309     case PIXEL_FORMAT_FLOAT:
0310         REG_SET_3(FORMAT_CONTROL, 0,
0311             CNVC_BYPASS, 0,
0312             FORMAT_EXPANSION_MODE, mode,
0313             OUTPUT_FP, 1);
0314         is_float = true;
0315         break;
0316     default:
0317 
0318         break;
0319     }
0320 
0321     dpp1_set_degamma_format_float(dpp_base, is_float);
0322 
0323     switch (format) {
0324     case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
0325         pixel_format = 1;
0326         break;
0327     case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
0328         pixel_format = 3;
0329         alpha_en = 0;
0330         break;
0331     case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
0332     case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
0333         pixel_format = 8;
0334         break;
0335     case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
0336     case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
0337         pixel_format = 10;
0338         break;
0339     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
0340         force_disable_cursor = false;
0341         pixel_format = 65;
0342         color_space = COLOR_SPACE_YCBCR709;
0343         select = INPUT_CSC_SELECT_ICSC;
0344         break;
0345     case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
0346         force_disable_cursor = true;
0347         pixel_format = 64;
0348         color_space = COLOR_SPACE_YCBCR709;
0349         select = INPUT_CSC_SELECT_ICSC;
0350         break;
0351     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
0352         force_disable_cursor = true;
0353         pixel_format = 67;
0354         color_space = COLOR_SPACE_YCBCR709;
0355         select = INPUT_CSC_SELECT_ICSC;
0356         break;
0357     case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
0358         force_disable_cursor = true;
0359         pixel_format = 66;
0360         color_space = COLOR_SPACE_YCBCR709;
0361         select = INPUT_CSC_SELECT_ICSC;
0362         break;
0363     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
0364     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
0365         pixel_format = 26; /* ARGB16161616_UNORM */
0366         break;
0367     case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
0368         pixel_format = 24;
0369         break;
0370     case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
0371         pixel_format = 25;
0372         break;
0373     default:
0374         break;
0375     }
0376 
0377     /* Set default color space based on format if none is given. */
0378     color_space = input_color_space ? input_color_space : color_space;
0379 
0380     REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
0381             CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
0382     REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
0383 
0384     // if input adjustments exist, program icsc with those values
0385 
0386     if (input_csc_color_matrix.enable_adjustment
0387                 == true) {
0388         for (i = 0; i < 12; i++)
0389             tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
0390 
0391         tbl_entry.color_space = color_space;
0392 
0393         if (color_space >= COLOR_SPACE_YCBCR601)
0394             select = INPUT_CSC_SELECT_ICSC;
0395         else
0396             select = INPUT_CSC_SELECT_BYPASS;
0397 
0398         dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
0399     } else
0400         dpp1_program_input_csc(dpp_base, color_space, select, NULL);
0401 
0402     if (force_disable_cursor) {
0403         REG_UPDATE(CURSOR_CONTROL,
0404                 CURSOR_ENABLE, 0);
0405         REG_UPDATE(CURSOR0_CONTROL,
0406                 CUR0_ENABLE, 0);
0407     }
0408 }
0409 
0410 void dpp1_set_cursor_attributes(
0411         struct dpp *dpp_base,
0412         struct dc_cursor_attributes *cursor_attributes)
0413 {
0414     enum dc_cursor_color_format color_format = cursor_attributes->color_format;
0415     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0416 
0417     REG_UPDATE_2(CURSOR0_CONTROL,
0418             CUR0_MODE, color_format,
0419             CUR0_EXPANSION_MODE, 0);
0420 
0421     if (color_format == CURSOR_MODE_MONO) {
0422         /* todo: clarify what to program these to */
0423         REG_UPDATE(CURSOR0_COLOR0,
0424                 CUR0_COLOR0, 0x00000000);
0425         REG_UPDATE(CURSOR0_COLOR1,
0426                 CUR0_COLOR1, 0xFFFFFFFF);
0427     }
0428 }
0429 
0430 
0431 void dpp1_set_cursor_position(
0432         struct dpp *dpp_base,
0433         const struct dc_cursor_position *pos,
0434         const struct dc_cursor_mi_param *param,
0435         uint32_t width,
0436         uint32_t height)
0437 {
0438     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0439     int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
0440     int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
0441     uint32_t cur_en = pos->enable ? 1 : 0;
0442 
0443     // Cursor width/height and hotspots need to be rotated for offset calculation
0444     if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
0445         swap(width, height);
0446         if (param->rotation == ROTATION_ANGLE_90) {
0447             src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
0448             src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
0449         }
0450     } else if (param->rotation == ROTATION_ANGLE_180) {
0451         src_x_offset = pos->x - param->viewport.x;
0452         src_y_offset = pos->y - param->viewport.y;
0453     }
0454 
0455 
0456     if (src_x_offset >= (int)param->viewport.width)
0457         cur_en = 0;  /* not visible beyond right edge*/
0458 
0459     if (src_x_offset + (int)width <= 0)
0460         cur_en = 0;  /* not visible beyond left edge*/
0461 
0462     if (src_y_offset >= (int)param->viewport.height)
0463         cur_en = 0;  /* not visible beyond bottom edge*/
0464 
0465     if (src_y_offset + (int)height <= 0)
0466         cur_en = 0;  /* not visible beyond top edge*/
0467 
0468     REG_UPDATE(CURSOR0_CONTROL,
0469             CUR0_ENABLE, cur_en);
0470 
0471 }
0472 
0473 void dpp1_cnv_set_optional_cursor_attributes(
0474         struct dpp *dpp_base,
0475         struct dpp_cursor_attributes *attr)
0476 {
0477     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0478 
0479     if (attr) {
0480         REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_BIAS,  attr->bias);
0481         REG_UPDATE(CURSOR0_FP_SCALE_BIAS,  CUR0_FP_SCALE, attr->scale);
0482     }
0483 }
0484 
0485 void dpp1_dppclk_control(
0486         struct dpp *dpp_base,
0487         bool dppclk_div,
0488         bool enable)
0489 {
0490     struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
0491 
0492     if (enable) {
0493         if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
0494             REG_UPDATE_2(DPP_CONTROL,
0495                 DPPCLK_RATE_CONTROL, dppclk_div,
0496                 DPP_CLOCK_ENABLE, 1);
0497         else
0498             REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
0499     } else
0500         REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
0501 }
0502 
0503 static const struct dpp_funcs dcn10_dpp_funcs = {
0504         .dpp_read_state = dpp_read_state,
0505         .dpp_reset = dpp_reset,
0506         .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
0507         .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
0508         .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
0509         .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
0510         .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
0511         .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
0512         .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
0513         .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
0514         .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
0515         .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
0516         .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
0517         .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
0518         .dpp_set_degamma = dpp1_set_degamma,
0519         .dpp_program_input_lut      = dpp1_program_input_lut,
0520         .dpp_program_degamma_pwl    = dpp1_set_degamma_pwl,
0521         .dpp_setup          = dpp1_cnv_setup,
0522         .dpp_full_bypass        = dpp1_full_bypass,
0523         .set_cursor_attributes = dpp1_set_cursor_attributes,
0524         .set_cursor_position = dpp1_set_cursor_position,
0525         .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
0526         .dpp_dppclk_control = dpp1_dppclk_control,
0527         .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
0528         .dpp_program_blnd_lut = NULL,
0529         .dpp_program_shaper_lut = NULL,
0530         .dpp_program_3dlut = NULL
0531 };
0532 
0533 static struct dpp_caps dcn10_dpp_cap = {
0534     .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
0535     .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
0536 };
0537 
0538 /*****************************************/
0539 /* Constructor, Destructor               */
0540 /*****************************************/
0541 
0542 void dpp1_construct(
0543     struct dcn10_dpp *dpp,
0544     struct dc_context *ctx,
0545     uint32_t inst,
0546     const struct dcn_dpp_registers *tf_regs,
0547     const struct dcn_dpp_shift *tf_shift,
0548     const struct dcn_dpp_mask *tf_mask)
0549 {
0550     dpp->base.ctx = ctx;
0551 
0552     dpp->base.inst = inst;
0553     dpp->base.funcs = &dcn10_dpp_funcs;
0554     dpp->base.caps = &dcn10_dpp_cap;
0555 
0556     dpp->tf_regs = tf_regs;
0557     dpp->tf_shift = tf_shift;
0558     dpp->tf_mask = tf_mask;
0559 
0560     dpp->lb_pixel_depth_supported =
0561         LB_PIXEL_DEPTH_18BPP |
0562         LB_PIXEL_DEPTH_24BPP |
0563         LB_PIXEL_DEPTH_30BPP |
0564         LB_PIXEL_DEPTH_36BPP;
0565 
0566     dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
0567     dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
0568 }
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