dc/dce80/dce80_timing_generator.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027
0028 /* include DCE8 register header files */
0029 #include "dce/dce_8_0_d.h"
0030 #include "dce/dce_8_0_sh_mask.h"
0031
0032 #include "dc_types.h"
0033
0034 #include "include/grph_object_id.h"
0035 #include "include/logger_interface.h"
0036 #include "../dce110/dce110_timing_generator.h"
0037 #include "dce80_timing_generator.h"
0038
0039 #include "timing_generator.h"
0040
0041 enum black_color_format {
0042     BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,   /* used as index in array */
0043     BLACK_COLOR_FORMAT_RGB_LIMITED,
0044     BLACK_COLOR_FORMAT_YUV_TV,
0045     BLACK_COLOR_FORMAT_YUV_CV,
0046     BLACK_COLOR_FORMAT_YUV_SUPER_AA,
0047
0048     BLACK_COLOR_FORMAT_COUNT
0049 };
0050
0051 static const struct dce110_timing_generator_offsets reg_offsets[] = {
0052 {
0053     .crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0054     .dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0055 },
0056 {
0057     .crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0058     .dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0059 },
0060 {
0061     .crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0062     .dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0063 },
0064 {
0065     .crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0066     .dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0067 },
0068 {
0069     .crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0070     .dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0071 },
0072 {
0073     .crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
0074     .dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
0075 }
0076 };
0077
0078 #define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
0079
0080 #define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
0081 #define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
0082
0083 #define CRTC_REG(reg) (reg + tg110->offsets.crtc)
0084 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
0085 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
0086
0087 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
0088 {
0089     uint64_t pix_dur;
0090     uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
0091                     + DCE110TG_FROM_TG(tg)->offsets.dmif;
0092     uint32_t value = dm_read_reg(tg->ctx, addr);
0093
0094     if (pix_clk_100hz == 0)
0095         return;
0096
0097     pix_dur = div_u64(10000000000ull, pix_clk_100hz);
0098
0099     set_reg_field_value(
0100         value,
0101         pix_dur,
0102         DPG_PIPE_ARBITRATION_CONTROL1,
0103         PIXEL_DURATION);
0104
0105     dm_write_reg(tg->ctx, addr, value);
0106 }
0107
0108 static void program_timing(struct timing_generator *tg,
0109     const struct dc_crtc_timing *timing,
0110     int vready_offset,
0111     int vstartup_start,
0112     int vupdate_offset,
0113     int vupdate_width,
0114     const enum signal_type signal,
0115     bool use_vbios)
0116 {
0117     if (!use_vbios)
0118         program_pix_dur(tg, timing->pix_clk_100hz);
0119
0120     dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios);
0121 }
0122
0123 static void dce80_timing_generator_enable_advanced_request(
0124     struct timing_generator *tg,
0125     bool enable,
0126     const struct dc_crtc_timing *timing)
0127 {
0128     struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
0129     uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
0130     uint32_t value = dm_read_reg(tg->ctx, addr);
0131
0132     if (enable) {
0133         set_reg_field_value(
0134             value,
0135             0,
0136             CRTC_START_LINE_CONTROL,
0137             CRTC_LEGACY_REQUESTOR_EN);
0138     } else {
0139         set_reg_field_value(
0140             value,
0141             1,
0142             CRTC_START_LINE_CONTROL,
0143             CRTC_LEGACY_REQUESTOR_EN);
0144     }
0145
0146     if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
0147         set_reg_field_value(
0148             value,
0149             3,
0150             CRTC_START_LINE_CONTROL,
0151             CRTC_ADVANCED_START_LINE_POSITION);
0152         set_reg_field_value(
0153             value,
0154             0,
0155             CRTC_START_LINE_CONTROL,
0156             CRTC_PREFETCH_EN);
0157     } else {
0158         set_reg_field_value(
0159             value,
0160             4,
0161             CRTC_START_LINE_CONTROL,
0162             CRTC_ADVANCED_START_LINE_POSITION);
0163         set_reg_field_value(
0164             value,
0165             1,
0166             CRTC_START_LINE_CONTROL,
0167             CRTC_PREFETCH_EN);
0168     }
0169
0170     set_reg_field_value(
0171         value,
0172         1,
0173         CRTC_START_LINE_CONTROL,
0174         CRTC_PROGRESSIVE_START_LINE_EARLY);
0175
0176     set_reg_field_value(
0177         value,
0178         1,
0179         CRTC_START_LINE_CONTROL,
0180         CRTC_INTERLACE_START_LINE_EARLY);
0181
0182     dm_write_reg(tg->ctx, addr, value);
0183 }
0184
0185 static const struct timing_generator_funcs dce80_tg_funcs = {
0186         .validate_timing = dce110_tg_validate_timing,
0187         .program_timing = program_timing,
0188         .enable_crtc = dce110_timing_generator_enable_crtc,
0189         .disable_crtc = dce110_timing_generator_disable_crtc,
0190         .is_counter_moving = dce110_timing_generator_is_counter_moving,
0191         .get_position = dce110_timing_generator_get_position,
0192         .get_frame_count = dce110_timing_generator_get_vblank_counter,
0193         .get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
0194         .set_early_control = dce110_timing_generator_set_early_control,
0195         .wait_for_state = dce110_tg_wait_for_state,
0196         .set_blank = dce110_tg_set_blank,
0197         .is_blanked = dce110_tg_is_blanked,
0198         .set_colors = dce110_tg_set_colors,
0199         .set_overscan_blank_color =
0200                 dce110_timing_generator_set_overscan_color_black,
0201         .set_blank_color = dce110_timing_generator_program_blank_color,
0202         .disable_vga = dce110_timing_generator_disable_vga,
0203         .did_triggered_reset_occur =
0204                 dce110_timing_generator_did_triggered_reset_occur,
0205         .setup_global_swap_lock =
0206                 dce110_timing_generator_setup_global_swap_lock,
0207         .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
0208         .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
0209         .tear_down_global_swap_lock =
0210                 dce110_timing_generator_tear_down_global_swap_lock,
0211         .set_drr = dce110_timing_generator_set_drr,
0212         .get_last_used_drr_vtotal = NULL,
0213         .set_static_screen_control =
0214             dce110_timing_generator_set_static_screen_control,
0215         .set_test_pattern = dce110_timing_generator_set_test_pattern,
0216         .arm_vert_intr = dce110_arm_vert_intr,
0217
0218         /* DCE8.0 overrides */
0219         .enable_advanced_request =
0220                 dce80_timing_generator_enable_advanced_request,
0221         .configure_crc = dce110_configure_crc,
0222         .get_crc = dce110_get_crc,
0223 };
0224
0225 void dce80_timing_generator_construct(
0226     struct dce110_timing_generator *tg110,
0227     struct dc_context *ctx,
0228     uint32_t instance,
0229     const struct dce110_timing_generator_offsets *offsets)
0230 {
0231     tg110->controller_id = CONTROLLER_ID_D0 + instance;
0232     tg110->base.inst = instance;
0233     tg110->offsets = *offsets;
0234     tg110->derived_offsets = reg_offsets[instance];
0235
0236     tg110->base.funcs = &dce80_tg_funcs;
0237
0238     tg110->base.ctx = ctx;
0239     tg110->base.bp = ctx->dc_bios;
0240
0241     tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
0242     tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
0243
0244     tg110->min_h_blank = 56;
0245     tg110->min_h_front_porch = 4;
0246     tg110->min_h_back_porch = 4;
0247 }
0248