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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dce/dce_8_0_d.h"
0027 #include "dce/dce_8_0_sh_mask.h"
0028 
0029 #include "dm_services.h"
0030 
0031 #include "link_encoder.h"
0032 #include "stream_encoder.h"
0033 
0034 #include "resource.h"
0035 #include "include/irq_service_interface.h"
0036 #include "irq/dce80/irq_service_dce80.h"
0037 #include "dce110/dce110_timing_generator.h"
0038 #include "dce110/dce110_resource.h"
0039 #include "dce80/dce80_timing_generator.h"
0040 #include "dce/dce_mem_input.h"
0041 #include "dce/dce_link_encoder.h"
0042 #include "dce/dce_stream_encoder.h"
0043 #include "dce/dce_ipp.h"
0044 #include "dce/dce_transform.h"
0045 #include "dce/dce_opp.h"
0046 #include "dce/dce_clock_source.h"
0047 #include "dce/dce_audio.h"
0048 #include "dce/dce_hwseq.h"
0049 #include "dce80/dce80_hw_sequencer.h"
0050 #include "dce100/dce100_resource.h"
0051 #include "dce/dce_panel_cntl.h"
0052 
0053 #include "reg_helper.h"
0054 
0055 #include "dce/dce_dmcu.h"
0056 #include "dce/dce_aux.h"
0057 #include "dce/dce_abm.h"
0058 #include "dce/dce_i2c.h"
0059 /* TODO remove this include */
0060 
0061 #include "dce80_resource.h"
0062 
0063 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
0064 #include "gmc/gmc_7_1_d.h"
0065 #include "gmc/gmc_7_1_sh_mask.h"
0066 #endif
0067 
0068 #ifndef mmDP_DPHY_INTERNAL_CTRL
0069 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
0070 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
0071 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
0072 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
0073 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
0074 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
0075 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
0076 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
0077 #endif
0078 
0079 
0080 #ifndef mmBIOS_SCRATCH_2
0081     #define mmBIOS_SCRATCH_2 0x05CB
0082     #define mmBIOS_SCRATCH_3 0x05CC
0083     #define mmBIOS_SCRATCH_6 0x05CF
0084 #endif
0085 
0086 #ifndef mmDP_DPHY_FAST_TRAINING
0087     #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
0088     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
0089     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
0090     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
0091     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
0092     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
0093     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
0094     #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
0095 #endif
0096 
0097 
0098 #ifndef mmHPD_DC_HPD_CONTROL
0099     #define mmHPD_DC_HPD_CONTROL                            0x189A
0100     #define mmHPD0_DC_HPD_CONTROL                           0x189A
0101     #define mmHPD1_DC_HPD_CONTROL                           0x18A2
0102     #define mmHPD2_DC_HPD_CONTROL                           0x18AA
0103     #define mmHPD3_DC_HPD_CONTROL                           0x18B2
0104     #define mmHPD4_DC_HPD_CONTROL                           0x18BA
0105     #define mmHPD5_DC_HPD_CONTROL                           0x18C2
0106 #endif
0107 
0108 #define DCE11_DIG_FE_CNTL 0x4a00
0109 #define DCE11_DIG_BE_CNTL 0x4a47
0110 #define DCE11_DP_SEC 0x4ac3
0111 
0112 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
0113         {
0114             .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
0115             .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
0116             .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
0117                     - mmDPG_WATERMARK_MASK_CONTROL),
0118         },
0119         {
0120             .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
0121             .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
0122             .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
0123                     - mmDPG_WATERMARK_MASK_CONTROL),
0124         },
0125         {
0126             .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
0127             .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
0128             .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
0129                     - mmDPG_WATERMARK_MASK_CONTROL),
0130         },
0131         {
0132             .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
0133             .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
0134             .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
0135                     - mmDPG_WATERMARK_MASK_CONTROL),
0136         },
0137         {
0138             .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
0139             .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
0140             .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
0141                     - mmDPG_WATERMARK_MASK_CONTROL),
0142         },
0143         {
0144             .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
0145             .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
0146             .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
0147                     - mmDPG_WATERMARK_MASK_CONTROL),
0148         }
0149 };
0150 
0151 /* set register offset */
0152 #define SR(reg_name)\
0153     .reg_name = mm ## reg_name
0154 
0155 /* set register offset with instance */
0156 #define SRI(reg_name, block, id)\
0157     .reg_name = mm ## block ## id ## _ ## reg_name
0158 
0159 #define ipp_regs(id)\
0160 [id] = {\
0161         IPP_COMMON_REG_LIST_DCE_BASE(id)\
0162 }
0163 
0164 static const struct dce_ipp_registers ipp_regs[] = {
0165         ipp_regs(0),
0166         ipp_regs(1),
0167         ipp_regs(2),
0168         ipp_regs(3),
0169         ipp_regs(4),
0170         ipp_regs(5)
0171 };
0172 
0173 static const struct dce_ipp_shift ipp_shift = {
0174         IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0175 };
0176 
0177 static const struct dce_ipp_mask ipp_mask = {
0178         IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0179 };
0180 
0181 #define transform_regs(id)\
0182 [id] = {\
0183         XFM_COMMON_REG_LIST_DCE80(id)\
0184 }
0185 
0186 static const struct dce_transform_registers xfm_regs[] = {
0187         transform_regs(0),
0188         transform_regs(1),
0189         transform_regs(2),
0190         transform_regs(3),
0191         transform_regs(4),
0192         transform_regs(5)
0193 };
0194 
0195 static const struct dce_transform_shift xfm_shift = {
0196         XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
0197 };
0198 
0199 static const struct dce_transform_mask xfm_mask = {
0200         XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
0201 };
0202 
0203 #define aux_regs(id)\
0204 [id] = {\
0205     AUX_REG_LIST(id)\
0206 }
0207 
0208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
0209     aux_regs(0),
0210     aux_regs(1),
0211     aux_regs(2),
0212     aux_regs(3),
0213     aux_regs(4),
0214     aux_regs(5)
0215 };
0216 
0217 #define hpd_regs(id)\
0218 [id] = {\
0219     HPD_REG_LIST(id)\
0220 }
0221 
0222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
0223         hpd_regs(0),
0224         hpd_regs(1),
0225         hpd_regs(2),
0226         hpd_regs(3),
0227         hpd_regs(4),
0228         hpd_regs(5)
0229 };
0230 
0231 #define link_regs(id)\
0232 [id] = {\
0233     LE_DCE80_REG_LIST(id)\
0234 }
0235 
0236 static const struct dce110_link_enc_registers link_enc_regs[] = {
0237     link_regs(0),
0238     link_regs(1),
0239     link_regs(2),
0240     link_regs(3),
0241     link_regs(4),
0242     link_regs(5),
0243     link_regs(6),
0244 };
0245 
0246 #define stream_enc_regs(id)\
0247 [id] = {\
0248     SE_COMMON_REG_LIST_DCE_BASE(id),\
0249     .AFMT_CNTL = 0,\
0250 }
0251 
0252 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
0253     stream_enc_regs(0),
0254     stream_enc_regs(1),
0255     stream_enc_regs(2),
0256     stream_enc_regs(3),
0257     stream_enc_regs(4),
0258     stream_enc_regs(5),
0259     stream_enc_regs(6)
0260 };
0261 
0262 static const struct dce_stream_encoder_shift se_shift = {
0263         SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
0264 };
0265 
0266 static const struct dce_stream_encoder_mask se_mask = {
0267         SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
0268 };
0269 
0270 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0271     { DCE_PANEL_CNTL_REG_LIST() }
0272 };
0273 
0274 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0275     DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0276 };
0277 
0278 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0279     DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0280 };
0281 
0282 #define opp_regs(id)\
0283 [id] = {\
0284     OPP_DCE_80_REG_LIST(id),\
0285 }
0286 
0287 static const struct dce_opp_registers opp_regs[] = {
0288     opp_regs(0),
0289     opp_regs(1),
0290     opp_regs(2),
0291     opp_regs(3),
0292     opp_regs(4),
0293     opp_regs(5)
0294 };
0295 
0296 static const struct dce_opp_shift opp_shift = {
0297     OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
0298 };
0299 
0300 static const struct dce_opp_mask opp_mask = {
0301     OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
0302 };
0303 
0304 static const struct dce110_aux_registers_shift aux_shift = {
0305     DCE10_AUX_MASK_SH_LIST(__SHIFT)
0306 };
0307 
0308 static const struct dce110_aux_registers_mask aux_mask = {
0309     DCE10_AUX_MASK_SH_LIST(_MASK)
0310 };
0311 
0312 #define aux_engine_regs(id)\
0313 [id] = {\
0314     AUX_COMMON_REG_LIST(id), \
0315     .AUX_RESET_MASK = 0 \
0316 }
0317 
0318 static const struct dce110_aux_registers aux_engine_regs[] = {
0319         aux_engine_regs(0),
0320         aux_engine_regs(1),
0321         aux_engine_regs(2),
0322         aux_engine_regs(3),
0323         aux_engine_regs(4),
0324         aux_engine_regs(5)
0325 };
0326 
0327 #define audio_regs(id)\
0328 [id] = {\
0329     AUD_COMMON_REG_LIST(id)\
0330 }
0331 
0332 static const struct dce_audio_registers audio_regs[] = {
0333     audio_regs(0),
0334     audio_regs(1),
0335     audio_regs(2),
0336     audio_regs(3),
0337     audio_regs(4),
0338     audio_regs(5),
0339     audio_regs(6),
0340 };
0341 
0342 static const struct dce_audio_shift audio_shift = {
0343         AUD_COMMON_MASK_SH_LIST(__SHIFT)
0344 };
0345 
0346 static const struct dce_audio_mask audio_mask = {
0347         AUD_COMMON_MASK_SH_LIST(_MASK)
0348 };
0349 
0350 #define clk_src_regs(id)\
0351 [id] = {\
0352     CS_COMMON_REG_LIST_DCE_80(id),\
0353 }
0354 
0355 
0356 static const struct dce110_clk_src_regs clk_src_regs[] = {
0357     clk_src_regs(0),
0358     clk_src_regs(1),
0359     clk_src_regs(2)
0360 };
0361 
0362 static const struct dce110_clk_src_shift cs_shift = {
0363         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0364 };
0365 
0366 static const struct dce110_clk_src_mask cs_mask = {
0367         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0368 };
0369 
0370 static const struct bios_registers bios_regs = {
0371     .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
0372     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
0373 };
0374 
0375 static const struct resource_caps res_cap = {
0376         .num_timing_generator = 6,
0377         .num_audio = 6,
0378         .num_stream_encoder = 6,
0379         .num_pll = 3,
0380         .num_ddc = 6,
0381 };
0382 
0383 static const struct resource_caps res_cap_81 = {
0384         .num_timing_generator = 4,
0385         .num_audio = 7,
0386         .num_stream_encoder = 7,
0387         .num_pll = 3,
0388         .num_ddc = 6,
0389 };
0390 
0391 static const struct resource_caps res_cap_83 = {
0392         .num_timing_generator = 2,
0393         .num_audio = 6,
0394         .num_stream_encoder = 6,
0395         .num_pll = 2,
0396         .num_ddc = 2,
0397 };
0398 
0399 static const struct dc_plane_cap plane_cap = {
0400     .type = DC_PLANE_TYPE_DCE_RGB,
0401 
0402     .pixel_format_support = {
0403             .argb8888 = true,
0404             .nv12 = false,
0405             .fp16 = true
0406     },
0407 
0408     .max_upscale_factor = {
0409             .argb8888 = 16000,
0410             .nv12 = 1,
0411             .fp16 = 1
0412     },
0413 
0414     .max_downscale_factor = {
0415             .argb8888 = 250,
0416             .nv12 = 1,
0417             .fp16 = 1
0418     }
0419 };
0420 
0421 static const struct dce_dmcu_registers dmcu_regs = {
0422         DMCU_DCE80_REG_LIST()
0423 };
0424 
0425 static const struct dce_dmcu_shift dmcu_shift = {
0426         DMCU_MASK_SH_LIST_DCE80(__SHIFT)
0427 };
0428 
0429 static const struct dce_dmcu_mask dmcu_mask = {
0430         DMCU_MASK_SH_LIST_DCE80(_MASK)
0431 };
0432 static const struct dce_abm_registers abm_regs = {
0433         ABM_DCE110_COMMON_REG_LIST()
0434 };
0435 
0436 static const struct dce_abm_shift abm_shift = {
0437         ABM_MASK_SH_LIST_DCE110(__SHIFT)
0438 };
0439 
0440 static const struct dce_abm_mask abm_mask = {
0441         ABM_MASK_SH_LIST_DCE110(_MASK)
0442 };
0443 
0444 #define CTX  ctx
0445 #define REG(reg) mm ## reg
0446 
0447 #ifndef mmCC_DC_HDMI_STRAPS
0448 #define mmCC_DC_HDMI_STRAPS 0x1918
0449 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
0450 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
0451 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
0452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
0453 #endif
0454 
0455 static int map_transmitter_id_to_phy_instance(
0456     enum transmitter transmitter)
0457 {
0458     switch (transmitter) {
0459     case TRANSMITTER_UNIPHY_A:
0460         return 0;
0461     case TRANSMITTER_UNIPHY_B:
0462         return 1;
0463     case TRANSMITTER_UNIPHY_C:
0464         return 2;
0465     case TRANSMITTER_UNIPHY_D:
0466         return 3;
0467     case TRANSMITTER_UNIPHY_E:
0468         return 4;
0469     case TRANSMITTER_UNIPHY_F:
0470         return 5;
0471     case TRANSMITTER_UNIPHY_G:
0472         return 6;
0473     default:
0474         ASSERT(0);
0475         return 0;
0476     }
0477 }
0478 
0479 static void read_dce_straps(
0480     struct dc_context *ctx,
0481     struct resource_straps *straps)
0482 {
0483     REG_GET_2(CC_DC_HDMI_STRAPS,
0484             HDMI_DISABLE, &straps->hdmi_disable,
0485             AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
0486 
0487     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
0488 }
0489 
0490 static struct audio *create_audio(
0491         struct dc_context *ctx, unsigned int inst)
0492 {
0493     return dce_audio_create(ctx, inst,
0494             &audio_regs[inst], &audio_shift, &audio_mask);
0495 }
0496 
0497 static struct timing_generator *dce80_timing_generator_create(
0498         struct dc_context *ctx,
0499         uint32_t instance,
0500         const struct dce110_timing_generator_offsets *offsets)
0501 {
0502     struct dce110_timing_generator *tg110 =
0503         kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
0504 
0505     if (!tg110)
0506         return NULL;
0507 
0508     dce80_timing_generator_construct(tg110, ctx, instance, offsets);
0509     return &tg110->base;
0510 }
0511 
0512 static struct output_pixel_processor *dce80_opp_create(
0513     struct dc_context *ctx,
0514     uint32_t inst)
0515 {
0516     struct dce110_opp *opp =
0517         kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
0518 
0519     if (!opp)
0520         return NULL;
0521 
0522     dce110_opp_construct(opp,
0523                  ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0524     return &opp->base;
0525 }
0526 
0527 static struct dce_aux *dce80_aux_engine_create(
0528     struct dc_context *ctx,
0529     uint32_t inst)
0530 {
0531     struct aux_engine_dce110 *aux_engine =
0532         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0533 
0534     if (!aux_engine)
0535         return NULL;
0536 
0537     dce110_aux_engine_construct(aux_engine, ctx, inst,
0538                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0539                     &aux_engine_regs[inst],
0540                     &aux_mask,
0541                     &aux_shift,
0542                     ctx->dc->caps.extended_aux_timeout_support);
0543 
0544     return &aux_engine->base;
0545 }
0546 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0547 
0548 static const struct dce_i2c_registers i2c_hw_regs[] = {
0549         i2c_inst_regs(1),
0550         i2c_inst_regs(2),
0551         i2c_inst_regs(3),
0552         i2c_inst_regs(4),
0553         i2c_inst_regs(5),
0554         i2c_inst_regs(6),
0555 };
0556 
0557 static const struct dce_i2c_shift i2c_shifts = {
0558         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0559 };
0560 
0561 static const struct dce_i2c_mask i2c_masks = {
0562         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0563 };
0564 
0565 static struct dce_i2c_hw *dce80_i2c_hw_create(
0566     struct dc_context *ctx,
0567     uint32_t inst)
0568 {
0569     struct dce_i2c_hw *dce_i2c_hw =
0570         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0571 
0572     if (!dce_i2c_hw)
0573         return NULL;
0574 
0575     dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0576                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0577 
0578     return dce_i2c_hw;
0579 }
0580 
0581 static struct dce_i2c_sw *dce80_i2c_sw_create(
0582     struct dc_context *ctx)
0583 {
0584     struct dce_i2c_sw *dce_i2c_sw =
0585         kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
0586 
0587     if (!dce_i2c_sw)
0588         return NULL;
0589 
0590     dce_i2c_sw_construct(dce_i2c_sw, ctx);
0591 
0592     return dce_i2c_sw;
0593 }
0594 static struct stream_encoder *dce80_stream_encoder_create(
0595     enum engine_id eng_id,
0596     struct dc_context *ctx)
0597 {
0598     struct dce110_stream_encoder *enc110 =
0599         kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
0600 
0601     if (!enc110)
0602         return NULL;
0603 
0604     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
0605                     &stream_enc_regs[eng_id],
0606                     &se_shift, &se_mask);
0607     return &enc110->base;
0608 }
0609 
0610 #define SRII(reg_name, block, id)\
0611     .reg_name[id] = mm ## block ## id ## _ ## reg_name
0612 
0613 static const struct dce_hwseq_registers hwseq_reg = {
0614         HWSEQ_DCE8_REG_LIST()
0615 };
0616 
0617 static const struct dce_hwseq_shift hwseq_shift = {
0618         HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
0619 };
0620 
0621 static const struct dce_hwseq_mask hwseq_mask = {
0622         HWSEQ_DCE8_MASK_SH_LIST(_MASK)
0623 };
0624 
0625 static struct dce_hwseq *dce80_hwseq_create(
0626     struct dc_context *ctx)
0627 {
0628     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0629 
0630     if (hws) {
0631         hws->ctx = ctx;
0632         hws->regs = &hwseq_reg;
0633         hws->shifts = &hwseq_shift;
0634         hws->masks = &hwseq_mask;
0635     }
0636     return hws;
0637 }
0638 
0639 static const struct resource_create_funcs res_create_funcs = {
0640     .read_dce_straps = read_dce_straps,
0641     .create_audio = create_audio,
0642     .create_stream_encoder = dce80_stream_encoder_create,
0643     .create_hwseq = dce80_hwseq_create,
0644 };
0645 
0646 #define mi_inst_regs(id) { \
0647     MI_DCE8_REG_LIST(id), \
0648     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
0649 }
0650 static const struct dce_mem_input_registers mi_regs[] = {
0651         mi_inst_regs(0),
0652         mi_inst_regs(1),
0653         mi_inst_regs(2),
0654         mi_inst_regs(3),
0655         mi_inst_regs(4),
0656         mi_inst_regs(5),
0657 };
0658 
0659 static const struct dce_mem_input_shift mi_shifts = {
0660         MI_DCE8_MASK_SH_LIST(__SHIFT),
0661         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
0662 };
0663 
0664 static const struct dce_mem_input_mask mi_masks = {
0665         MI_DCE8_MASK_SH_LIST(_MASK),
0666         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
0667 };
0668 
0669 static struct mem_input *dce80_mem_input_create(
0670     struct dc_context *ctx,
0671     uint32_t inst)
0672 {
0673     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
0674                            GFP_KERNEL);
0675 
0676     if (!dce_mi) {
0677         BREAK_TO_DEBUGGER();
0678         return NULL;
0679     }
0680 
0681     dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
0682     dce_mi->wa.single_head_rdreq_dmif_limit = 2;
0683     return &dce_mi->base;
0684 }
0685 
0686 static void dce80_transform_destroy(struct transform **xfm)
0687 {
0688     kfree(TO_DCE_TRANSFORM(*xfm));
0689     *xfm = NULL;
0690 }
0691 
0692 static struct transform *dce80_transform_create(
0693     struct dc_context *ctx,
0694     uint32_t inst)
0695 {
0696     struct dce_transform *transform =
0697         kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
0698 
0699     if (!transform)
0700         return NULL;
0701 
0702     dce_transform_construct(transform, ctx, inst,
0703                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
0704     transform->prescaler_on = false;
0705     return &transform->base;
0706 }
0707 
0708 static const struct encoder_feature_support link_enc_feature = {
0709         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0710         .max_hdmi_pixel_clock = 297000,
0711         .flags.bits.IS_HBR2_CAPABLE = true,
0712         .flags.bits.IS_TPS3_CAPABLE = true
0713 };
0714 
0715 static struct link_encoder *dce80_link_encoder_create(
0716     struct dc_context *ctx,
0717     const struct encoder_init_data *enc_init_data)
0718 {
0719     struct dce110_link_encoder *enc110 =
0720         kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
0721     int link_regs_id;
0722 
0723     if (!enc110)
0724         return NULL;
0725 
0726     link_regs_id =
0727         map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
0728 
0729     dce110_link_encoder_construct(enc110,
0730                       enc_init_data,
0731                       &link_enc_feature,
0732                       &link_enc_regs[link_regs_id],
0733                       &link_enc_aux_regs[enc_init_data->channel - 1],
0734                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
0735     return &enc110->base;
0736 }
0737 
0738 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0739 {
0740     struct dce_panel_cntl *panel_cntl =
0741         kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0742 
0743     if (!panel_cntl)
0744         return NULL;
0745 
0746     dce_panel_cntl_construct(panel_cntl,
0747             init_data,
0748             &panel_cntl_regs[init_data->inst],
0749             &panel_cntl_shift,
0750             &panel_cntl_mask);
0751 
0752     return &panel_cntl->base;
0753 }
0754 
0755 static struct clock_source *dce80_clock_source_create(
0756     struct dc_context *ctx,
0757     struct dc_bios *bios,
0758     enum clock_source_id id,
0759     const struct dce110_clk_src_regs *regs,
0760     bool dp_clk_src)
0761 {
0762     struct dce110_clk_src *clk_src =
0763         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0764 
0765     if (!clk_src)
0766         return NULL;
0767 
0768     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
0769             regs, &cs_shift, &cs_mask)) {
0770         clk_src->base.dp_clk_src = dp_clk_src;
0771         return &clk_src->base;
0772     }
0773 
0774     kfree(clk_src);
0775     BREAK_TO_DEBUGGER();
0776     return NULL;
0777 }
0778 
0779 static void dce80_clock_source_destroy(struct clock_source **clk_src)
0780 {
0781     kfree(TO_DCE110_CLK_SRC(*clk_src));
0782     *clk_src = NULL;
0783 }
0784 
0785 static struct input_pixel_processor *dce80_ipp_create(
0786     struct dc_context *ctx, uint32_t inst)
0787 {
0788     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
0789 
0790     if (!ipp) {
0791         BREAK_TO_DEBUGGER();
0792         return NULL;
0793     }
0794 
0795     dce_ipp_construct(ipp, ctx, inst,
0796             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0797     return &ipp->base;
0798 }
0799 
0800 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
0801 {
0802     unsigned int i;
0803 
0804     for (i = 0; i < pool->base.pipe_count; i++) {
0805         if (pool->base.opps[i] != NULL)
0806             dce110_opp_destroy(&pool->base.opps[i]);
0807 
0808         if (pool->base.transforms[i] != NULL)
0809             dce80_transform_destroy(&pool->base.transforms[i]);
0810 
0811         if (pool->base.ipps[i] != NULL)
0812             dce_ipp_destroy(&pool->base.ipps[i]);
0813 
0814         if (pool->base.mis[i] != NULL) {
0815             kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
0816             pool->base.mis[i] = NULL;
0817         }
0818 
0819         if (pool->base.timing_generators[i] != NULL)    {
0820             kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
0821             pool->base.timing_generators[i] = NULL;
0822         }
0823     }
0824 
0825     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
0826         if (pool->base.engines[i] != NULL)
0827             dce110_engine_destroy(&pool->base.engines[i]);
0828         if (pool->base.hw_i2cs[i] != NULL) {
0829             kfree(pool->base.hw_i2cs[i]);
0830             pool->base.hw_i2cs[i] = NULL;
0831         }
0832         if (pool->base.sw_i2cs[i] != NULL) {
0833             kfree(pool->base.sw_i2cs[i]);
0834             pool->base.sw_i2cs[i] = NULL;
0835         }
0836     }
0837 
0838     for (i = 0; i < pool->base.stream_enc_count; i++) {
0839         if (pool->base.stream_enc[i] != NULL)
0840             kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0841     }
0842 
0843     for (i = 0; i < pool->base.clk_src_count; i++) {
0844         if (pool->base.clock_sources[i] != NULL) {
0845             dce80_clock_source_destroy(&pool->base.clock_sources[i]);
0846         }
0847     }
0848 
0849     if (pool->base.abm != NULL)
0850             dce_abm_destroy(&pool->base.abm);
0851 
0852     if (pool->base.dmcu != NULL)
0853             dce_dmcu_destroy(&pool->base.dmcu);
0854 
0855     if (pool->base.dp_clock_source != NULL)
0856         dce80_clock_source_destroy(&pool->base.dp_clock_source);
0857 
0858     for (i = 0; i < pool->base.audio_count; i++)    {
0859         if (pool->base.audios[i] != NULL) {
0860             dce_aud_destroy(&pool->base.audios[i]);
0861         }
0862     }
0863 
0864     if (pool->base.irqs != NULL) {
0865         dal_irq_service_destroy(&pool->base.irqs);
0866     }
0867 }
0868 
0869 static bool dce80_validate_bandwidth(
0870     struct dc *dc,
0871     struct dc_state *context,
0872     bool fast_validate)
0873 {
0874     int i;
0875     bool at_least_one_pipe = false;
0876 
0877     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0878         if (context->res_ctx.pipe_ctx[i].stream)
0879             at_least_one_pipe = true;
0880     }
0881 
0882     if (at_least_one_pipe) {
0883         /* TODO implement when needed but for now hardcode max value*/
0884         context->bw_ctx.bw.dce.dispclk_khz = 681000;
0885         context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
0886     } else {
0887         context->bw_ctx.bw.dce.dispclk_khz = 0;
0888         context->bw_ctx.bw.dce.yclk_khz = 0;
0889     }
0890 
0891     return true;
0892 }
0893 
0894 static bool dce80_validate_surface_sets(
0895         struct dc_state *context)
0896 {
0897     int i;
0898 
0899     for (i = 0; i < context->stream_count; i++) {
0900         if (context->stream_status[i].plane_count == 0)
0901             continue;
0902 
0903         if (context->stream_status[i].plane_count > 1)
0904             return false;
0905 
0906         if (context->stream_status[i].plane_states[0]->format
0907                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
0908             return false;
0909     }
0910 
0911     return true;
0912 }
0913 
0914 static enum dc_status dce80_validate_global(
0915         struct dc *dc,
0916         struct dc_state *context)
0917 {
0918     if (!dce80_validate_surface_sets(context))
0919         return DC_FAIL_SURFACE_VALIDATE;
0920 
0921     return DC_OK;
0922 }
0923 
0924 static void dce80_destroy_resource_pool(struct resource_pool **pool)
0925 {
0926     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
0927 
0928     dce80_resource_destruct(dce110_pool);
0929     kfree(dce110_pool);
0930     *pool = NULL;
0931 }
0932 
0933 static const struct resource_funcs dce80_res_pool_funcs = {
0934     .destroy = dce80_destroy_resource_pool,
0935     .link_enc_create = dce80_link_encoder_create,
0936     .panel_cntl_create = dce80_panel_cntl_create,
0937     .validate_bandwidth = dce80_validate_bandwidth,
0938     .validate_plane = dce100_validate_plane,
0939     .add_stream_to_ctx = dce100_add_stream_to_ctx,
0940     .validate_global = dce80_validate_global,
0941     .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
0942 };
0943 
0944 static bool dce80_construct(
0945     uint8_t num_virtual_links,
0946     struct dc *dc,
0947     struct dce110_resource_pool *pool)
0948 {
0949     unsigned int i;
0950     struct dc_context *ctx = dc->ctx;
0951     struct dc_bios *bp;
0952 
0953     ctx->dc_bios->regs = &bios_regs;
0954 
0955     pool->base.res_cap = &res_cap;
0956     pool->base.funcs = &dce80_res_pool_funcs;
0957 
0958 
0959     /*************************************************
0960      *  Resource + asic cap harcoding                *
0961      *************************************************/
0962     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
0963     pool->base.pipe_count = res_cap.num_timing_generator;
0964     pool->base.timing_generator_count = res_cap.num_timing_generator;
0965     dc->caps.max_downscale_ratio = 200;
0966     dc->caps.i2c_speed_in_khz = 40;
0967     dc->caps.i2c_speed_in_khz_hdcp = 40;
0968     dc->caps.max_cursor_size = 128;
0969     dc->caps.min_horizontal_blanking_period = 80;
0970     dc->caps.dual_link_dvi = true;
0971     dc->caps.extended_aux_timeout_support = false;
0972 
0973     /*************************************************
0974      *  Create resources                             *
0975      *************************************************/
0976 
0977     bp = ctx->dc_bios;
0978 
0979     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
0980         pool->base.dp_clock_source =
0981                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
0982 
0983         pool->base.clock_sources[0] =
0984                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
0985         pool->base.clock_sources[1] =
0986                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
0987         pool->base.clock_sources[2] =
0988                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
0989         pool->base.clk_src_count = 3;
0990 
0991     } else {
0992         pool->base.dp_clock_source =
0993                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
0994 
0995         pool->base.clock_sources[0] =
0996                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
0997         pool->base.clock_sources[1] =
0998                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
0999         pool->base.clk_src_count = 2;
1000     }
1001 
1002     if (pool->base.dp_clock_source == NULL) {
1003         dm_error("DC: failed to create dp clock source!\n");
1004         BREAK_TO_DEBUGGER();
1005         goto res_create_fail;
1006     }
1007 
1008     for (i = 0; i < pool->base.clk_src_count; i++) {
1009         if (pool->base.clock_sources[i] == NULL) {
1010             dm_error("DC: failed to create clock sources!\n");
1011             BREAK_TO_DEBUGGER();
1012             goto res_create_fail;
1013         }
1014     }
1015 
1016     pool->base.dmcu = dce_dmcu_create(ctx,
1017             &dmcu_regs,
1018             &dmcu_shift,
1019             &dmcu_mask);
1020     if (pool->base.dmcu == NULL) {
1021         dm_error("DC: failed to create dmcu!\n");
1022         BREAK_TO_DEBUGGER();
1023         goto res_create_fail;
1024     }
1025 
1026     pool->base.abm = dce_abm_create(ctx,
1027             &abm_regs,
1028             &abm_shift,
1029             &abm_mask);
1030     if (pool->base.abm == NULL) {
1031         dm_error("DC: failed to create abm!\n");
1032         BREAK_TO_DEBUGGER();
1033         goto res_create_fail;
1034     }
1035 
1036     {
1037         struct irq_service_init_data init_data;
1038         init_data.ctx = dc->ctx;
1039         pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1040         if (!pool->base.irqs)
1041             goto res_create_fail;
1042     }
1043 
1044     for (i = 0; i < pool->base.pipe_count; i++) {
1045         pool->base.timing_generators[i] = dce80_timing_generator_create(
1046                 ctx, i, &dce80_tg_offsets[i]);
1047         if (pool->base.timing_generators[i] == NULL) {
1048             BREAK_TO_DEBUGGER();
1049             dm_error("DC: failed to create tg!\n");
1050             goto res_create_fail;
1051         }
1052 
1053         pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1054         if (pool->base.mis[i] == NULL) {
1055             BREAK_TO_DEBUGGER();
1056             dm_error("DC: failed to create memory input!\n");
1057             goto res_create_fail;
1058         }
1059 
1060         pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1061         if (pool->base.ipps[i] == NULL) {
1062             BREAK_TO_DEBUGGER();
1063             dm_error("DC: failed to create input pixel processor!\n");
1064             goto res_create_fail;
1065         }
1066 
1067         pool->base.transforms[i] = dce80_transform_create(ctx, i);
1068         if (pool->base.transforms[i] == NULL) {
1069             BREAK_TO_DEBUGGER();
1070             dm_error("DC: failed to create transform!\n");
1071             goto res_create_fail;
1072         }
1073 
1074         pool->base.opps[i] = dce80_opp_create(ctx, i);
1075         if (pool->base.opps[i] == NULL) {
1076             BREAK_TO_DEBUGGER();
1077             dm_error("DC: failed to create output pixel processor!\n");
1078             goto res_create_fail;
1079         }
1080     }
1081 
1082     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1083         pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1084         if (pool->base.engines[i] == NULL) {
1085             BREAK_TO_DEBUGGER();
1086             dm_error(
1087                 "DC:failed to create aux engine!!\n");
1088             goto res_create_fail;
1089         }
1090         pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1091         if (pool->base.hw_i2cs[i] == NULL) {
1092             BREAK_TO_DEBUGGER();
1093             dm_error(
1094                 "DC:failed to create i2c engine!!\n");
1095             goto res_create_fail;
1096         }
1097         pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1098         if (pool->base.sw_i2cs[i] == NULL) {
1099             BREAK_TO_DEBUGGER();
1100             dm_error(
1101                 "DC:failed to create sw i2c!!\n");
1102             goto res_create_fail;
1103         }
1104     }
1105 
1106     dc->caps.max_planes =  pool->base.pipe_count;
1107 
1108     for (i = 0; i < dc->caps.max_planes; ++i)
1109         dc->caps.planes[i] = plane_cap;
1110 
1111     dc->caps.disable_dp_clk_share = true;
1112 
1113     if (!resource_construct(num_virtual_links, dc, &pool->base,
1114             &res_create_funcs))
1115         goto res_create_fail;
1116 
1117     /* Create hardware sequencer */
1118     dce80_hw_sequencer_construct(dc);
1119 
1120     return true;
1121 
1122 res_create_fail:
1123     dce80_resource_destruct(pool);
1124     return false;
1125 }
1126 
1127 struct resource_pool *dce80_create_resource_pool(
1128     uint8_t num_virtual_links,
1129     struct dc *dc)
1130 {
1131     struct dce110_resource_pool *pool =
1132         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1133 
1134     if (!pool)
1135         return NULL;
1136 
1137     if (dce80_construct(num_virtual_links, dc, pool))
1138         return &pool->base;
1139 
1140     BREAK_TO_DEBUGGER();
1141     return NULL;
1142 }
1143 
1144 static bool dce81_construct(
1145     uint8_t num_virtual_links,
1146     struct dc *dc,
1147     struct dce110_resource_pool *pool)
1148 {
1149     unsigned int i;
1150     struct dc_context *ctx = dc->ctx;
1151     struct dc_bios *bp;
1152 
1153     ctx->dc_bios->regs = &bios_regs;
1154 
1155     pool->base.res_cap = &res_cap_81;
1156     pool->base.funcs = &dce80_res_pool_funcs;
1157 
1158 
1159     /*************************************************
1160      *  Resource + asic cap harcoding                *
1161      *************************************************/
1162     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1163     pool->base.pipe_count = res_cap_81.num_timing_generator;
1164     pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1165     dc->caps.max_downscale_ratio = 200;
1166     dc->caps.i2c_speed_in_khz = 40;
1167     dc->caps.i2c_speed_in_khz_hdcp = 40;
1168     dc->caps.max_cursor_size = 128;
1169     dc->caps.min_horizontal_blanking_period = 80;
1170     dc->caps.is_apu = true;
1171 
1172     /*************************************************
1173      *  Create resources                             *
1174      *************************************************/
1175 
1176     bp = ctx->dc_bios;
1177 
1178     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1179         pool->base.dp_clock_source =
1180                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1181 
1182         pool->base.clock_sources[0] =
1183                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1184         pool->base.clock_sources[1] =
1185                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1186         pool->base.clock_sources[2] =
1187                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1188         pool->base.clk_src_count = 3;
1189 
1190     } else {
1191         pool->base.dp_clock_source =
1192                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1193 
1194         pool->base.clock_sources[0] =
1195                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1196         pool->base.clock_sources[1] =
1197                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1198         pool->base.clk_src_count = 2;
1199     }
1200 
1201     if (pool->base.dp_clock_source == NULL) {
1202         dm_error("DC: failed to create dp clock source!\n");
1203         BREAK_TO_DEBUGGER();
1204         goto res_create_fail;
1205     }
1206 
1207     for (i = 0; i < pool->base.clk_src_count; i++) {
1208         if (pool->base.clock_sources[i] == NULL) {
1209             dm_error("DC: failed to create clock sources!\n");
1210             BREAK_TO_DEBUGGER();
1211             goto res_create_fail;
1212         }
1213     }
1214 
1215     pool->base.dmcu = dce_dmcu_create(ctx,
1216             &dmcu_regs,
1217             &dmcu_shift,
1218             &dmcu_mask);
1219     if (pool->base.dmcu == NULL) {
1220         dm_error("DC: failed to create dmcu!\n");
1221         BREAK_TO_DEBUGGER();
1222         goto res_create_fail;
1223     }
1224 
1225     pool->base.abm = dce_abm_create(ctx,
1226             &abm_regs,
1227             &abm_shift,
1228             &abm_mask);
1229     if (pool->base.abm == NULL) {
1230         dm_error("DC: failed to create abm!\n");
1231         BREAK_TO_DEBUGGER();
1232         goto res_create_fail;
1233     }
1234 
1235     {
1236         struct irq_service_init_data init_data;
1237         init_data.ctx = dc->ctx;
1238         pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1239         if (!pool->base.irqs)
1240             goto res_create_fail;
1241     }
1242 
1243     for (i = 0; i < pool->base.pipe_count; i++) {
1244         pool->base.timing_generators[i] = dce80_timing_generator_create(
1245                 ctx, i, &dce80_tg_offsets[i]);
1246         if (pool->base.timing_generators[i] == NULL) {
1247             BREAK_TO_DEBUGGER();
1248             dm_error("DC: failed to create tg!\n");
1249             goto res_create_fail;
1250         }
1251 
1252         pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1253         if (pool->base.mis[i] == NULL) {
1254             BREAK_TO_DEBUGGER();
1255             dm_error("DC: failed to create memory input!\n");
1256             goto res_create_fail;
1257         }
1258 
1259         pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1260         if (pool->base.ipps[i] == NULL) {
1261             BREAK_TO_DEBUGGER();
1262             dm_error("DC: failed to create input pixel processor!\n");
1263             goto res_create_fail;
1264         }
1265 
1266         pool->base.transforms[i] = dce80_transform_create(ctx, i);
1267         if (pool->base.transforms[i] == NULL) {
1268             BREAK_TO_DEBUGGER();
1269             dm_error("DC: failed to create transform!\n");
1270             goto res_create_fail;
1271         }
1272 
1273         pool->base.opps[i] = dce80_opp_create(ctx, i);
1274         if (pool->base.opps[i] == NULL) {
1275             BREAK_TO_DEBUGGER();
1276             dm_error("DC: failed to create output pixel processor!\n");
1277             goto res_create_fail;
1278         }
1279     }
1280 
1281     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1282         pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1283         if (pool->base.engines[i] == NULL) {
1284             BREAK_TO_DEBUGGER();
1285             dm_error(
1286                 "DC:failed to create aux engine!!\n");
1287             goto res_create_fail;
1288         }
1289         pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1290         if (pool->base.hw_i2cs[i] == NULL) {
1291             BREAK_TO_DEBUGGER();
1292             dm_error(
1293                 "DC:failed to create i2c engine!!\n");
1294             goto res_create_fail;
1295         }
1296         pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1297         if (pool->base.sw_i2cs[i] == NULL) {
1298             BREAK_TO_DEBUGGER();
1299             dm_error(
1300                 "DC:failed to create sw i2c!!\n");
1301             goto res_create_fail;
1302         }
1303     }
1304 
1305     dc->caps.max_planes =  pool->base.pipe_count;
1306 
1307     for (i = 0; i < dc->caps.max_planes; ++i)
1308         dc->caps.planes[i] = plane_cap;
1309 
1310     dc->caps.disable_dp_clk_share = true;
1311 
1312     if (!resource_construct(num_virtual_links, dc, &pool->base,
1313             &res_create_funcs))
1314         goto res_create_fail;
1315 
1316     /* Create hardware sequencer */
1317     dce80_hw_sequencer_construct(dc);
1318 
1319     return true;
1320 
1321 res_create_fail:
1322     dce80_resource_destruct(pool);
1323     return false;
1324 }
1325 
1326 struct resource_pool *dce81_create_resource_pool(
1327     uint8_t num_virtual_links,
1328     struct dc *dc)
1329 {
1330     struct dce110_resource_pool *pool =
1331         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1332 
1333     if (!pool)
1334         return NULL;
1335 
1336     if (dce81_construct(num_virtual_links, dc, pool))
1337         return &pool->base;
1338 
1339     BREAK_TO_DEBUGGER();
1340     return NULL;
1341 }
1342 
1343 static bool dce83_construct(
1344     uint8_t num_virtual_links,
1345     struct dc *dc,
1346     struct dce110_resource_pool *pool)
1347 {
1348     unsigned int i;
1349     struct dc_context *ctx = dc->ctx;
1350     struct dc_bios *bp;
1351 
1352     ctx->dc_bios->regs = &bios_regs;
1353 
1354     pool->base.res_cap = &res_cap_83;
1355     pool->base.funcs = &dce80_res_pool_funcs;
1356 
1357 
1358     /*************************************************
1359      *  Resource + asic cap harcoding                *
1360      *************************************************/
1361     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1362     pool->base.pipe_count = res_cap_83.num_timing_generator;
1363     pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1364     dc->caps.max_downscale_ratio = 200;
1365     dc->caps.i2c_speed_in_khz = 40;
1366     dc->caps.i2c_speed_in_khz_hdcp = 40;
1367     dc->caps.max_cursor_size = 128;
1368     dc->caps.min_horizontal_blanking_period = 80;
1369     dc->caps.is_apu = true;
1370 
1371     /*************************************************
1372      *  Create resources                             *
1373      *************************************************/
1374 
1375     bp = ctx->dc_bios;
1376 
1377     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1378         pool->base.dp_clock_source =
1379                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1380 
1381         pool->base.clock_sources[0] =
1382                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1383         pool->base.clock_sources[1] =
1384                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1385         pool->base.clk_src_count = 2;
1386 
1387     } else {
1388         pool->base.dp_clock_source =
1389                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1390 
1391         pool->base.clock_sources[0] =
1392                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1393         pool->base.clk_src_count = 1;
1394     }
1395 
1396     if (pool->base.dp_clock_source == NULL) {
1397         dm_error("DC: failed to create dp clock source!\n");
1398         BREAK_TO_DEBUGGER();
1399         goto res_create_fail;
1400     }
1401 
1402     for (i = 0; i < pool->base.clk_src_count; i++) {
1403         if (pool->base.clock_sources[i] == NULL) {
1404             dm_error("DC: failed to create clock sources!\n");
1405             BREAK_TO_DEBUGGER();
1406             goto res_create_fail;
1407         }
1408     }
1409 
1410     pool->base.dmcu = dce_dmcu_create(ctx,
1411             &dmcu_regs,
1412             &dmcu_shift,
1413             &dmcu_mask);
1414     if (pool->base.dmcu == NULL) {
1415         dm_error("DC: failed to create dmcu!\n");
1416         BREAK_TO_DEBUGGER();
1417         goto res_create_fail;
1418     }
1419 
1420     pool->base.abm = dce_abm_create(ctx,
1421             &abm_regs,
1422             &abm_shift,
1423             &abm_mask);
1424     if (pool->base.abm == NULL) {
1425         dm_error("DC: failed to create abm!\n");
1426         BREAK_TO_DEBUGGER();
1427         goto res_create_fail;
1428     }
1429 
1430     {
1431         struct irq_service_init_data init_data;
1432         init_data.ctx = dc->ctx;
1433         pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1434         if (!pool->base.irqs)
1435             goto res_create_fail;
1436     }
1437 
1438     for (i = 0; i < pool->base.pipe_count; i++) {
1439         pool->base.timing_generators[i] = dce80_timing_generator_create(
1440                 ctx, i, &dce80_tg_offsets[i]);
1441         if (pool->base.timing_generators[i] == NULL) {
1442             BREAK_TO_DEBUGGER();
1443             dm_error("DC: failed to create tg!\n");
1444             goto res_create_fail;
1445         }
1446 
1447         pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1448         if (pool->base.mis[i] == NULL) {
1449             BREAK_TO_DEBUGGER();
1450             dm_error("DC: failed to create memory input!\n");
1451             goto res_create_fail;
1452         }
1453 
1454         pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1455         if (pool->base.ipps[i] == NULL) {
1456             BREAK_TO_DEBUGGER();
1457             dm_error("DC: failed to create input pixel processor!\n");
1458             goto res_create_fail;
1459         }
1460 
1461         pool->base.transforms[i] = dce80_transform_create(ctx, i);
1462         if (pool->base.transforms[i] == NULL) {
1463             BREAK_TO_DEBUGGER();
1464             dm_error("DC: failed to create transform!\n");
1465             goto res_create_fail;
1466         }
1467 
1468         pool->base.opps[i] = dce80_opp_create(ctx, i);
1469         if (pool->base.opps[i] == NULL) {
1470             BREAK_TO_DEBUGGER();
1471             dm_error("DC: failed to create output pixel processor!\n");
1472             goto res_create_fail;
1473         }
1474     }
1475 
1476     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1477         pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1478         if (pool->base.engines[i] == NULL) {
1479             BREAK_TO_DEBUGGER();
1480             dm_error(
1481                 "DC:failed to create aux engine!!\n");
1482             goto res_create_fail;
1483         }
1484         pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1485         if (pool->base.hw_i2cs[i] == NULL) {
1486             BREAK_TO_DEBUGGER();
1487             dm_error(
1488                 "DC:failed to create i2c engine!!\n");
1489             goto res_create_fail;
1490         }
1491         pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1492         if (pool->base.sw_i2cs[i] == NULL) {
1493             BREAK_TO_DEBUGGER();
1494             dm_error(
1495                 "DC:failed to create sw i2c!!\n");
1496             goto res_create_fail;
1497         }
1498     }
1499 
1500     dc->caps.max_planes =  pool->base.pipe_count;
1501 
1502     for (i = 0; i < dc->caps.max_planes; ++i)
1503         dc->caps.planes[i] = plane_cap;
1504 
1505     dc->caps.disable_dp_clk_share = true;
1506 
1507     if (!resource_construct(num_virtual_links, dc, &pool->base,
1508             &res_create_funcs))
1509         goto res_create_fail;
1510 
1511     /* Create hardware sequencer */
1512     dce80_hw_sequencer_construct(dc);
1513 
1514     return true;
1515 
1516 res_create_fail:
1517     dce80_resource_destruct(pool);
1518     return false;
1519 }
1520 
1521 struct resource_pool *dce83_create_resource_pool(
1522     uint8_t num_virtual_links,
1523     struct dc *dc)
1524 {
1525     struct dce110_resource_pool *pool =
1526         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1527 
1528     if (!pool)
1529         return NULL;
1530 
1531     if (dce83_construct(num_virtual_links, dc, pool))
1532         return &pool->base;
1533 
1534     BREAK_TO_DEBUGGER();
1535     return NULL;
1536 }
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