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0001 /*
0002  * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include <linux/slab.h>
0027 
0028 #include "dce/dce_6_0_d.h"
0029 #include "dce/dce_6_0_sh_mask.h"
0030 
0031 #include "dm_services.h"
0032 
0033 #include "link_encoder.h"
0034 #include "stream_encoder.h"
0035 
0036 #include "resource.h"
0037 #include "include/irq_service_interface.h"
0038 #include "irq/dce60/irq_service_dce60.h"
0039 #include "dce110/dce110_timing_generator.h"
0040 #include "dce110/dce110_resource.h"
0041 #include "dce60/dce60_timing_generator.h"
0042 #include "dce/dce_mem_input.h"
0043 #include "dce/dce_link_encoder.h"
0044 #include "dce/dce_stream_encoder.h"
0045 #include "dce/dce_ipp.h"
0046 #include "dce/dce_transform.h"
0047 #include "dce/dce_opp.h"
0048 #include "dce/dce_clock_source.h"
0049 #include "dce/dce_audio.h"
0050 #include "dce/dce_hwseq.h"
0051 #include "dce60/dce60_hw_sequencer.h"
0052 #include "dce100/dce100_resource.h"
0053 #include "dce/dce_panel_cntl.h"
0054 
0055 #include "reg_helper.h"
0056 
0057 #include "dce/dce_dmcu.h"
0058 #include "dce/dce_aux.h"
0059 #include "dce/dce_abm.h"
0060 #include "dce/dce_i2c.h"
0061 /* TODO remove this include */
0062 
0063 #include "dce60_resource.h"
0064 
0065 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
0066 #include "gmc/gmc_6_0_d.h"
0067 #include "gmc/gmc_6_0_sh_mask.h"
0068 #endif
0069 
0070 #ifndef mmDP_DPHY_INTERNAL_CTRL
0071 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
0072 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
0073 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
0074 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
0075 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
0076 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
0077 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
0078 #endif
0079 
0080 
0081 #ifndef mmBIOS_SCRATCH_2
0082     #define mmBIOS_SCRATCH_2 0x05CB
0083     #define mmBIOS_SCRATCH_3 0x05CC
0084     #define mmBIOS_SCRATCH_6 0x05CF
0085 #endif
0086 
0087 #ifndef mmDP_DPHY_FAST_TRAINING
0088     #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
0089     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
0090     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
0091     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
0092     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
0093     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
0094     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
0095 #endif
0096 
0097 
0098 #ifndef mmHPD_DC_HPD_CONTROL
0099     #define mmHPD_DC_HPD_CONTROL                            0x189A
0100     #define mmHPD0_DC_HPD_CONTROL                           0x189A
0101     #define mmHPD1_DC_HPD_CONTROL                           0x18A2
0102     #define mmHPD2_DC_HPD_CONTROL                           0x18AA
0103     #define mmHPD3_DC_HPD_CONTROL                           0x18B2
0104     #define mmHPD4_DC_HPD_CONTROL                           0x18BA
0105     #define mmHPD5_DC_HPD_CONTROL                           0x18C2
0106 #endif
0107 
0108 #define DCE11_DIG_FE_CNTL 0x4a00
0109 #define DCE11_DIG_BE_CNTL 0x4a47
0110 #define DCE11_DP_SEC 0x4ac3
0111 
0112 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
0113         {
0114             .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
0115             .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
0116             .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
0117                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0118         },
0119         {
0120             .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
0121             .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
0122             .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
0123                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0124         },
0125         {
0126             .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
0127             .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
0128             .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
0129                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0130         },
0131         {
0132             .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
0133             .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
0134             .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
0135                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0136         },
0137         {
0138             .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
0139             .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
0140             .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
0141                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0142         },
0143         {
0144             .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
0145             .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
0146             .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3
0147                     - mmDPG_PIPE_ARBITRATION_CONTROL3),
0148         }
0149 };
0150 
0151 /* set register offset */
0152 #define SR(reg_name)\
0153     .reg_name = mm ## reg_name
0154 
0155 /* set register offset with instance */
0156 #define SRI(reg_name, block, id)\
0157     .reg_name = mm ## block ## id ## _ ## reg_name
0158 
0159 #define ipp_regs(id)\
0160 [id] = {\
0161         IPP_COMMON_REG_LIST_DCE_BASE(id)\
0162 }
0163 
0164 static const struct dce_ipp_registers ipp_regs[] = {
0165         ipp_regs(0),
0166         ipp_regs(1),
0167         ipp_regs(2),
0168         ipp_regs(3),
0169         ipp_regs(4),
0170         ipp_regs(5)
0171 };
0172 
0173 static const struct dce_ipp_shift ipp_shift = {
0174         IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0175 };
0176 
0177 static const struct dce_ipp_mask ipp_mask = {
0178         IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0179 };
0180 
0181 #define transform_regs(id)\
0182 [id] = {\
0183         XFM_COMMON_REG_LIST_DCE60(id)\
0184 }
0185 
0186 static const struct dce_transform_registers xfm_regs[] = {
0187         transform_regs(0),
0188         transform_regs(1),
0189         transform_regs(2),
0190         transform_regs(3),
0191         transform_regs(4),
0192         transform_regs(5)
0193 };
0194 
0195 static const struct dce_transform_shift xfm_shift = {
0196         XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT)
0197 };
0198 
0199 static const struct dce_transform_mask xfm_mask = {
0200         XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)
0201 };
0202 
0203 #define aux_regs(id)\
0204 [id] = {\
0205     AUX_REG_LIST(id)\
0206 }
0207 
0208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
0209     aux_regs(0),
0210     aux_regs(1),
0211     aux_regs(2),
0212     aux_regs(3),
0213     aux_regs(4),
0214     aux_regs(5)
0215 };
0216 
0217 #define hpd_regs(id)\
0218 [id] = {\
0219     HPD_REG_LIST(id)\
0220 }
0221 
0222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
0223         hpd_regs(0),
0224         hpd_regs(1),
0225         hpd_regs(2),
0226         hpd_regs(3),
0227         hpd_regs(4),
0228         hpd_regs(5)
0229 };
0230 
0231 #define link_regs(id)\
0232 [id] = {\
0233     LE_DCE60_REG_LIST(id)\
0234 }
0235 
0236 static const struct dce110_link_enc_registers link_enc_regs[] = {
0237     link_regs(0),
0238     link_regs(1),
0239     link_regs(2),
0240     link_regs(3),
0241     link_regs(4),
0242     link_regs(5)
0243 };
0244 
0245 #define stream_enc_regs(id)\
0246 [id] = {\
0247     SE_COMMON_REG_LIST_DCE_BASE(id),\
0248     .AFMT_CNTL = 0,\
0249 }
0250 
0251 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
0252     stream_enc_regs(0),
0253     stream_enc_regs(1),
0254     stream_enc_regs(2),
0255     stream_enc_regs(3),
0256     stream_enc_regs(4),
0257     stream_enc_regs(5)
0258 };
0259 
0260 static const struct dce_stream_encoder_shift se_shift = {
0261         SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
0262 };
0263 
0264 static const struct dce_stream_encoder_mask se_mask = {
0265         SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
0266 };
0267 
0268 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0269     { DCE_PANEL_CNTL_REG_LIST() }
0270 };
0271 
0272 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0273     DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0274 };
0275 
0276 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0277     DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0278 };
0279 
0280 #define opp_regs(id)\
0281 [id] = {\
0282     OPP_DCE_60_REG_LIST(id),\
0283 }
0284 
0285 static const struct dce_opp_registers opp_regs[] = {
0286     opp_regs(0),
0287     opp_regs(1),
0288     opp_regs(2),
0289     opp_regs(3),
0290     opp_regs(4),
0291     opp_regs(5)
0292 };
0293 
0294 static const struct dce_opp_shift opp_shift = {
0295     OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT)
0296 };
0297 
0298 static const struct dce_opp_mask opp_mask = {
0299     OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)
0300 };
0301 
0302 static const struct dce110_aux_registers_shift aux_shift = {
0303     DCE10_AUX_MASK_SH_LIST(__SHIFT)
0304 };
0305 
0306 static const struct dce110_aux_registers_mask aux_mask = {
0307     DCE10_AUX_MASK_SH_LIST(_MASK)
0308 };
0309 
0310 #define aux_engine_regs(id)\
0311 [id] = {\
0312     AUX_COMMON_REG_LIST(id), \
0313     .AUX_RESET_MASK = 0 \
0314 }
0315 
0316 static const struct dce110_aux_registers aux_engine_regs[] = {
0317         aux_engine_regs(0),
0318         aux_engine_regs(1),
0319         aux_engine_regs(2),
0320         aux_engine_regs(3),
0321         aux_engine_regs(4),
0322         aux_engine_regs(5)
0323 };
0324 
0325 #define audio_regs(id)\
0326 [id] = {\
0327     AUD_COMMON_REG_LIST(id)\
0328 }
0329 
0330 static const struct dce_audio_registers audio_regs[] = {
0331     audio_regs(0),
0332     audio_regs(1),
0333     audio_regs(2),
0334     audio_regs(3),
0335     audio_regs(4),
0336     audio_regs(5),
0337 };
0338 
0339 static const struct dce_audio_shift audio_shift = {
0340         AUD_DCE60_MASK_SH_LIST(__SHIFT)
0341 };
0342 
0343 static const struct dce_audio_mask audio_mask = {
0344         AUD_DCE60_MASK_SH_LIST(_MASK)
0345 };
0346 
0347 #define clk_src_regs(id)\
0348 [id] = {\
0349     CS_COMMON_REG_LIST_DCE_80(id),\
0350 }
0351 
0352 
0353 static const struct dce110_clk_src_regs clk_src_regs[] = {
0354     clk_src_regs(0),
0355     clk_src_regs(1),
0356     clk_src_regs(2)
0357 };
0358 
0359 static const struct dce110_clk_src_shift cs_shift = {
0360         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0361 };
0362 
0363 static const struct dce110_clk_src_mask cs_mask = {
0364         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0365 };
0366 
0367 static const struct bios_registers bios_regs = {
0368     .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
0369     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
0370 };
0371 
0372 static const struct resource_caps res_cap = {
0373         .num_timing_generator = 6,
0374         .num_audio = 6,
0375         .num_stream_encoder = 6,
0376         .num_pll = 2,
0377         .num_ddc = 6,
0378 };
0379 
0380 static const struct resource_caps res_cap_61 = {
0381         .num_timing_generator = 4,
0382         .num_audio = 6,
0383         .num_stream_encoder = 6,
0384         .num_pll = 3,
0385         .num_ddc = 6,
0386 };
0387 
0388 static const struct resource_caps res_cap_64 = {
0389         .num_timing_generator = 2,
0390         .num_audio = 2,
0391         .num_stream_encoder = 2,
0392         .num_pll = 2,
0393         .num_ddc = 2,
0394 };
0395 
0396 static const struct dc_plane_cap plane_cap = {
0397     .type = DC_PLANE_TYPE_DCE_RGB,
0398 
0399     .pixel_format_support = {
0400             .argb8888 = true,
0401             .nv12 = false,
0402             .fp16 = false
0403     },
0404 
0405     .max_upscale_factor = {
0406             .argb8888 = 16000,
0407             .nv12 = 1,
0408             .fp16 = 1
0409     },
0410 
0411     .max_downscale_factor = {
0412             .argb8888 = 250,
0413             .nv12 = 1,
0414             .fp16 = 1
0415     }
0416 };
0417 
0418 static const struct dce_dmcu_registers dmcu_regs = {
0419         DMCU_DCE60_REG_LIST()
0420 };
0421 
0422 static const struct dce_dmcu_shift dmcu_shift = {
0423         DMCU_MASK_SH_LIST_DCE60(__SHIFT)
0424 };
0425 
0426 static const struct dce_dmcu_mask dmcu_mask = {
0427         DMCU_MASK_SH_LIST_DCE60(_MASK)
0428 };
0429 static const struct dce_abm_registers abm_regs = {
0430         ABM_DCE110_COMMON_REG_LIST()
0431 };
0432 
0433 static const struct dce_abm_shift abm_shift = {
0434         ABM_MASK_SH_LIST_DCE110(__SHIFT)
0435 };
0436 
0437 static const struct dce_abm_mask abm_mask = {
0438         ABM_MASK_SH_LIST_DCE110(_MASK)
0439 };
0440 
0441 #define CTX  ctx
0442 #define REG(reg) mm ## reg
0443 
0444 #ifndef mmCC_DC_HDMI_STRAPS
0445 #define mmCC_DC_HDMI_STRAPS 0x1918
0446 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
0447 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
0448 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
0449 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
0450 #endif
0451 
0452 static int map_transmitter_id_to_phy_instance(
0453     enum transmitter transmitter)
0454 {
0455     switch (transmitter) {
0456     case TRANSMITTER_UNIPHY_A:
0457         return 0;
0458     case TRANSMITTER_UNIPHY_B:
0459         return 1;
0460     case TRANSMITTER_UNIPHY_C:
0461         return 2;
0462     case TRANSMITTER_UNIPHY_D:
0463         return 3;
0464     case TRANSMITTER_UNIPHY_E:
0465         return 4;
0466     case TRANSMITTER_UNIPHY_F:
0467         return 5;
0468     case TRANSMITTER_UNIPHY_G:
0469         return 6;
0470     default:
0471         ASSERT(0);
0472         return 0;
0473     }
0474 }
0475 
0476 static void read_dce_straps(
0477     struct dc_context *ctx,
0478     struct resource_straps *straps)
0479 {
0480     REG_GET_2(CC_DC_HDMI_STRAPS,
0481             HDMI_DISABLE, &straps->hdmi_disable,
0482             AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
0483 
0484     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
0485 }
0486 
0487 static struct audio *create_audio(
0488         struct dc_context *ctx, unsigned int inst)
0489 {
0490     return dce60_audio_create(ctx, inst,
0491             &audio_regs[inst], &audio_shift, &audio_mask);
0492 }
0493 
0494 static struct timing_generator *dce60_timing_generator_create(
0495         struct dc_context *ctx,
0496         uint32_t instance,
0497         const struct dce110_timing_generator_offsets *offsets)
0498 {
0499     struct dce110_timing_generator *tg110 =
0500         kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
0501 
0502     if (!tg110)
0503         return NULL;
0504 
0505     dce60_timing_generator_construct(tg110, ctx, instance, offsets);
0506     return &tg110->base;
0507 }
0508 
0509 static struct output_pixel_processor *dce60_opp_create(
0510     struct dc_context *ctx,
0511     uint32_t inst)
0512 {
0513     struct dce110_opp *opp =
0514         kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
0515 
0516     if (!opp)
0517         return NULL;
0518 
0519     dce60_opp_construct(opp,
0520                  ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0521     return &opp->base;
0522 }
0523 
0524 static struct dce_aux *dce60_aux_engine_create(
0525     struct dc_context *ctx,
0526     uint32_t inst)
0527 {
0528     struct aux_engine_dce110 *aux_engine =
0529         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0530 
0531     if (!aux_engine)
0532         return NULL;
0533 
0534     dce110_aux_engine_construct(aux_engine, ctx, inst,
0535                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0536                     &aux_engine_regs[inst],
0537                     &aux_mask,
0538                     &aux_shift,
0539                     ctx->dc->caps.extended_aux_timeout_support);
0540 
0541     return &aux_engine->base;
0542 }
0543 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0544 
0545 static const struct dce_i2c_registers i2c_hw_regs[] = {
0546         i2c_inst_regs(1),
0547         i2c_inst_regs(2),
0548         i2c_inst_regs(3),
0549         i2c_inst_regs(4),
0550         i2c_inst_regs(5),
0551         i2c_inst_regs(6),
0552 };
0553 
0554 static const struct dce_i2c_shift i2c_shifts = {
0555         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0556 };
0557 
0558 static const struct dce_i2c_mask i2c_masks = {
0559         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0560 };
0561 
0562 static struct dce_i2c_hw *dce60_i2c_hw_create(
0563     struct dc_context *ctx,
0564     uint32_t inst)
0565 {
0566     struct dce_i2c_hw *dce_i2c_hw =
0567         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0568 
0569     if (!dce_i2c_hw)
0570         return NULL;
0571 
0572     dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0573                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0574 
0575     return dce_i2c_hw;
0576 }
0577 
0578 static struct dce_i2c_sw *dce60_i2c_sw_create(
0579     struct dc_context *ctx)
0580 {
0581     struct dce_i2c_sw *dce_i2c_sw =
0582         kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
0583 
0584     if (!dce_i2c_sw)
0585         return NULL;
0586 
0587     dce_i2c_sw_construct(dce_i2c_sw, ctx);
0588 
0589     return dce_i2c_sw;
0590 }
0591 static struct stream_encoder *dce60_stream_encoder_create(
0592     enum engine_id eng_id,
0593     struct dc_context *ctx)
0594 {
0595     struct dce110_stream_encoder *enc110 =
0596         kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
0597 
0598     if (!enc110)
0599         return NULL;
0600 
0601     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
0602                     &stream_enc_regs[eng_id],
0603                     &se_shift, &se_mask);
0604     return &enc110->base;
0605 }
0606 
0607 #define SRII(reg_name, block, id)\
0608     .reg_name[id] = mm ## block ## id ## _ ## reg_name
0609 
0610 static const struct dce_hwseq_registers hwseq_reg = {
0611         HWSEQ_DCE6_REG_LIST()
0612 };
0613 
0614 static const struct dce_hwseq_shift hwseq_shift = {
0615         HWSEQ_DCE6_MASK_SH_LIST(__SHIFT)
0616 };
0617 
0618 static const struct dce_hwseq_mask hwseq_mask = {
0619         HWSEQ_DCE6_MASK_SH_LIST(_MASK)
0620 };
0621 
0622 static struct dce_hwseq *dce60_hwseq_create(
0623     struct dc_context *ctx)
0624 {
0625     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0626 
0627     if (hws) {
0628         hws->ctx = ctx;
0629         hws->regs = &hwseq_reg;
0630         hws->shifts = &hwseq_shift;
0631         hws->masks = &hwseq_mask;
0632     }
0633     return hws;
0634 }
0635 
0636 static const struct resource_create_funcs res_create_funcs = {
0637     .read_dce_straps = read_dce_straps,
0638     .create_audio = create_audio,
0639     .create_stream_encoder = dce60_stream_encoder_create,
0640     .create_hwseq = dce60_hwseq_create,
0641 };
0642 
0643 #define mi_inst_regs(id) { \
0644     MI_DCE6_REG_LIST(id), \
0645     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
0646 }
0647 static const struct dce_mem_input_registers mi_regs[] = {
0648         mi_inst_regs(0),
0649         mi_inst_regs(1),
0650         mi_inst_regs(2),
0651         mi_inst_regs(3),
0652         mi_inst_regs(4),
0653         mi_inst_regs(5),
0654 };
0655 
0656 static const struct dce_mem_input_shift mi_shifts = {
0657         MI_DCE6_MASK_SH_LIST(__SHIFT),
0658         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
0659 };
0660 
0661 static const struct dce_mem_input_mask mi_masks = {
0662         MI_DCE6_MASK_SH_LIST(_MASK),
0663         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
0664 };
0665 
0666 static struct mem_input *dce60_mem_input_create(
0667     struct dc_context *ctx,
0668     uint32_t inst)
0669 {
0670     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
0671                            GFP_KERNEL);
0672 
0673     if (!dce_mi) {
0674         BREAK_TO_DEBUGGER();
0675         return NULL;
0676     }
0677 
0678     dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
0679     dce_mi->wa.single_head_rdreq_dmif_limit = 2;
0680     return &dce_mi->base;
0681 }
0682 
0683 static void dce60_transform_destroy(struct transform **xfm)
0684 {
0685     kfree(TO_DCE_TRANSFORM(*xfm));
0686     *xfm = NULL;
0687 }
0688 
0689 static struct transform *dce60_transform_create(
0690     struct dc_context *ctx,
0691     uint32_t inst)
0692 {
0693     struct dce_transform *transform =
0694         kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
0695 
0696     if (!transform)
0697         return NULL;
0698 
0699     dce60_transform_construct(transform, ctx, inst,
0700                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
0701     transform->prescaler_on = false;
0702     return &transform->base;
0703 }
0704 
0705 static const struct encoder_feature_support link_enc_feature = {
0706         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0707         .max_hdmi_pixel_clock = 297000,
0708         .flags.bits.IS_HBR2_CAPABLE = true,
0709         .flags.bits.IS_TPS3_CAPABLE = true
0710 };
0711 
0712 static struct link_encoder *dce60_link_encoder_create(
0713     struct dc_context *ctx,
0714     const struct encoder_init_data *enc_init_data)
0715 {
0716     struct dce110_link_encoder *enc110 =
0717         kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
0718     int link_regs_id;
0719 
0720     if (!enc110)
0721         return NULL;
0722 
0723     link_regs_id =
0724         map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
0725 
0726     dce60_link_encoder_construct(enc110,
0727                       enc_init_data,
0728                       &link_enc_feature,
0729                       &link_enc_regs[link_regs_id],
0730                       &link_enc_aux_regs[enc_init_data->channel - 1],
0731                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
0732     return &enc110->base;
0733 }
0734 
0735 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0736 {
0737     struct dce_panel_cntl *panel_cntl =
0738         kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0739 
0740     if (!panel_cntl)
0741         return NULL;
0742 
0743     dce_panel_cntl_construct(panel_cntl,
0744             init_data,
0745             &panel_cntl_regs[init_data->inst],
0746             &panel_cntl_shift,
0747             &panel_cntl_mask);
0748 
0749     return &panel_cntl->base;
0750 }
0751 
0752 static struct clock_source *dce60_clock_source_create(
0753     struct dc_context *ctx,
0754     struct dc_bios *bios,
0755     enum clock_source_id id,
0756     const struct dce110_clk_src_regs *regs,
0757     bool dp_clk_src)
0758 {
0759     struct dce110_clk_src *clk_src =
0760         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0761 
0762     if (!clk_src)
0763         return NULL;
0764 
0765     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
0766             regs, &cs_shift, &cs_mask)) {
0767         clk_src->base.dp_clk_src = dp_clk_src;
0768         return &clk_src->base;
0769     }
0770 
0771     kfree(clk_src);
0772     BREAK_TO_DEBUGGER();
0773     return NULL;
0774 }
0775 
0776 static void dce60_clock_source_destroy(struct clock_source **clk_src)
0777 {
0778     kfree(TO_DCE110_CLK_SRC(*clk_src));
0779     *clk_src = NULL;
0780 }
0781 
0782 static struct input_pixel_processor *dce60_ipp_create(
0783     struct dc_context *ctx, uint32_t inst)
0784 {
0785     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
0786 
0787     if (!ipp) {
0788         BREAK_TO_DEBUGGER();
0789         return NULL;
0790     }
0791 
0792     dce60_ipp_construct(ipp, ctx, inst,
0793             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0794     return &ipp->base;
0795 }
0796 
0797 static void dce60_resource_destruct(struct dce110_resource_pool *pool)
0798 {
0799     unsigned int i;
0800 
0801     for (i = 0; i < pool->base.pipe_count; i++) {
0802         if (pool->base.opps[i] != NULL)
0803             dce110_opp_destroy(&pool->base.opps[i]);
0804 
0805         if (pool->base.transforms[i] != NULL)
0806             dce60_transform_destroy(&pool->base.transforms[i]);
0807 
0808         if (pool->base.ipps[i] != NULL)
0809             dce_ipp_destroy(&pool->base.ipps[i]);
0810 
0811         if (pool->base.mis[i] != NULL) {
0812             kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
0813             pool->base.mis[i] = NULL;
0814         }
0815 
0816         if (pool->base.timing_generators[i] != NULL)    {
0817             kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
0818             pool->base.timing_generators[i] = NULL;
0819         }
0820     }
0821 
0822     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
0823         if (pool->base.engines[i] != NULL)
0824             dce110_engine_destroy(&pool->base.engines[i]);
0825         if (pool->base.hw_i2cs[i] != NULL) {
0826             kfree(pool->base.hw_i2cs[i]);
0827             pool->base.hw_i2cs[i] = NULL;
0828         }
0829         if (pool->base.sw_i2cs[i] != NULL) {
0830             kfree(pool->base.sw_i2cs[i]);
0831             pool->base.sw_i2cs[i] = NULL;
0832         }
0833     }
0834 
0835     for (i = 0; i < pool->base.stream_enc_count; i++) {
0836         if (pool->base.stream_enc[i] != NULL)
0837             kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0838     }
0839 
0840     for (i = 0; i < pool->base.clk_src_count; i++) {
0841         if (pool->base.clock_sources[i] != NULL) {
0842             dce60_clock_source_destroy(&pool->base.clock_sources[i]);
0843         }
0844     }
0845 
0846     if (pool->base.abm != NULL)
0847             dce_abm_destroy(&pool->base.abm);
0848 
0849     if (pool->base.dmcu != NULL)
0850             dce_dmcu_destroy(&pool->base.dmcu);
0851 
0852     if (pool->base.dp_clock_source != NULL)
0853         dce60_clock_source_destroy(&pool->base.dp_clock_source);
0854 
0855     for (i = 0; i < pool->base.audio_count; i++)    {
0856         if (pool->base.audios[i] != NULL) {
0857             dce_aud_destroy(&pool->base.audios[i]);
0858         }
0859     }
0860 
0861     if (pool->base.irqs != NULL) {
0862         dal_irq_service_destroy(&pool->base.irqs);
0863     }
0864 }
0865 
0866 static bool dce60_validate_bandwidth(
0867     struct dc *dc,
0868     struct dc_state *context,
0869     bool fast_validate)
0870 {
0871     int i;
0872     bool at_least_one_pipe = false;
0873 
0874     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0875         if (context->res_ctx.pipe_ctx[i].stream)
0876             at_least_one_pipe = true;
0877     }
0878 
0879     if (at_least_one_pipe) {
0880         /* TODO implement when needed but for now hardcode max value*/
0881         context->bw_ctx.bw.dce.dispclk_khz = 681000;
0882         context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
0883     } else {
0884         context->bw_ctx.bw.dce.dispclk_khz = 0;
0885         context->bw_ctx.bw.dce.yclk_khz = 0;
0886     }
0887 
0888     return true;
0889 }
0890 
0891 static bool dce60_validate_surface_sets(
0892         struct dc_state *context)
0893 {
0894     int i;
0895 
0896     for (i = 0; i < context->stream_count; i++) {
0897         if (context->stream_status[i].plane_count == 0)
0898             continue;
0899 
0900         if (context->stream_status[i].plane_count > 1)
0901             return false;
0902 
0903         if (context->stream_status[i].plane_states[0]->format
0904                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
0905             return false;
0906     }
0907 
0908     return true;
0909 }
0910 
0911 static enum dc_status dce60_validate_global(
0912         struct dc *dc,
0913         struct dc_state *context)
0914 {
0915     if (!dce60_validate_surface_sets(context))
0916         return DC_FAIL_SURFACE_VALIDATE;
0917 
0918     return DC_OK;
0919 }
0920 
0921 static void dce60_destroy_resource_pool(struct resource_pool **pool)
0922 {
0923     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
0924 
0925     dce60_resource_destruct(dce110_pool);
0926     kfree(dce110_pool);
0927     *pool = NULL;
0928 }
0929 
0930 static const struct resource_funcs dce60_res_pool_funcs = {
0931     .destroy = dce60_destroy_resource_pool,
0932     .link_enc_create = dce60_link_encoder_create,
0933     .panel_cntl_create = dce60_panel_cntl_create,
0934     .validate_bandwidth = dce60_validate_bandwidth,
0935     .validate_plane = dce100_validate_plane,
0936     .add_stream_to_ctx = dce100_add_stream_to_ctx,
0937     .validate_global = dce60_validate_global,
0938     .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
0939 };
0940 
0941 static bool dce60_construct(
0942     uint8_t num_virtual_links,
0943     struct dc *dc,
0944     struct dce110_resource_pool *pool)
0945 {
0946     unsigned int i;
0947     struct dc_context *ctx = dc->ctx;
0948     struct dc_bios *bp;
0949 
0950     ctx->dc_bios->regs = &bios_regs;
0951 
0952     pool->base.res_cap = &res_cap;
0953     pool->base.funcs = &dce60_res_pool_funcs;
0954 
0955 
0956     /*************************************************
0957      *  Resource + asic cap harcoding                *
0958      *************************************************/
0959     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
0960     pool->base.pipe_count = res_cap.num_timing_generator;
0961     pool->base.timing_generator_count = res_cap.num_timing_generator;
0962     dc->caps.max_downscale_ratio = 200;
0963     dc->caps.i2c_speed_in_khz = 40;
0964     dc->caps.max_cursor_size = 64;
0965     dc->caps.dual_link_dvi = true;
0966     dc->caps.extended_aux_timeout_support = false;
0967 
0968     /*************************************************
0969      *  Create resources                             *
0970      *************************************************/
0971 
0972     bp = ctx->dc_bios;
0973 
0974     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
0975         pool->base.dp_clock_source =
0976                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
0977 
0978         pool->base.clock_sources[0] =
0979                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
0980         pool->base.clock_sources[1] =
0981                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
0982         pool->base.clk_src_count = 2;
0983 
0984     } else {
0985         pool->base.dp_clock_source =
0986                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
0987 
0988         pool->base.clock_sources[0] =
0989                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
0990         pool->base.clk_src_count = 1;
0991     }
0992 
0993     if (pool->base.dp_clock_source == NULL) {
0994         dm_error("DC: failed to create dp clock source!\n");
0995         BREAK_TO_DEBUGGER();
0996         goto res_create_fail;
0997     }
0998 
0999     for (i = 0; i < pool->base.clk_src_count; i++) {
1000         if (pool->base.clock_sources[i] == NULL) {
1001             dm_error("DC: failed to create clock sources!\n");
1002             BREAK_TO_DEBUGGER();
1003             goto res_create_fail;
1004         }
1005     }
1006 
1007     pool->base.dmcu = dce_dmcu_create(ctx,
1008             &dmcu_regs,
1009             &dmcu_shift,
1010             &dmcu_mask);
1011     if (pool->base.dmcu == NULL) {
1012         dm_error("DC: failed to create dmcu!\n");
1013         BREAK_TO_DEBUGGER();
1014         goto res_create_fail;
1015     }
1016 
1017     pool->base.abm = dce_abm_create(ctx,
1018             &abm_regs,
1019             &abm_shift,
1020             &abm_mask);
1021     if (pool->base.abm == NULL) {
1022         dm_error("DC: failed to create abm!\n");
1023         BREAK_TO_DEBUGGER();
1024         goto res_create_fail;
1025     }
1026 
1027     {
1028         struct irq_service_init_data init_data;
1029         init_data.ctx = dc->ctx;
1030         pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1031         if (!pool->base.irqs)
1032             goto res_create_fail;
1033     }
1034 
1035     for (i = 0; i < pool->base.pipe_count; i++) {
1036         pool->base.timing_generators[i] = dce60_timing_generator_create(
1037                 ctx, i, &dce60_tg_offsets[i]);
1038         if (pool->base.timing_generators[i] == NULL) {
1039             BREAK_TO_DEBUGGER();
1040             dm_error("DC: failed to create tg!\n");
1041             goto res_create_fail;
1042         }
1043 
1044         pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1045         if (pool->base.mis[i] == NULL) {
1046             BREAK_TO_DEBUGGER();
1047             dm_error("DC: failed to create memory input!\n");
1048             goto res_create_fail;
1049         }
1050 
1051         pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1052         if (pool->base.ipps[i] == NULL) {
1053             BREAK_TO_DEBUGGER();
1054             dm_error("DC: failed to create input pixel processor!\n");
1055             goto res_create_fail;
1056         }
1057 
1058         pool->base.transforms[i] = dce60_transform_create(ctx, i);
1059         if (pool->base.transforms[i] == NULL) {
1060             BREAK_TO_DEBUGGER();
1061             dm_error("DC: failed to create transform!\n");
1062             goto res_create_fail;
1063         }
1064 
1065         pool->base.opps[i] = dce60_opp_create(ctx, i);
1066         if (pool->base.opps[i] == NULL) {
1067             BREAK_TO_DEBUGGER();
1068             dm_error("DC: failed to create output pixel processor!\n");
1069             goto res_create_fail;
1070         }
1071     }
1072 
1073     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1074         pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1075         if (pool->base.engines[i] == NULL) {
1076             BREAK_TO_DEBUGGER();
1077             dm_error(
1078                 "DC:failed to create aux engine!!\n");
1079             goto res_create_fail;
1080         }
1081         pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1082         if (pool->base.hw_i2cs[i] == NULL) {
1083             BREAK_TO_DEBUGGER();
1084             dm_error(
1085                 "DC:failed to create i2c engine!!\n");
1086             goto res_create_fail;
1087         }
1088         pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1089         if (pool->base.sw_i2cs[i] == NULL) {
1090             BREAK_TO_DEBUGGER();
1091             dm_error(
1092                 "DC:failed to create sw i2c!!\n");
1093             goto res_create_fail;
1094         }
1095     }
1096 
1097     dc->caps.max_planes =  pool->base.pipe_count;
1098 
1099     for (i = 0; i < dc->caps.max_planes; ++i)
1100         dc->caps.planes[i] = plane_cap;
1101 
1102     dc->caps.disable_dp_clk_share = true;
1103 
1104     if (!resource_construct(num_virtual_links, dc, &pool->base,
1105             &res_create_funcs))
1106         goto res_create_fail;
1107 
1108     /* Create hardware sequencer */
1109     dce60_hw_sequencer_construct(dc);
1110 
1111     return true;
1112 
1113 res_create_fail:
1114     dce60_resource_destruct(pool);
1115     return false;
1116 }
1117 
1118 struct resource_pool *dce60_create_resource_pool(
1119     uint8_t num_virtual_links,
1120     struct dc *dc)
1121 {
1122     struct dce110_resource_pool *pool =
1123         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1124 
1125     if (!pool)
1126         return NULL;
1127 
1128     if (dce60_construct(num_virtual_links, dc, pool))
1129         return &pool->base;
1130 
1131     BREAK_TO_DEBUGGER();
1132     return NULL;
1133 }
1134 
1135 static bool dce61_construct(
1136     uint8_t num_virtual_links,
1137     struct dc *dc,
1138     struct dce110_resource_pool *pool)
1139 {
1140     unsigned int i;
1141     struct dc_context *ctx = dc->ctx;
1142     struct dc_bios *bp;
1143 
1144     ctx->dc_bios->regs = &bios_regs;
1145 
1146     pool->base.res_cap = &res_cap_61;
1147     pool->base.funcs = &dce60_res_pool_funcs;
1148 
1149 
1150     /*************************************************
1151      *  Resource + asic cap harcoding                *
1152      *************************************************/
1153     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1154     pool->base.pipe_count = res_cap_61.num_timing_generator;
1155     pool->base.timing_generator_count = res_cap_61.num_timing_generator;
1156     dc->caps.max_downscale_ratio = 200;
1157     dc->caps.i2c_speed_in_khz = 40;
1158     dc->caps.max_cursor_size = 64;
1159     dc->caps.is_apu = true;
1160 
1161     /*************************************************
1162      *  Create resources                             *
1163      *************************************************/
1164 
1165     bp = ctx->dc_bios;
1166 
1167     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1168         pool->base.dp_clock_source =
1169                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1170 
1171         pool->base.clock_sources[0] =
1172                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1173         pool->base.clock_sources[1] =
1174                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1175         pool->base.clock_sources[2] =
1176                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1177         pool->base.clk_src_count = 3;
1178 
1179     } else {
1180         pool->base.dp_clock_source =
1181                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1182 
1183         pool->base.clock_sources[0] =
1184                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1185         pool->base.clock_sources[1] =
1186                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1187         pool->base.clk_src_count = 2;
1188     }
1189 
1190     if (pool->base.dp_clock_source == NULL) {
1191         dm_error("DC: failed to create dp clock source!\n");
1192         BREAK_TO_DEBUGGER();
1193         goto res_create_fail;
1194     }
1195 
1196     for (i = 0; i < pool->base.clk_src_count; i++) {
1197         if (pool->base.clock_sources[i] == NULL) {
1198             dm_error("DC: failed to create clock sources!\n");
1199             BREAK_TO_DEBUGGER();
1200             goto res_create_fail;
1201         }
1202     }
1203 
1204     pool->base.dmcu = dce_dmcu_create(ctx,
1205             &dmcu_regs,
1206             &dmcu_shift,
1207             &dmcu_mask);
1208     if (pool->base.dmcu == NULL) {
1209         dm_error("DC: failed to create dmcu!\n");
1210         BREAK_TO_DEBUGGER();
1211         goto res_create_fail;
1212     }
1213 
1214     pool->base.abm = dce_abm_create(ctx,
1215             &abm_regs,
1216             &abm_shift,
1217             &abm_mask);
1218     if (pool->base.abm == NULL) {
1219         dm_error("DC: failed to create abm!\n");
1220         BREAK_TO_DEBUGGER();
1221         goto res_create_fail;
1222     }
1223 
1224     {
1225         struct irq_service_init_data init_data;
1226         init_data.ctx = dc->ctx;
1227         pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1228         if (!pool->base.irqs)
1229             goto res_create_fail;
1230     }
1231 
1232     for (i = 0; i < pool->base.pipe_count; i++) {
1233         pool->base.timing_generators[i] = dce60_timing_generator_create(
1234                 ctx, i, &dce60_tg_offsets[i]);
1235         if (pool->base.timing_generators[i] == NULL) {
1236             BREAK_TO_DEBUGGER();
1237             dm_error("DC: failed to create tg!\n");
1238             goto res_create_fail;
1239         }
1240 
1241         pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1242         if (pool->base.mis[i] == NULL) {
1243             BREAK_TO_DEBUGGER();
1244             dm_error("DC: failed to create memory input!\n");
1245             goto res_create_fail;
1246         }
1247 
1248         pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1249         if (pool->base.ipps[i] == NULL) {
1250             BREAK_TO_DEBUGGER();
1251             dm_error("DC: failed to create input pixel processor!\n");
1252             goto res_create_fail;
1253         }
1254 
1255         pool->base.transforms[i] = dce60_transform_create(ctx, i);
1256         if (pool->base.transforms[i] == NULL) {
1257             BREAK_TO_DEBUGGER();
1258             dm_error("DC: failed to create transform!\n");
1259             goto res_create_fail;
1260         }
1261 
1262         pool->base.opps[i] = dce60_opp_create(ctx, i);
1263         if (pool->base.opps[i] == NULL) {
1264             BREAK_TO_DEBUGGER();
1265             dm_error("DC: failed to create output pixel processor!\n");
1266             goto res_create_fail;
1267         }
1268     }
1269 
1270     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1271         pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1272         if (pool->base.engines[i] == NULL) {
1273             BREAK_TO_DEBUGGER();
1274             dm_error(
1275                 "DC:failed to create aux engine!!\n");
1276             goto res_create_fail;
1277         }
1278         pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1279         if (pool->base.hw_i2cs[i] == NULL) {
1280             BREAK_TO_DEBUGGER();
1281             dm_error(
1282                 "DC:failed to create i2c engine!!\n");
1283             goto res_create_fail;
1284         }
1285         pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1286         if (pool->base.sw_i2cs[i] == NULL) {
1287             BREAK_TO_DEBUGGER();
1288             dm_error(
1289                 "DC:failed to create sw i2c!!\n");
1290             goto res_create_fail;
1291         }
1292     }
1293 
1294     dc->caps.max_planes =  pool->base.pipe_count;
1295 
1296     for (i = 0; i < dc->caps.max_planes; ++i)
1297         dc->caps.planes[i] = plane_cap;
1298 
1299     dc->caps.disable_dp_clk_share = true;
1300 
1301     if (!resource_construct(num_virtual_links, dc, &pool->base,
1302             &res_create_funcs))
1303         goto res_create_fail;
1304 
1305     /* Create hardware sequencer */
1306     dce60_hw_sequencer_construct(dc);
1307 
1308     return true;
1309 
1310 res_create_fail:
1311     dce60_resource_destruct(pool);
1312     return false;
1313 }
1314 
1315 struct resource_pool *dce61_create_resource_pool(
1316     uint8_t num_virtual_links,
1317     struct dc *dc)
1318 {
1319     struct dce110_resource_pool *pool =
1320         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1321 
1322     if (!pool)
1323         return NULL;
1324 
1325     if (dce61_construct(num_virtual_links, dc, pool))
1326         return &pool->base;
1327 
1328     BREAK_TO_DEBUGGER();
1329     return NULL;
1330 }
1331 
1332 static bool dce64_construct(
1333     uint8_t num_virtual_links,
1334     struct dc *dc,
1335     struct dce110_resource_pool *pool)
1336 {
1337     unsigned int i;
1338     struct dc_context *ctx = dc->ctx;
1339     struct dc_bios *bp;
1340 
1341     ctx->dc_bios->regs = &bios_regs;
1342 
1343     pool->base.res_cap = &res_cap_64;
1344     pool->base.funcs = &dce60_res_pool_funcs;
1345 
1346 
1347     /*************************************************
1348      *  Resource + asic cap harcoding                *
1349      *************************************************/
1350     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1351     pool->base.pipe_count = res_cap_64.num_timing_generator;
1352     pool->base.timing_generator_count = res_cap_64.num_timing_generator;
1353     dc->caps.max_downscale_ratio = 200;
1354     dc->caps.i2c_speed_in_khz = 40;
1355     dc->caps.max_cursor_size = 64;
1356     dc->caps.is_apu = true;
1357 
1358     /*************************************************
1359      *  Create resources                             *
1360      *************************************************/
1361 
1362     bp = ctx->dc_bios;
1363 
1364     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1365         pool->base.dp_clock_source =
1366                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1367 
1368         pool->base.clock_sources[0] =
1369                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1370         pool->base.clock_sources[1] =
1371                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1372         pool->base.clk_src_count = 2;
1373 
1374     } else {
1375         pool->base.dp_clock_source =
1376                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1377 
1378         pool->base.clock_sources[0] =
1379                 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1380         pool->base.clk_src_count = 1;
1381     }
1382 
1383     if (pool->base.dp_clock_source == NULL) {
1384         dm_error("DC: failed to create dp clock source!\n");
1385         BREAK_TO_DEBUGGER();
1386         goto res_create_fail;
1387     }
1388 
1389     for (i = 0; i < pool->base.clk_src_count; i++) {
1390         if (pool->base.clock_sources[i] == NULL) {
1391             dm_error("DC: failed to create clock sources!\n");
1392             BREAK_TO_DEBUGGER();
1393             goto res_create_fail;
1394         }
1395     }
1396 
1397     pool->base.dmcu = dce_dmcu_create(ctx,
1398             &dmcu_regs,
1399             &dmcu_shift,
1400             &dmcu_mask);
1401     if (pool->base.dmcu == NULL) {
1402         dm_error("DC: failed to create dmcu!\n");
1403         BREAK_TO_DEBUGGER();
1404         goto res_create_fail;
1405     }
1406 
1407     pool->base.abm = dce_abm_create(ctx,
1408             &abm_regs,
1409             &abm_shift,
1410             &abm_mask);
1411     if (pool->base.abm == NULL) {
1412         dm_error("DC: failed to create abm!\n");
1413         BREAK_TO_DEBUGGER();
1414         goto res_create_fail;
1415     }
1416 
1417     {
1418         struct irq_service_init_data init_data;
1419         init_data.ctx = dc->ctx;
1420         pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1421         if (!pool->base.irqs)
1422             goto res_create_fail;
1423     }
1424 
1425     for (i = 0; i < pool->base.pipe_count; i++) {
1426         pool->base.timing_generators[i] = dce60_timing_generator_create(
1427                 ctx, i, &dce60_tg_offsets[i]);
1428         if (pool->base.timing_generators[i] == NULL) {
1429             BREAK_TO_DEBUGGER();
1430             dm_error("DC: failed to create tg!\n");
1431             goto res_create_fail;
1432         }
1433 
1434         pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1435         if (pool->base.mis[i] == NULL) {
1436             BREAK_TO_DEBUGGER();
1437             dm_error("DC: failed to create memory input!\n");
1438             goto res_create_fail;
1439         }
1440 
1441         pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1442         if (pool->base.ipps[i] == NULL) {
1443             BREAK_TO_DEBUGGER();
1444             dm_error("DC: failed to create input pixel processor!\n");
1445             goto res_create_fail;
1446         }
1447 
1448         pool->base.transforms[i] = dce60_transform_create(ctx, i);
1449         if (pool->base.transforms[i] == NULL) {
1450             BREAK_TO_DEBUGGER();
1451             dm_error("DC: failed to create transform!\n");
1452             goto res_create_fail;
1453         }
1454 
1455         pool->base.opps[i] = dce60_opp_create(ctx, i);
1456         if (pool->base.opps[i] == NULL) {
1457             BREAK_TO_DEBUGGER();
1458             dm_error("DC: failed to create output pixel processor!\n");
1459             goto res_create_fail;
1460         }
1461     }
1462 
1463     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1464         pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1465         if (pool->base.engines[i] == NULL) {
1466             BREAK_TO_DEBUGGER();
1467             dm_error(
1468                 "DC:failed to create aux engine!!\n");
1469             goto res_create_fail;
1470         }
1471         pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1472         if (pool->base.hw_i2cs[i] == NULL) {
1473             BREAK_TO_DEBUGGER();
1474             dm_error(
1475                 "DC:failed to create i2c engine!!\n");
1476             goto res_create_fail;
1477         }
1478         pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1479         if (pool->base.sw_i2cs[i] == NULL) {
1480             BREAK_TO_DEBUGGER();
1481             dm_error(
1482                 "DC:failed to create sw i2c!!\n");
1483             goto res_create_fail;
1484         }
1485     }
1486 
1487     dc->caps.max_planes =  pool->base.pipe_count;
1488 
1489     for (i = 0; i < dc->caps.max_planes; ++i)
1490         dc->caps.planes[i] = plane_cap;
1491 
1492     dc->caps.disable_dp_clk_share = true;
1493 
1494     if (!resource_construct(num_virtual_links, dc, &pool->base,
1495             &res_create_funcs))
1496         goto res_create_fail;
1497 
1498     /* Create hardware sequencer */
1499     dce60_hw_sequencer_construct(dc);
1500 
1501     return true;
1502 
1503 res_create_fail:
1504     dce60_resource_destruct(pool);
1505     return false;
1506 }
1507 
1508 struct resource_pool *dce64_create_resource_pool(
1509     uint8_t num_virtual_links,
1510     struct dc *dc)
1511 {
1512     struct dce110_resource_pool *pool =
1513         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1514 
1515     if (!pool)
1516         return NULL;
1517 
1518     if (dce64_construct(num_virtual_links, dc, pool))
1519         return &pool->base;
1520 
1521     BREAK_TO_DEBUGGER();
1522     return NULL;
1523 }
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