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0001 /*
0002 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
0003 *
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026 
0027 #include "dm_services.h"
0028 
0029 
0030 #include "stream_encoder.h"
0031 #include "resource.h"
0032 #include "include/irq_service_interface.h"
0033 #include "dce120_resource.h"
0034 
0035 #include "dce112/dce112_resource.h"
0036 
0037 #include "dce110/dce110_resource.h"
0038 #include "../virtual/virtual_stream_encoder.h"
0039 #include "dce120_timing_generator.h"
0040 #include "irq/dce120/irq_service_dce120.h"
0041 #include "dce/dce_opp.h"
0042 #include "dce/dce_clock_source.h"
0043 #include "dce/dce_ipp.h"
0044 #include "dce/dce_mem_input.h"
0045 #include "dce/dce_panel_cntl.h"
0046 
0047 #include "dce110/dce110_hw_sequencer.h"
0048 #include "dce120/dce120_hw_sequencer.h"
0049 #include "dce/dce_transform.h"
0050 #include "clk_mgr.h"
0051 #include "dce/dce_audio.h"
0052 #include "dce/dce_link_encoder.h"
0053 #include "dce/dce_stream_encoder.h"
0054 #include "dce/dce_hwseq.h"
0055 #include "dce/dce_abm.h"
0056 #include "dce/dce_dmcu.h"
0057 #include "dce/dce_aux.h"
0058 #include "dce/dce_i2c.h"
0059 
0060 #include "dce/dce_12_0_offset.h"
0061 #include "dce/dce_12_0_sh_mask.h"
0062 #include "soc15_hw_ip.h"
0063 #include "vega10_ip_offset.h"
0064 #include "nbio/nbio_6_1_offset.h"
0065 #include "mmhub/mmhub_1_0_offset.h"
0066 #include "mmhub/mmhub_1_0_sh_mask.h"
0067 #include "reg_helper.h"
0068 
0069 #include "dce100/dce100_resource.h"
0070 
0071 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
0072     #define mmDP0_DP_DPHY_INTERNAL_CTRL     0x210f
0073     #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0074     #define mmDP1_DP_DPHY_INTERNAL_CTRL     0x220f
0075     #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0076     #define mmDP2_DP_DPHY_INTERNAL_CTRL     0x230f
0077     #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0078     #define mmDP3_DP_DPHY_INTERNAL_CTRL     0x240f
0079     #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0080     #define mmDP4_DP_DPHY_INTERNAL_CTRL     0x250f
0081     #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0082     #define mmDP5_DP_DPHY_INTERNAL_CTRL     0x260f
0083     #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0084     #define mmDP6_DP_DPHY_INTERNAL_CTRL     0x270f
0085     #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
0086 #endif
0087 
0088 enum dce120_clk_src_array_id {
0089     DCE120_CLK_SRC_PLL0,
0090     DCE120_CLK_SRC_PLL1,
0091     DCE120_CLK_SRC_PLL2,
0092     DCE120_CLK_SRC_PLL3,
0093     DCE120_CLK_SRC_PLL4,
0094     DCE120_CLK_SRC_PLL5,
0095 
0096     DCE120_CLK_SRC_TOTAL
0097 };
0098 
0099 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
0100     {
0101         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0102     },
0103     {
0104         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0105     },
0106     {
0107         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0108     },
0109     {
0110         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0111     },
0112     {
0113         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0114     },
0115     {
0116         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
0117     }
0118 };
0119 
0120 /* begin *********************
0121  * macros to expend register list macro defined in HW object header file */
0122 
0123 #define BASE_INNER(seg) \
0124     DCE_BASE__INST0_SEG ## seg
0125 
0126 #define NBIO_BASE_INNER(seg) \
0127     NBIF_BASE__INST0_SEG ## seg
0128 
0129 #define NBIO_BASE(seg) \
0130     NBIO_BASE_INNER(seg)
0131 
0132 /* compile time expand base address. */
0133 #define BASE(seg) \
0134     BASE_INNER(seg)
0135 
0136 #define SR(reg_name)\
0137         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
0138                     mm ## reg_name
0139 
0140 #define SRI(reg_name, block, id)\
0141     .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0142                     mm ## block ## id ## _ ## reg_name
0143 
0144 /* MMHUB */
0145 #define MMHUB_BASE_INNER(seg) \
0146     MMHUB_BASE__INST0_SEG ## seg
0147 
0148 #define MMHUB_BASE(seg) \
0149     MMHUB_BASE_INNER(seg)
0150 
0151 #define MMHUB_SR(reg_name)\
0152         .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
0153                     mm ## reg_name
0154 
0155 /* macros to expend register list macro defined in HW object header file
0156  * end *********************/
0157 
0158 
0159 static const struct dce_dmcu_registers dmcu_regs = {
0160         DMCU_DCE110_COMMON_REG_LIST()
0161 };
0162 
0163 static const struct dce_dmcu_shift dmcu_shift = {
0164         DMCU_MASK_SH_LIST_DCE110(__SHIFT)
0165 };
0166 
0167 static const struct dce_dmcu_mask dmcu_mask = {
0168         DMCU_MASK_SH_LIST_DCE110(_MASK)
0169 };
0170 
0171 static const struct dce_abm_registers abm_regs = {
0172         ABM_DCE110_COMMON_REG_LIST()
0173 };
0174 
0175 static const struct dce_abm_shift abm_shift = {
0176         ABM_MASK_SH_LIST_DCE110(__SHIFT)
0177 };
0178 
0179 static const struct dce_abm_mask abm_mask = {
0180         ABM_MASK_SH_LIST_DCE110(_MASK)
0181 };
0182 
0183 #define ipp_regs(id)\
0184 [id] = {\
0185         IPP_DCE110_REG_LIST_DCE_BASE(id)\
0186 }
0187 
0188 static const struct dce_ipp_registers ipp_regs[] = {
0189         ipp_regs(0),
0190         ipp_regs(1),
0191         ipp_regs(2),
0192         ipp_regs(3),
0193         ipp_regs(4),
0194         ipp_regs(5)
0195 };
0196 
0197 static const struct dce_ipp_shift ipp_shift = {
0198         IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
0199 };
0200 
0201 static const struct dce_ipp_mask ipp_mask = {
0202         IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
0203 };
0204 
0205 #define transform_regs(id)\
0206 [id] = {\
0207         XFM_COMMON_REG_LIST_DCE110(id)\
0208 }
0209 
0210 static const struct dce_transform_registers xfm_regs[] = {
0211         transform_regs(0),
0212         transform_regs(1),
0213         transform_regs(2),
0214         transform_regs(3),
0215         transform_regs(4),
0216         transform_regs(5)
0217 };
0218 
0219 static const struct dce_transform_shift xfm_shift = {
0220         XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
0221 };
0222 
0223 static const struct dce_transform_mask xfm_mask = {
0224         XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
0225 };
0226 
0227 #define aux_regs(id)\
0228 [id] = {\
0229     AUX_REG_LIST(id)\
0230 }
0231 
0232 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
0233         aux_regs(0),
0234         aux_regs(1),
0235         aux_regs(2),
0236         aux_regs(3),
0237         aux_regs(4),
0238         aux_regs(5)
0239 };
0240 
0241 #define hpd_regs(id)\
0242 [id] = {\
0243     HPD_REG_LIST(id)\
0244 }
0245 
0246 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
0247         hpd_regs(0),
0248         hpd_regs(1),
0249         hpd_regs(2),
0250         hpd_regs(3),
0251         hpd_regs(4),
0252         hpd_regs(5)
0253 };
0254 
0255 #define link_regs(id)\
0256 [id] = {\
0257     LE_DCE120_REG_LIST(id), \
0258     SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
0259 }
0260 
0261 static const struct dce110_link_enc_registers link_enc_regs[] = {
0262     link_regs(0),
0263     link_regs(1),
0264     link_regs(2),
0265     link_regs(3),
0266     link_regs(4),
0267     link_regs(5),
0268     link_regs(6),
0269 };
0270 
0271 
0272 #define stream_enc_regs(id)\
0273 [id] = {\
0274     SE_COMMON_REG_LIST(id),\
0275     .TMDS_CNTL = 0,\
0276 }
0277 
0278 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
0279     stream_enc_regs(0),
0280     stream_enc_regs(1),
0281     stream_enc_regs(2),
0282     stream_enc_regs(3),
0283     stream_enc_regs(4),
0284     stream_enc_regs(5)
0285 };
0286 
0287 static const struct dce_stream_encoder_shift se_shift = {
0288         SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
0289 };
0290 
0291 static const struct dce_stream_encoder_mask se_mask = {
0292         SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
0293 };
0294 
0295 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0296     { DCE_PANEL_CNTL_REG_LIST() }
0297 };
0298 
0299 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0300     DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0301 };
0302 
0303 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0304     DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0305 };
0306 
0307 static const struct dce110_aux_registers_shift aux_shift = {
0308     DCE12_AUX_MASK_SH_LIST(__SHIFT)
0309 };
0310 
0311 static const struct dce110_aux_registers_mask aux_mask = {
0312     DCE12_AUX_MASK_SH_LIST(_MASK)
0313 };
0314 
0315 #define opp_regs(id)\
0316 [id] = {\
0317     OPP_DCE_120_REG_LIST(id),\
0318 }
0319 
0320 static const struct dce_opp_registers opp_regs[] = {
0321     opp_regs(0),
0322     opp_regs(1),
0323     opp_regs(2),
0324     opp_regs(3),
0325     opp_regs(4),
0326     opp_regs(5)
0327 };
0328 
0329 static const struct dce_opp_shift opp_shift = {
0330     OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
0331 };
0332 
0333 static const struct dce_opp_mask opp_mask = {
0334     OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
0335 };
0336  #define aux_engine_regs(id)\
0337 [id] = {\
0338     AUX_COMMON_REG_LIST(id), \
0339     .AUX_RESET_MASK = 0 \
0340 }
0341 
0342 static const struct dce110_aux_registers aux_engine_regs[] = {
0343         aux_engine_regs(0),
0344         aux_engine_regs(1),
0345         aux_engine_regs(2),
0346         aux_engine_regs(3),
0347         aux_engine_regs(4),
0348         aux_engine_regs(5)
0349 };
0350 
0351 #define audio_regs(id)\
0352 [id] = {\
0353     AUD_COMMON_REG_LIST(id)\
0354 }
0355 
0356 static const struct dce_audio_registers audio_regs[] = {
0357     audio_regs(0),
0358     audio_regs(1),
0359     audio_regs(2),
0360     audio_regs(3),
0361     audio_regs(4),
0362     audio_regs(5)
0363 };
0364 
0365 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
0366         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0367         SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
0368         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
0369 
0370 static const struct dce_audio_shift audio_shift = {
0371         DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
0372 };
0373 
0374 static const struct dce_audio_mask audio_mask = {
0375         DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
0376 };
0377 
0378 static int map_transmitter_id_to_phy_instance(
0379     enum transmitter transmitter)
0380 {
0381     switch (transmitter) {
0382     case TRANSMITTER_UNIPHY_A:
0383         return 0;
0384     case TRANSMITTER_UNIPHY_B:
0385         return 1;
0386     case TRANSMITTER_UNIPHY_C:
0387         return 2;
0388     case TRANSMITTER_UNIPHY_D:
0389         return 3;
0390     case TRANSMITTER_UNIPHY_E:
0391         return 4;
0392     case TRANSMITTER_UNIPHY_F:
0393         return 5;
0394     case TRANSMITTER_UNIPHY_G:
0395         return 6;
0396     default:
0397         ASSERT(0);
0398         return 0;
0399     }
0400 }
0401 
0402 #define clk_src_regs(index, id)\
0403 [index] = {\
0404     CS_COMMON_REG_LIST_DCE_112(id),\
0405 }
0406 
0407 static const struct dce110_clk_src_regs clk_src_regs[] = {
0408     clk_src_regs(0, A),
0409     clk_src_regs(1, B),
0410     clk_src_regs(2, C),
0411     clk_src_regs(3, D),
0412     clk_src_regs(4, E),
0413     clk_src_regs(5, F)
0414 };
0415 
0416 static const struct dce110_clk_src_shift cs_shift = {
0417         CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
0418 };
0419 
0420 static const struct dce110_clk_src_mask cs_mask = {
0421         CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
0422 };
0423 
0424 static struct output_pixel_processor *dce120_opp_create(
0425     struct dc_context *ctx,
0426     uint32_t inst)
0427 {
0428     struct dce110_opp *opp =
0429         kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
0430 
0431     if (!opp)
0432         return NULL;
0433 
0434     dce110_opp_construct(opp,
0435                  ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0436     return &opp->base;
0437 }
0438 static struct dce_aux *dce120_aux_engine_create(
0439     struct dc_context *ctx,
0440     uint32_t inst)
0441 {
0442     struct aux_engine_dce110 *aux_engine =
0443         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0444 
0445     if (!aux_engine)
0446         return NULL;
0447 
0448     dce110_aux_engine_construct(aux_engine, ctx, inst,
0449                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0450                     &aux_engine_regs[inst],
0451                     &aux_mask,
0452                     &aux_shift,
0453                     ctx->dc->caps.extended_aux_timeout_support);
0454 
0455     return &aux_engine->base;
0456 }
0457 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0458 
0459 static const struct dce_i2c_registers i2c_hw_regs[] = {
0460         i2c_inst_regs(1),
0461         i2c_inst_regs(2),
0462         i2c_inst_regs(3),
0463         i2c_inst_regs(4),
0464         i2c_inst_regs(5),
0465         i2c_inst_regs(6),
0466 };
0467 
0468 static const struct dce_i2c_shift i2c_shifts = {
0469         I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
0470 };
0471 
0472 static const struct dce_i2c_mask i2c_masks = {
0473         I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
0474 };
0475 
0476 static struct dce_i2c_hw *dce120_i2c_hw_create(
0477     struct dc_context *ctx,
0478     uint32_t inst)
0479 {
0480     struct dce_i2c_hw *dce_i2c_hw =
0481         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0482 
0483     if (!dce_i2c_hw)
0484         return NULL;
0485 
0486     dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0487                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0488 
0489     return dce_i2c_hw;
0490 }
0491 static const struct bios_registers bios_regs = {
0492     .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
0493     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
0494 };
0495 
0496 static const struct resource_caps res_cap = {
0497         .num_timing_generator = 6,
0498         .num_audio = 7,
0499         .num_stream_encoder = 6,
0500         .num_pll = 6,
0501         .num_ddc = 6,
0502 };
0503 
0504 static const struct dc_plane_cap plane_cap = {
0505     .type = DC_PLANE_TYPE_DCE_RGB,
0506 
0507     .pixel_format_support = {
0508             .argb8888 = true,
0509             .nv12 = false,
0510             .fp16 = true
0511     },
0512 
0513     .max_upscale_factor = {
0514             .argb8888 = 16000,
0515             .nv12 = 1,
0516             .fp16 = 1
0517     },
0518 
0519     .max_downscale_factor = {
0520             .argb8888 = 250,
0521             .nv12 = 1,
0522             .fp16 = 1
0523     }
0524 };
0525 
0526 static const struct dc_debug_options debug_defaults = {
0527         .disable_clock_gate = true,
0528 };
0529 
0530 static struct clock_source *dce120_clock_source_create(
0531     struct dc_context *ctx,
0532     struct dc_bios *bios,
0533     enum clock_source_id id,
0534     const struct dce110_clk_src_regs *regs,
0535     bool dp_clk_src)
0536 {
0537     struct dce110_clk_src *clk_src =
0538         kzalloc(sizeof(*clk_src), GFP_KERNEL);
0539 
0540     if (!clk_src)
0541         return NULL;
0542 
0543     if (dce112_clk_src_construct(clk_src, ctx, bios, id,
0544                      regs, &cs_shift, &cs_mask)) {
0545         clk_src->base.dp_clk_src = dp_clk_src;
0546         return &clk_src->base;
0547     }
0548 
0549     kfree(clk_src);
0550     BREAK_TO_DEBUGGER();
0551     return NULL;
0552 }
0553 
0554 static void dce120_clock_source_destroy(struct clock_source **clk_src)
0555 {
0556     kfree(TO_DCE110_CLK_SRC(*clk_src));
0557     *clk_src = NULL;
0558 }
0559 
0560 
0561 static bool dce120_hw_sequencer_create(struct dc *dc)
0562 {
0563     /* All registers used by dce11.2 match those in dce11 in offset and
0564      * structure
0565      */
0566     dce120_hw_sequencer_construct(dc);
0567 
0568     /*TODO  Move to separate file and Override what is needed */
0569 
0570     return true;
0571 }
0572 
0573 static struct timing_generator *dce120_timing_generator_create(
0574         struct dc_context *ctx,
0575         uint32_t instance,
0576         const struct dce110_timing_generator_offsets *offsets)
0577 {
0578     struct dce110_timing_generator *tg110 =
0579         kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
0580 
0581     if (!tg110)
0582         return NULL;
0583 
0584     dce120_timing_generator_construct(tg110, ctx, instance, offsets);
0585     return &tg110->base;
0586 }
0587 
0588 static void dce120_transform_destroy(struct transform **xfm)
0589 {
0590     kfree(TO_DCE_TRANSFORM(*xfm));
0591     *xfm = NULL;
0592 }
0593 
0594 static void dce120_resource_destruct(struct dce110_resource_pool *pool)
0595 {
0596     unsigned int i;
0597 
0598     for (i = 0; i < pool->base.pipe_count; i++) {
0599         if (pool->base.opps[i] != NULL)
0600             dce110_opp_destroy(&pool->base.opps[i]);
0601 
0602         if (pool->base.transforms[i] != NULL)
0603             dce120_transform_destroy(&pool->base.transforms[i]);
0604 
0605         if (pool->base.ipps[i] != NULL)
0606             dce_ipp_destroy(&pool->base.ipps[i]);
0607 
0608         if (pool->base.mis[i] != NULL) {
0609             kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
0610             pool->base.mis[i] = NULL;
0611         }
0612 
0613         if (pool->base.irqs != NULL) {
0614             dal_irq_service_destroy(&pool->base.irqs);
0615         }
0616 
0617         if (pool->base.timing_generators[i] != NULL) {
0618             kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
0619             pool->base.timing_generators[i] = NULL;
0620         }
0621     }
0622 
0623     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
0624         if (pool->base.engines[i] != NULL)
0625             dce110_engine_destroy(&pool->base.engines[i]);
0626         if (pool->base.hw_i2cs[i] != NULL) {
0627             kfree(pool->base.hw_i2cs[i]);
0628             pool->base.hw_i2cs[i] = NULL;
0629         }
0630         if (pool->base.sw_i2cs[i] != NULL) {
0631             kfree(pool->base.sw_i2cs[i]);
0632             pool->base.sw_i2cs[i] = NULL;
0633         }
0634     }
0635 
0636     for (i = 0; i < pool->base.audio_count; i++) {
0637         if (pool->base.audios[i])
0638             dce_aud_destroy(&pool->base.audios[i]);
0639     }
0640 
0641     for (i = 0; i < pool->base.stream_enc_count; i++) {
0642         if (pool->base.stream_enc[i] != NULL)
0643             kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0644     }
0645 
0646     for (i = 0; i < pool->base.clk_src_count; i++) {
0647         if (pool->base.clock_sources[i] != NULL)
0648             dce120_clock_source_destroy(
0649                 &pool->base.clock_sources[i]);
0650     }
0651 
0652     if (pool->base.dp_clock_source != NULL)
0653         dce120_clock_source_destroy(&pool->base.dp_clock_source);
0654 
0655     if (pool->base.abm != NULL)
0656         dce_abm_destroy(&pool->base.abm);
0657 
0658     if (pool->base.dmcu != NULL)
0659         dce_dmcu_destroy(&pool->base.dmcu);
0660 }
0661 
0662 static void read_dce_straps(
0663     struct dc_context *ctx,
0664     struct resource_straps *straps)
0665 {
0666     uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
0667 
0668     straps->audio_stream_number = get_reg_field_value(reg_val,
0669                               CC_DC_MISC_STRAPS,
0670                               AUDIO_STREAM_NUMBER);
0671     straps->hdmi_disable = get_reg_field_value(reg_val,
0672                            CC_DC_MISC_STRAPS,
0673                            HDMI_DISABLE);
0674 
0675     reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
0676     straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
0677                              DC_PINSTRAPS,
0678                              DC_PINSTRAPS_AUDIO);
0679 }
0680 
0681 static struct audio *create_audio(
0682         struct dc_context *ctx, unsigned int inst)
0683 {
0684     return dce_audio_create(ctx, inst,
0685             &audio_regs[inst], &audio_shift, &audio_mask);
0686 }
0687 
0688 static const struct encoder_feature_support link_enc_feature = {
0689         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0690         .max_hdmi_pixel_clock = 600000,
0691         .hdmi_ycbcr420_supported = true,
0692         .dp_ycbcr420_supported = false,
0693         .flags.bits.IS_HBR2_CAPABLE = true,
0694         .flags.bits.IS_HBR3_CAPABLE = true,
0695         .flags.bits.IS_TPS3_CAPABLE = true,
0696         .flags.bits.IS_TPS4_CAPABLE = true,
0697 };
0698 
0699 static struct link_encoder *dce120_link_encoder_create(
0700     struct dc_context *ctx,
0701     const struct encoder_init_data *enc_init_data)
0702 {
0703     struct dce110_link_encoder *enc110 =
0704         kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
0705     int link_regs_id;
0706 
0707     if (!enc110)
0708         return NULL;
0709 
0710     link_regs_id =
0711         map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
0712 
0713     dce110_link_encoder_construct(enc110,
0714                       enc_init_data,
0715                       &link_enc_feature,
0716                       &link_enc_regs[link_regs_id],
0717                       &link_enc_aux_regs[enc_init_data->channel - 1],
0718                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
0719 
0720     return &enc110->base;
0721 }
0722 
0723 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0724 {
0725     struct dce_panel_cntl *panel_cntl =
0726         kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0727 
0728     if (!panel_cntl)
0729         return NULL;
0730 
0731     dce_panel_cntl_construct(panel_cntl,
0732             init_data,
0733             &panel_cntl_regs[init_data->inst],
0734             &panel_cntl_shift,
0735             &panel_cntl_mask);
0736 
0737     return &panel_cntl->base;
0738 }
0739 
0740 static struct input_pixel_processor *dce120_ipp_create(
0741     struct dc_context *ctx, uint32_t inst)
0742 {
0743     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
0744 
0745     if (!ipp) {
0746         BREAK_TO_DEBUGGER();
0747         return NULL;
0748     }
0749 
0750     dce_ipp_construct(ipp, ctx, inst,
0751             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0752     return &ipp->base;
0753 }
0754 
0755 static struct stream_encoder *dce120_stream_encoder_create(
0756     enum engine_id eng_id,
0757     struct dc_context *ctx)
0758 {
0759     struct dce110_stream_encoder *enc110 =
0760         kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
0761 
0762     if (!enc110)
0763         return NULL;
0764 
0765     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
0766                     &stream_enc_regs[eng_id],
0767                     &se_shift, &se_mask);
0768     return &enc110->base;
0769 }
0770 
0771 #define SRII(reg_name, block, id)\
0772     .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
0773                     mm ## block ## id ## _ ## reg_name
0774 
0775 static const struct dce_hwseq_registers hwseq_reg = {
0776         HWSEQ_DCE120_REG_LIST()
0777 };
0778 
0779 static const struct dce_hwseq_shift hwseq_shift = {
0780         HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
0781 };
0782 
0783 static const struct dce_hwseq_mask hwseq_mask = {
0784         HWSEQ_DCE12_MASK_SH_LIST(_MASK)
0785 };
0786 
0787 /* HWSEQ regs for VG20 */
0788 static const struct dce_hwseq_registers dce121_hwseq_reg = {
0789         HWSEQ_VG20_REG_LIST()
0790 };
0791 
0792 static const struct dce_hwseq_shift dce121_hwseq_shift = {
0793         HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
0794 };
0795 
0796 static const struct dce_hwseq_mask dce121_hwseq_mask = {
0797         HWSEQ_VG20_MASK_SH_LIST(_MASK)
0798 };
0799 
0800 static struct dce_hwseq *dce120_hwseq_create(
0801     struct dc_context *ctx)
0802 {
0803     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0804 
0805     if (hws) {
0806         hws->ctx = ctx;
0807         hws->regs = &hwseq_reg;
0808         hws->shifts = &hwseq_shift;
0809         hws->masks = &hwseq_mask;
0810     }
0811     return hws;
0812 }
0813 
0814 static struct dce_hwseq *dce121_hwseq_create(
0815     struct dc_context *ctx)
0816 {
0817     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0818 
0819     if (hws) {
0820         hws->ctx = ctx;
0821         hws->regs = &dce121_hwseq_reg;
0822         hws->shifts = &dce121_hwseq_shift;
0823         hws->masks = &dce121_hwseq_mask;
0824     }
0825     return hws;
0826 }
0827 
0828 static const struct resource_create_funcs res_create_funcs = {
0829     .read_dce_straps = read_dce_straps,
0830     .create_audio = create_audio,
0831     .create_stream_encoder = dce120_stream_encoder_create,
0832     .create_hwseq = dce120_hwseq_create,
0833 };
0834 
0835 static const struct resource_create_funcs dce121_res_create_funcs = {
0836     .read_dce_straps = read_dce_straps,
0837     .create_audio = create_audio,
0838     .create_stream_encoder = dce120_stream_encoder_create,
0839     .create_hwseq = dce121_hwseq_create,
0840 };
0841 
0842 
0843 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
0844 static const struct dce_mem_input_registers mi_regs[] = {
0845         mi_inst_regs(0),
0846         mi_inst_regs(1),
0847         mi_inst_regs(2),
0848         mi_inst_regs(3),
0849         mi_inst_regs(4),
0850         mi_inst_regs(5),
0851 };
0852 
0853 static const struct dce_mem_input_shift mi_shifts = {
0854         MI_DCE12_MASK_SH_LIST(__SHIFT)
0855 };
0856 
0857 static const struct dce_mem_input_mask mi_masks = {
0858         MI_DCE12_MASK_SH_LIST(_MASK)
0859 };
0860 
0861 static struct mem_input *dce120_mem_input_create(
0862     struct dc_context *ctx,
0863     uint32_t inst)
0864 {
0865     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
0866                            GFP_KERNEL);
0867 
0868     if (!dce_mi) {
0869         BREAK_TO_DEBUGGER();
0870         return NULL;
0871     }
0872 
0873     dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
0874     return &dce_mi->base;
0875 }
0876 
0877 static struct transform *dce120_transform_create(
0878     struct dc_context *ctx,
0879     uint32_t inst)
0880 {
0881     struct dce_transform *transform =
0882         kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
0883 
0884     if (!transform)
0885         return NULL;
0886 
0887     dce_transform_construct(transform, ctx, inst,
0888                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
0889     transform->lb_memory_size = 0x1404; /*5124*/
0890     return &transform->base;
0891 }
0892 
0893 static void dce120_destroy_resource_pool(struct resource_pool **pool)
0894 {
0895     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
0896 
0897     dce120_resource_destruct(dce110_pool);
0898     kfree(dce110_pool);
0899     *pool = NULL;
0900 }
0901 
0902 static const struct resource_funcs dce120_res_pool_funcs = {
0903     .destroy = dce120_destroy_resource_pool,
0904     .link_enc_create = dce120_link_encoder_create,
0905     .panel_cntl_create = dce120_panel_cntl_create,
0906     .validate_bandwidth = dce112_validate_bandwidth,
0907     .validate_plane = dce100_validate_plane,
0908     .add_stream_to_ctx = dce112_add_stream_to_ctx,
0909     .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
0910 };
0911 
0912 static void bw_calcs_data_update_from_pplib(struct dc *dc)
0913 {
0914     struct dm_pp_clock_levels_with_latency eng_clks = {0};
0915     struct dm_pp_clock_levels_with_latency mem_clks = {0};
0916     struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
0917     int i;
0918     unsigned int clk;
0919     unsigned int latency;
0920     /*original logic in dal3*/
0921     int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
0922 
0923     /*do system clock*/
0924     if (!dm_pp_get_clock_levels_by_type_with_latency(
0925                 dc->ctx,
0926                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
0927                 &eng_clks) || eng_clks.num_levels == 0) {
0928 
0929         eng_clks.num_levels = 8;
0930         clk = 300000;
0931 
0932         for (i = 0; i < eng_clks.num_levels; i++) {
0933             eng_clks.data[i].clocks_in_khz = clk;
0934             clk += 100000;
0935         }
0936     }
0937 
0938     /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
0939     dc->bw_vbios->high_sclk = bw_frc_to_fixed(
0940         eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
0941     dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
0942         eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
0943     dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
0944         eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
0945     dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
0946         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
0947     dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
0948         eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
0949     dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
0950         eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
0951     dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
0952         eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
0953     dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
0954             eng_clks.data[0].clocks_in_khz, 1000);
0955 
0956     /*do memory clock*/
0957     if (!dm_pp_get_clock_levels_by_type_with_latency(
0958             dc->ctx,
0959             DM_PP_CLOCK_TYPE_MEMORY_CLK,
0960             &mem_clks) || mem_clks.num_levels == 0) {
0961 
0962         mem_clks.num_levels = 3;
0963         clk = 250000;
0964         latency = 45;
0965 
0966         for (i = 0; i < eng_clks.num_levels; i++) {
0967             mem_clks.data[i].clocks_in_khz = clk;
0968             mem_clks.data[i].latency_in_us = latency;
0969             clk += 500000;
0970             latency -= 5;
0971         }
0972 
0973     }
0974 
0975     /* we don't need to call PPLIB for validation clock since they
0976      * also give us the highest sclk and highest mclk (UMA clock).
0977      * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
0978      * YCLK = UMACLK*m_memoryTypeMultiplier
0979      */
0980     if (dc->bw_vbios->memory_type == bw_def_hbm)
0981         memory_type_multiplier = MEMORY_TYPE_HBM;
0982 
0983     dc->bw_vbios->low_yclk = bw_frc_to_fixed(
0984         mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
0985     dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
0986         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
0987         1000);
0988     dc->bw_vbios->high_yclk = bw_frc_to_fixed(
0989         mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
0990         1000);
0991 
0992     /* Now notify PPLib/SMU about which Watermarks sets they should select
0993      * depending on DPM state they are in. And update BW MGR GFX Engine and
0994      * Memory clock member variables for Watermarks calculations for each
0995      * Watermark Set
0996      */
0997     clk_ranges.num_wm_sets = 4;
0998     clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
0999     clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1000             eng_clks.data[0].clocks_in_khz;
1001     clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1002             eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1003     clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1004             mem_clks.data[0].clocks_in_khz;
1005     clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1006             mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1007 
1008     clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1009     clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1010             eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1011     /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1012     clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1013     clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1014             mem_clks.data[0].clocks_in_khz;
1015     clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1016             mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1017 
1018     clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1019     clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1020             eng_clks.data[0].clocks_in_khz;
1021     clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1022             eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1023     clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1024             mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1025     /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1026     clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1027 
1028     clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1029     clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1030             eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1031     /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1032     clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1033     clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1034             mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1035     /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1036     clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1037 
1038     /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1039     dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1040 }
1041 
1042 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1043 {
1044     uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1045     /* VG20 support max 6 pipes */
1046     value = value & 0x3f;
1047     return value;
1048 }
1049 
1050 static bool dce120_resource_construct(
1051     uint8_t num_virtual_links,
1052     struct dc *dc,
1053     struct dce110_resource_pool *pool)
1054 {
1055     unsigned int i;
1056     int j;
1057     struct dc_context *ctx = dc->ctx;
1058     struct irq_service_init_data irq_init_data;
1059     static const struct resource_create_funcs *res_funcs;
1060     bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1061     uint32_t pipe_fuses;
1062 
1063     ctx->dc_bios->regs = &bios_regs;
1064 
1065     pool->base.res_cap = &res_cap;
1066     pool->base.funcs = &dce120_res_pool_funcs;
1067 
1068     /* TODO: Fill more data from GreenlandAsicCapability.cpp */
1069     pool->base.pipe_count = res_cap.num_timing_generator;
1070     pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1071     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1072 
1073     dc->caps.max_downscale_ratio = 200;
1074     dc->caps.i2c_speed_in_khz = 100;
1075     dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1076     dc->caps.max_cursor_size = 128;
1077     dc->caps.min_horizontal_blanking_period = 80;
1078     dc->caps.dual_link_dvi = true;
1079     dc->caps.psp_setup_panel_mode = true;
1080     dc->caps.extended_aux_timeout_support = false;
1081     dc->debug = debug_defaults;
1082 
1083     /*************************************************
1084      *  Create resources                             *
1085      *************************************************/
1086 
1087     pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1088             dce120_clock_source_create(ctx, ctx->dc_bios,
1089                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1090                 &clk_src_regs[0], false);
1091     pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1092             dce120_clock_source_create(ctx, ctx->dc_bios,
1093                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1094                 &clk_src_regs[1], false);
1095     pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1096             dce120_clock_source_create(ctx, ctx->dc_bios,
1097                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1098                 &clk_src_regs[2], false);
1099     pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1100             dce120_clock_source_create(ctx, ctx->dc_bios,
1101                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1102                 &clk_src_regs[3], false);
1103     pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1104             dce120_clock_source_create(ctx, ctx->dc_bios,
1105                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1106                 &clk_src_regs[4], false);
1107     pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1108             dce120_clock_source_create(ctx, ctx->dc_bios,
1109                 CLOCK_SOURCE_COMBO_PHY_PLL5,
1110                 &clk_src_regs[5], false);
1111     pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1112 
1113     pool->base.dp_clock_source =
1114             dce120_clock_source_create(ctx, ctx->dc_bios,
1115                 CLOCK_SOURCE_ID_DP_DTO,
1116                 &clk_src_regs[0], true);
1117 
1118     for (i = 0; i < pool->base.clk_src_count; i++) {
1119         if (pool->base.clock_sources[i] == NULL) {
1120             dm_error("DC: failed to create clock sources!\n");
1121             BREAK_TO_DEBUGGER();
1122             goto clk_src_create_fail;
1123         }
1124     }
1125 
1126     pool->base.dmcu = dce_dmcu_create(ctx,
1127             &dmcu_regs,
1128             &dmcu_shift,
1129             &dmcu_mask);
1130     if (pool->base.dmcu == NULL) {
1131         dm_error("DC: failed to create dmcu!\n");
1132         BREAK_TO_DEBUGGER();
1133         goto res_create_fail;
1134     }
1135 
1136     pool->base.abm = dce_abm_create(ctx,
1137             &abm_regs,
1138             &abm_shift,
1139             &abm_mask);
1140     if (pool->base.abm == NULL) {
1141         dm_error("DC: failed to create abm!\n");
1142         BREAK_TO_DEBUGGER();
1143         goto res_create_fail;
1144     }
1145 
1146 
1147     irq_init_data.ctx = dc->ctx;
1148     pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1149     if (!pool->base.irqs)
1150         goto irqs_create_fail;
1151 
1152     /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1153     if (is_vg20)
1154         pipe_fuses = read_pipe_fuses(ctx);
1155 
1156     /* index to valid pipe resource */
1157     j = 0;
1158     for (i = 0; i < pool->base.pipe_count; i++) {
1159         if (is_vg20) {
1160             if ((pipe_fuses & (1 << i)) != 0) {
1161                 dm_error("DC: skip invalid pipe %d!\n", i);
1162                 continue;
1163             }
1164         }
1165 
1166         pool->base.timing_generators[j] =
1167                 dce120_timing_generator_create(
1168                     ctx,
1169                     i,
1170                     &dce120_tg_offsets[i]);
1171         if (pool->base.timing_generators[j] == NULL) {
1172             BREAK_TO_DEBUGGER();
1173             dm_error("DC: failed to create tg!\n");
1174             goto controller_create_fail;
1175         }
1176 
1177         pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1178 
1179         if (pool->base.mis[j] == NULL) {
1180             BREAK_TO_DEBUGGER();
1181             dm_error(
1182                 "DC: failed to create memory input!\n");
1183             goto controller_create_fail;
1184         }
1185 
1186         pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1187         if (pool->base.ipps[i] == NULL) {
1188             BREAK_TO_DEBUGGER();
1189             dm_error(
1190                 "DC: failed to create input pixel processor!\n");
1191             goto controller_create_fail;
1192         }
1193 
1194         pool->base.transforms[j] = dce120_transform_create(ctx, i);
1195         if (pool->base.transforms[i] == NULL) {
1196             BREAK_TO_DEBUGGER();
1197             dm_error(
1198                 "DC: failed to create transform!\n");
1199             goto res_create_fail;
1200         }
1201 
1202         pool->base.opps[j] = dce120_opp_create(
1203             ctx,
1204             i);
1205         if (pool->base.opps[j] == NULL) {
1206             BREAK_TO_DEBUGGER();
1207             dm_error(
1208                 "DC: failed to create output pixel processor!\n");
1209         }
1210 
1211         /* check next valid pipe */
1212         j++;
1213     }
1214 
1215     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1216         pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1217         if (pool->base.engines[i] == NULL) {
1218             BREAK_TO_DEBUGGER();
1219             dm_error(
1220                 "DC:failed to create aux engine!!\n");
1221             goto res_create_fail;
1222         }
1223         pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1224         if (pool->base.hw_i2cs[i] == NULL) {
1225             BREAK_TO_DEBUGGER();
1226             dm_error(
1227                 "DC:failed to create i2c engine!!\n");
1228             goto res_create_fail;
1229         }
1230         pool->base.sw_i2cs[i] = NULL;
1231     }
1232 
1233     /* valid pipe num */
1234     pool->base.pipe_count = j;
1235     pool->base.timing_generator_count = j;
1236 
1237     if (is_vg20)
1238         res_funcs = &dce121_res_create_funcs;
1239     else
1240         res_funcs = &res_create_funcs;
1241 
1242     if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1243         goto res_create_fail;
1244 
1245     /* Create hardware sequencer */
1246     if (!dce120_hw_sequencer_create(dc))
1247         goto controller_create_fail;
1248 
1249     dc->caps.max_planes =  pool->base.pipe_count;
1250 
1251     for (i = 0; i < dc->caps.max_planes; ++i)
1252         dc->caps.planes[i] = plane_cap;
1253 
1254     bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1255 
1256     bw_calcs_data_update_from_pplib(dc);
1257 
1258     return true;
1259 
1260 irqs_create_fail:
1261 controller_create_fail:
1262 clk_src_create_fail:
1263 res_create_fail:
1264 
1265     dce120_resource_destruct(pool);
1266 
1267     return false;
1268 }
1269 
1270 struct resource_pool *dce120_create_resource_pool(
1271     uint8_t num_virtual_links,
1272     struct dc *dc)
1273 {
1274     struct dce110_resource_pool *pool =
1275         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1276 
1277     if (!pool)
1278         return NULL;
1279 
1280     if (dce120_resource_construct(num_virtual_links, dc, pool))
1281         return &pool->base;
1282 
1283     kfree(pool);
1284     BREAK_TO_DEBUGGER();
1285     return NULL;
1286 }
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