dc/dce112/dce112_hw_sequencer.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "dm_services.h"
0027 #include "dc.h"
0028 #include "core_types.h"
0029 #include "dce112_hw_sequencer.h"
0030
0031 #include "dce110/dce110_hw_sequencer.h"
0032
0033 /* include DCE11.2 register header files */
0034 #include "dce/dce_11_2_d.h"
0035 #include "dce/dce_11_2_sh_mask.h"
0036
0037 struct dce112_hw_seq_reg_offsets {
0038     uint32_t crtc;
0039 };
0040
0041
0042 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
0043 {
0044     .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0045 },
0046 {
0047     .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0048 },
0049 {
0050     .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0051 },
0052 {
0053     .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0054 },
0055 {
0056     .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0057 },
0058 {
0059     .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0060 }
0061 };
0062 #define HW_REG_CRTC(reg, id)\
0063     (reg + reg_offsets[id].crtc)
0064
0065 /*******************************************************************************
0066  * Private definitions
0067  ******************************************************************************/
0068
0069 static void dce112_init_pte(struct dc_context *ctx)
0070 {
0071     uint32_t addr;
0072     uint32_t value = 0;
0073     uint32_t chunk_int = 0;
0074     uint32_t chunk_mul = 0;
0075
0076     addr = mmDVMM_PTE_REQ;
0077     value = dm_read_reg(ctx, addr);
0078
0079     chunk_int = get_reg_field_value(
0080         value,
0081         DVMM_PTE_REQ,
0082         HFLIP_PTEREQ_PER_CHUNK_INT);
0083
0084     chunk_mul = get_reg_field_value(
0085         value,
0086         DVMM_PTE_REQ,
0087         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
0088
0089     if (chunk_int != 0x4 || chunk_mul != 0x4) {
0090
0091         set_reg_field_value(
0092             value,
0093             255,
0094             DVMM_PTE_REQ,
0095             MAX_PTEREQ_TO_ISSUE);
0096
0097         set_reg_field_value(
0098             value,
0099             4,
0100             DVMM_PTE_REQ,
0101             HFLIP_PTEREQ_PER_CHUNK_INT);
0102
0103         set_reg_field_value(
0104             value,
0105             4,
0106             DVMM_PTE_REQ,
0107             HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
0108
0109         dm_write_reg(ctx, addr, value);
0110     }
0111 }
0112
0113 static bool dce112_enable_display_power_gating(
0114     struct dc *dc,
0115     uint8_t controller_id,
0116     struct dc_bios *dcb,
0117     enum pipe_gating_control power_gating)
0118 {
0119     enum bp_result bp_result = BP_RESULT_OK;
0120     enum bp_pipe_control_action cntl;
0121     struct dc_context *ctx = dc->ctx;
0122
0123     if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
0124         return true;
0125
0126     if (power_gating == PIPE_GATING_CONTROL_INIT)
0127         cntl = ASIC_PIPE_INIT;
0128     else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
0129         cntl = ASIC_PIPE_ENABLE;
0130     else
0131         cntl = ASIC_PIPE_DISABLE;
0132
0133     if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
0134
0135         bp_result = dcb->funcs->enable_disp_power_gating(
0136                         dcb, controller_id + 1, cntl);
0137
0138         /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
0139          * by default when command table is called
0140          */
0141         dm_write_reg(ctx,
0142             HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
0143             0);
0144     }
0145
0146     if (power_gating != PIPE_GATING_CONTROL_ENABLE)
0147         dce112_init_pte(ctx);
0148
0149     if (bp_result == BP_RESULT_OK)
0150         return true;
0151     else
0152         return false;
0153 }
0154
0155 void dce112_hw_sequencer_construct(struct dc *dc)
0156 {
0157     /* All registers used by dce11.2 match those in dce11 in offset and
0158      * structure
0159      */
0160     dce110_hw_sequencer_construct(dc);
0161     dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
0162 }
0163