dc/dce110/dce110_timing_generator.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_TIMING_GENERATOR_DCE110_H__
0027 #define __DC_TIMING_GENERATOR_DCE110_H__
0028
0029 #include "timing_generator.h"
0030 #include "../include/grph_object_id.h"
0031
0032 /* GSL Sync related values */
0033
0034 /* In VSync mode, after 4 units of time, master pipe will generate
0035  * flip_ready signal */
0036 #define VFLIP_READY_DELAY 4
0037 /* In HSync mode, after 2 units of time, master pipe will generate
0038  * flip_ready signal */
0039 #define HFLIP_READY_DELAY 2
0040 /* 6 lines delay between forcing flip and checking all pipes ready */
0041 #define HFLIP_CHECK_DELAY 6
0042 /* 3 lines before end of frame */
0043 #define FLIP_READY_BACK_LOOKUP 3
0044
0045 /* Trigger Source Select - ASIC-defendant, actual values for the
0046  * register programming */
0047 enum trigger_source_select {
0048     TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0,
0049     TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1,
0050     TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2,
0051     TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3,
0052     TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4,
0053     TRIGGER_SOURCE_SELECT_GENERICF = 5,
0054     TRIGGER_SOURCE_SELECT_GENERICE = 6,
0055     TRIGGER_SOURCE_SELECT_VSYNCA = 7,
0056     TRIGGER_SOURCE_SELECT_HSYNCA = 8,
0057     TRIGGER_SOURCE_SELECT_VSYNCB = 9,
0058     TRIGGER_SOURCE_SELECT_HSYNCB = 10,
0059     TRIGGER_SOURCE_SELECT_HPD1 = 11,
0060     TRIGGER_SOURCE_SELECT_HPD2 = 12,
0061     TRIGGER_SOURCE_SELECT_GENERICD = 13,
0062     TRIGGER_SOURCE_SELECT_GENERICC = 14,
0063     TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15,
0064     TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16,
0065     TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17,
0066     TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18,
0067     TRIGGER_SOURCE_SELECT_BLONY = 19,
0068     TRIGGER_SOURCE_SELECT_GENERICA = 20,
0069     TRIGGER_SOURCE_SELECT_GENERICB = 21,
0070     TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22,
0071     TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23
0072 };
0073
0074 /* Trigger Source Select - ASIC-dependant, actual values for the
0075  * register programming */
0076 enum trigger_polarity_select {
0077     TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0,
0078     TRIGGER_POLARITY_SELECT_CRTC = 1,
0079     TRIGGER_POLARITY_SELECT_GENERICA = 2,
0080     TRIGGER_POLARITY_SELECT_GENERICB = 3,
0081     TRIGGER_POLARITY_SELECT_HSYNCA = 4,
0082     TRIGGER_POLARITY_SELECT_HSYNCB = 5,
0083     TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE = 6,
0084     TRIGGER_POLARITY_SELECT_GENERICC = 7
0085 };
0086
0087
0088 struct dce110_timing_generator_offsets {
0089     int32_t crtc;
0090     int32_t dcp;
0091
0092     /* DCE80 use only */
0093     int32_t dmif;
0094 };
0095
0096 struct dce110_timing_generator {
0097     struct timing_generator base;
0098     struct dce110_timing_generator_offsets offsets;
0099     struct dce110_timing_generator_offsets derived_offsets;
0100
0101     enum controller_id controller_id;
0102
0103     uint32_t max_h_total;
0104     uint32_t max_v_total;
0105
0106     uint32_t min_h_blank;
0107     uint32_t min_h_front_porch;
0108     uint32_t min_h_back_porch;
0109
0110     /* DCE 12 */
0111     uint32_t min_h_sync_width;
0112     uint32_t min_v_sync_width;
0113     uint32_t min_v_blank;
0114
0115 };
0116
0117 #define DCE110TG_FROM_TG(tg)\
0118     container_of(tg, struct dce110_timing_generator, base)
0119
0120 void dce110_timing_generator_construct(
0121     struct dce110_timing_generator *tg,
0122     struct dc_context *ctx,
0123     uint32_t instance,
0124     const struct dce110_timing_generator_offsets *offsets);
0125
0126 /* determine if given timing can be supported by TG */
0127 bool dce110_timing_generator_validate_timing(
0128     struct timing_generator *tg,
0129     const struct dc_crtc_timing *timing,
0130     enum signal_type signal);
0131
0132 /******** HW programming ************/
0133
0134 /* Program timing generator with given timing */
0135 bool dce110_timing_generator_program_timing_generator(
0136     struct timing_generator *tg,
0137     const struct dc_crtc_timing *dc_crtc_timing);
0138
0139 /* Disable/Enable Timing Generator */
0140 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
0141 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
0142
0143 void dce110_timing_generator_set_early_control(
0144         struct timing_generator *tg,
0145         uint32_t early_cntl);
0146
0147 /**************** TG current status ******************/
0148
0149 /* return the current frame counter. Used by Linux kernel DRM */
0150 uint32_t dce110_timing_generator_get_vblank_counter(
0151         struct timing_generator *tg);
0152
0153 void dce110_timing_generator_get_position(
0154     struct timing_generator *tg,
0155     struct crtc_position *position);
0156
0157 /* return true if TG counter is moving. false if TG is stopped */
0158 bool dce110_timing_generator_is_counter_moving(struct timing_generator *tg);
0159
0160 /* wait until TG is in beginning of vertical blank region */
0161 void dce110_timing_generator_wait_for_vblank(struct timing_generator *tg);
0162
0163 /* wait until TG is in beginning of active region */
0164 void dce110_timing_generator_wait_for_vactive(struct timing_generator *tg);
0165
0166 /*********** Timing Generator Synchronization routines ****/
0167
0168 /* Setups Global Swap Lock group, TimingServer or TimingClient*/
0169 void dce110_timing_generator_setup_global_swap_lock(
0170     struct timing_generator *tg,
0171     const struct dcp_gsl_params *gsl_params);
0172
0173 /* Clear all the register writes done by setup_global_swap_lock */
0174 void dce110_timing_generator_tear_down_global_swap_lock(
0175     struct timing_generator *tg);
0176
0177 /* Reset crtc position on master VSync */
0178 void dce110_timing_generator_enable_crtc_reset(
0179     struct timing_generator *tg,
0180     int source,
0181     struct crtc_trigger_info *crtc_tp);
0182
0183 /* Reset slave controllers on master VSync */
0184 void dce110_timing_generator_enable_reset_trigger(
0185     struct timing_generator *tg,
0186     int source);
0187
0188 /* disabling trigger-reset */
0189 void dce110_timing_generator_disable_reset_trigger(
0190     struct timing_generator *tg);
0191
0192 /* Checks whether CRTC triggered reset occurred */
0193 bool dce110_timing_generator_did_triggered_reset_occur(
0194     struct timing_generator *tg);
0195
0196 /******** Stuff to move to other virtual HW objects *****************/
0197 /* Move to enable accelerated mode */
0198 void dce110_timing_generator_disable_vga(struct timing_generator *tg);
0199 /* TODO: Should we move it to transform */
0200 /* Fully program CRTC timing in timing generator */
0201 void dce110_timing_generator_program_blanking(
0202     struct timing_generator *tg,
0203     const struct dc_crtc_timing *timing);
0204
0205 /* TODO: Should we move it to opp? */
0206 /* Combine with below and move YUV/RGB color conversion to SW layer */
0207 void dce110_timing_generator_program_blank_color(
0208     struct timing_generator *tg,
0209     const struct tg_color *black_color);
0210 /* Combine with above and move YUV/RGB color conversion to SW layer */
0211 void dce110_timing_generator_set_overscan_color_black(
0212     struct timing_generator *tg,
0213     const struct tg_color *color);
0214 void dce110_timing_generator_color_space_to_black_color(
0215         enum dc_color_space colorspace,
0216     struct tg_color *black_color);
0217 /*************** End-of-move ********************/
0218
0219 /* Not called yet */
0220 void dce110_timing_generator_set_test_pattern(
0221     struct timing_generator *tg,
0222     /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
0223      * because this is not DP-specific (which is probably somewhere in DP
0224      * encoder) */
0225     enum controller_dp_test_pattern test_pattern,
0226     enum dc_color_depth color_depth);
0227
0228 void dce110_timing_generator_set_drr(
0229     struct timing_generator *tg,
0230     const struct drr_params *params);
0231
0232 void dce110_timing_generator_set_static_screen_control(
0233     struct timing_generator *tg,
0234     uint32_t event_triggers,
0235     uint32_t num_frames);
0236
0237 void dce110_timing_generator_get_crtc_scanoutpos(
0238     struct timing_generator *tg,
0239     uint32_t *v_blank_start,
0240     uint32_t *v_blank_end,
0241     uint32_t *h_position,
0242     uint32_t *v_position);
0243
0244 void dce110_timing_generator_enable_advanced_request(
0245     struct timing_generator *tg,
0246     bool enable,
0247     const struct dc_crtc_timing *timing);
0248
0249 void dce110_timing_generator_set_lock_master(struct timing_generator *tg,
0250         bool lock);
0251
0252 void dce110_tg_program_blank_color(struct timing_generator *tg,
0253     const struct tg_color *black_color);
0254
0255 void dce110_tg_set_overscan_color(struct timing_generator *tg,
0256     const struct tg_color *overscan_color);
0257
0258 void dce110_tg_program_timing(struct timing_generator *tg,
0259     const struct dc_crtc_timing *timing,
0260     int vready_offset,
0261     int vstartup_start,
0262     int vupdate_offset,
0263     int vupdate_width,
0264     const enum signal_type signal,
0265     bool use_vbios);
0266
0267 bool dce110_tg_is_blanked(struct timing_generator *tg);
0268
0269 void dce110_tg_set_blank(struct timing_generator *tg,
0270         bool enable_blanking);
0271
0272 bool dce110_tg_validate_timing(struct timing_generator *tg,
0273     const struct dc_crtc_timing *timing);
0274
0275 void dce110_tg_wait_for_state(struct timing_generator *tg,
0276     enum crtc_state state);
0277
0278 void dce110_tg_set_colors(struct timing_generator *tg,
0279     const struct tg_color *blank_color,
0280     const struct tg_color *overscan_color);
0281
0282 bool dce110_arm_vert_intr(
0283         struct timing_generator *tg, uint8_t width);
0284
0285 bool dce110_configure_crc(struct timing_generator *tg,
0286               const struct crc_params *params);
0287
0288 bool dce110_get_crc(struct timing_generator *tg,
0289             uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
0290
0291 #endif /* __DC_TIMING_GENERATOR_DCE110_H__ */