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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 
0028 #include "link_encoder.h"
0029 #include "stream_encoder.h"
0030 
0031 #include "resource.h"
0032 #include "dce110/dce110_resource.h"
0033 #include "include/irq_service_interface.h"
0034 #include "dce/dce_audio.h"
0035 #include "dce110/dce110_timing_generator.h"
0036 #include "irq/dce110/irq_service_dce110.h"
0037 #include "dce110/dce110_timing_generator_v.h"
0038 #include "dce/dce_link_encoder.h"
0039 #include "dce/dce_stream_encoder.h"
0040 #include "dce/dce_mem_input.h"
0041 #include "dce110/dce110_mem_input_v.h"
0042 #include "dce/dce_ipp.h"
0043 #include "dce/dce_transform.h"
0044 #include "dce110/dce110_transform_v.h"
0045 #include "dce/dce_opp.h"
0046 #include "dce110/dce110_opp_v.h"
0047 #include "dce/dce_clock_source.h"
0048 #include "dce/dce_hwseq.h"
0049 #include "dce110/dce110_hw_sequencer.h"
0050 #include "dce/dce_aux.h"
0051 #include "dce/dce_abm.h"
0052 #include "dce/dce_dmcu.h"
0053 #include "dce/dce_i2c.h"
0054 #include "dce/dce_panel_cntl.h"
0055 
0056 #define DC_LOGGER \
0057         dc->ctx->logger
0058 
0059 #include "dce110/dce110_compressor.h"
0060 
0061 #include "reg_helper.h"
0062 
0063 #include "dce/dce_11_0_d.h"
0064 #include "dce/dce_11_0_sh_mask.h"
0065 
0066 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
0067 #include "gmc/gmc_8_2_d.h"
0068 #include "gmc/gmc_8_2_sh_mask.h"
0069 #endif
0070 
0071 #ifndef mmDP_DPHY_INTERNAL_CTRL
0072     #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
0073     #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
0074     #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
0075     #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
0076     #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
0077     #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
0078     #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
0079     #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
0080     #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
0081     #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
0082 #endif
0083 
0084 #ifndef mmBIOS_SCRATCH_2
0085     #define mmBIOS_SCRATCH_2 0x05CB
0086     #define mmBIOS_SCRATCH_3 0x05CC
0087     #define mmBIOS_SCRATCH_6 0x05CF
0088 #endif
0089 
0090 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
0091     #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
0092     #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
0093     #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
0094     #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
0095     #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
0096     #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
0097     #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
0098     #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
0099 #endif
0100 
0101 #ifndef mmDP_DPHY_FAST_TRAINING
0102     #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
0103     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
0104     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
0105     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
0106     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
0107     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
0108     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
0109     #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
0110 #endif
0111 
0112 #ifndef DPHY_RX_FAST_TRAINING_CAPABLE
0113     #define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
0114 #endif
0115 
0116 static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
0117     {
0118         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
0119         .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
0120     },
0121     {
0122         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
0123         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
0124     },
0125     {
0126         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
0127         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
0128     },
0129     {
0130         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
0131         .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
0132     },
0133     {
0134         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
0135         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
0136     },
0137     {
0138         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
0139         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
0140     }
0141 };
0142 
0143 /* set register offset */
0144 #define SR(reg_name)\
0145     .reg_name = mm ## reg_name
0146 
0147 /* set register offset with instance */
0148 #define SRI(reg_name, block, id)\
0149     .reg_name = mm ## block ## id ## _ ## reg_name
0150 
0151 static const struct dce_dmcu_registers dmcu_regs = {
0152         DMCU_DCE110_COMMON_REG_LIST()
0153 };
0154 
0155 static const struct dce_dmcu_shift dmcu_shift = {
0156         DMCU_MASK_SH_LIST_DCE110(__SHIFT)
0157 };
0158 
0159 static const struct dce_dmcu_mask dmcu_mask = {
0160         DMCU_MASK_SH_LIST_DCE110(_MASK)
0161 };
0162 
0163 static const struct dce_abm_registers abm_regs = {
0164         ABM_DCE110_COMMON_REG_LIST()
0165 };
0166 
0167 static const struct dce_abm_shift abm_shift = {
0168         ABM_MASK_SH_LIST_DCE110(__SHIFT)
0169 };
0170 
0171 static const struct dce_abm_mask abm_mask = {
0172         ABM_MASK_SH_LIST_DCE110(_MASK)
0173 };
0174 
0175 #define ipp_regs(id)\
0176 [id] = {\
0177         IPP_DCE110_REG_LIST_DCE_BASE(id)\
0178 }
0179 
0180 static const struct dce_ipp_registers ipp_regs[] = {
0181         ipp_regs(0),
0182         ipp_regs(1),
0183         ipp_regs(2)
0184 };
0185 
0186 static const struct dce_ipp_shift ipp_shift = {
0187         IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0188 };
0189 
0190 static const struct dce_ipp_mask ipp_mask = {
0191         IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0192 };
0193 
0194 #define transform_regs(id)\
0195 [id] = {\
0196         XFM_COMMON_REG_LIST_DCE110(id)\
0197 }
0198 
0199 static const struct dce_transform_registers xfm_regs[] = {
0200         transform_regs(0),
0201         transform_regs(1),
0202         transform_regs(2)
0203 };
0204 
0205 static const struct dce_transform_shift xfm_shift = {
0206         XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
0207 };
0208 
0209 static const struct dce_transform_mask xfm_mask = {
0210         XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
0211 };
0212 
0213 #define aux_regs(id)\
0214 [id] = {\
0215     AUX_REG_LIST(id)\
0216 }
0217 
0218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
0219         aux_regs(0),
0220         aux_regs(1),
0221         aux_regs(2),
0222         aux_regs(3),
0223         aux_regs(4),
0224         aux_regs(5)
0225 };
0226 
0227 #define hpd_regs(id)\
0228 [id] = {\
0229     HPD_REG_LIST(id)\
0230 }
0231 
0232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
0233         hpd_regs(0),
0234         hpd_regs(1),
0235         hpd_regs(2),
0236         hpd_regs(3),
0237         hpd_regs(4),
0238         hpd_regs(5)
0239 };
0240 
0241 
0242 #define link_regs(id)\
0243 [id] = {\
0244     LE_DCE110_REG_LIST(id)\
0245 }
0246 
0247 static const struct dce110_link_enc_registers link_enc_regs[] = {
0248     link_regs(0),
0249     link_regs(1),
0250     link_regs(2),
0251     link_regs(3),
0252     link_regs(4),
0253     link_regs(5),
0254     link_regs(6),
0255 };
0256 
0257 #define stream_enc_regs(id)\
0258 [id] = {\
0259     SE_COMMON_REG_LIST(id),\
0260     .TMDS_CNTL = 0,\
0261 }
0262 
0263 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
0264     stream_enc_regs(0),
0265     stream_enc_regs(1),
0266     stream_enc_regs(2)
0267 };
0268 
0269 static const struct dce_stream_encoder_shift se_shift = {
0270         SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
0271 };
0272 
0273 static const struct dce_stream_encoder_mask se_mask = {
0274         SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
0275 };
0276 
0277 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0278     { DCE_PANEL_CNTL_REG_LIST() }
0279 };
0280 
0281 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0282     DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0283 };
0284 
0285 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0286     DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0287 };
0288 
0289 static const struct dce110_aux_registers_shift aux_shift = {
0290     DCE_AUX_MASK_SH_LIST(__SHIFT)
0291 };
0292 
0293 static const struct dce110_aux_registers_mask aux_mask = {
0294     DCE_AUX_MASK_SH_LIST(_MASK)
0295 };
0296 
0297 #define opp_regs(id)\
0298 [id] = {\
0299     OPP_DCE_110_REG_LIST(id),\
0300 }
0301 
0302 static const struct dce_opp_registers opp_regs[] = {
0303     opp_regs(0),
0304     opp_regs(1),
0305     opp_regs(2),
0306     opp_regs(3),
0307     opp_regs(4),
0308     opp_regs(5)
0309 };
0310 
0311 static const struct dce_opp_shift opp_shift = {
0312     OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
0313 };
0314 
0315 static const struct dce_opp_mask opp_mask = {
0316     OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
0317 };
0318 
0319 #define aux_engine_regs(id)\
0320 [id] = {\
0321     AUX_COMMON_REG_LIST(id), \
0322     .AUX_RESET_MASK = 0 \
0323 }
0324 
0325 static const struct dce110_aux_registers aux_engine_regs[] = {
0326         aux_engine_regs(0),
0327         aux_engine_regs(1),
0328         aux_engine_regs(2),
0329         aux_engine_regs(3),
0330         aux_engine_regs(4),
0331         aux_engine_regs(5)
0332 };
0333 
0334 #define audio_regs(id)\
0335 [id] = {\
0336     AUD_COMMON_REG_LIST(id)\
0337 }
0338 
0339 static const struct dce_audio_registers audio_regs[] = {
0340     audio_regs(0),
0341     audio_regs(1),
0342     audio_regs(2),
0343     audio_regs(3),
0344     audio_regs(4),
0345     audio_regs(5),
0346     audio_regs(6),
0347 };
0348 
0349 static const struct dce_audio_shift audio_shift = {
0350         AUD_COMMON_MASK_SH_LIST(__SHIFT)
0351 };
0352 
0353 static const struct dce_audio_mask audio_mask = {
0354         AUD_COMMON_MASK_SH_LIST(_MASK)
0355 };
0356 
0357 /* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
0358 
0359 
0360 #define clk_src_regs(id)\
0361 [id] = {\
0362     CS_COMMON_REG_LIST_DCE_100_110(id),\
0363 }
0364 
0365 static const struct dce110_clk_src_regs clk_src_regs[] = {
0366     clk_src_regs(0),
0367     clk_src_regs(1),
0368     clk_src_regs(2)
0369 };
0370 
0371 static const struct dce110_clk_src_shift cs_shift = {
0372         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0373 };
0374 
0375 static const struct dce110_clk_src_mask cs_mask = {
0376         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0377 };
0378 
0379 static const struct bios_registers bios_regs = {
0380     .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
0381     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
0382 };
0383 
0384 static const struct resource_caps carrizo_resource_cap = {
0385         .num_timing_generator = 3,
0386         .num_video_plane = 1,
0387         .num_audio = 3,
0388         .num_stream_encoder = 3,
0389         .num_pll = 2,
0390         .num_ddc = 3,
0391 };
0392 
0393 static const struct resource_caps stoney_resource_cap = {
0394         .num_timing_generator = 2,
0395         .num_video_plane = 1,
0396         .num_audio = 3,
0397         .num_stream_encoder = 3,
0398         .num_pll = 2,
0399         .num_ddc = 3,
0400 };
0401 
0402 static const struct dc_plane_cap plane_cap = {
0403         .type = DC_PLANE_TYPE_DCE_RGB,
0404         .blends_with_below = true,
0405         .blends_with_above = true,
0406         .per_pixel_alpha = 1,
0407 
0408         .pixel_format_support = {
0409                 .argb8888 = true,
0410                 .nv12 = false,
0411                 .fp16 = true
0412         },
0413 
0414         .max_upscale_factor = {
0415                 .argb8888 = 16000,
0416                 .nv12 = 1,
0417                 .fp16 = 1
0418         },
0419 
0420         .max_downscale_factor = {
0421                 .argb8888 = 250,
0422                 .nv12 = 1,
0423                 .fp16 = 1
0424         },
0425         64,
0426         64
0427 };
0428 
0429 static const struct dc_plane_cap underlay_plane_cap = {
0430         .type = DC_PLANE_TYPE_DCE_UNDERLAY,
0431         .blends_with_above = true,
0432         .per_pixel_alpha = 1,
0433 
0434         .pixel_format_support = {
0435                 .argb8888 = false,
0436                 .nv12 = true,
0437                 .fp16 = false
0438         },
0439 
0440         .max_upscale_factor = {
0441                 .argb8888 = 1,
0442                 .nv12 = 16000,
0443                 .fp16 = 1
0444         },
0445 
0446         .max_downscale_factor = {
0447                 .argb8888 = 1,
0448                 .nv12 = 250,
0449                 .fp16 = 1
0450         },
0451         64,
0452         64
0453 };
0454 
0455 #define CTX  ctx
0456 #define REG(reg) mm ## reg
0457 
0458 #ifndef mmCC_DC_HDMI_STRAPS
0459 #define mmCC_DC_HDMI_STRAPS 0x4819
0460 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
0461 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
0462 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
0463 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
0464 #endif
0465 
0466 static int map_transmitter_id_to_phy_instance(
0467     enum transmitter transmitter)
0468 {
0469     switch (transmitter) {
0470     case TRANSMITTER_UNIPHY_A:
0471         return 0;
0472     case TRANSMITTER_UNIPHY_B:
0473         return 1;
0474     case TRANSMITTER_UNIPHY_C:
0475         return 2;
0476     case TRANSMITTER_UNIPHY_D:
0477         return 3;
0478     case TRANSMITTER_UNIPHY_E:
0479         return 4;
0480     case TRANSMITTER_UNIPHY_F:
0481         return 5;
0482     case TRANSMITTER_UNIPHY_G:
0483         return 6;
0484     default:
0485         ASSERT(0);
0486         return 0;
0487     }
0488 }
0489 
0490 static void read_dce_straps(
0491     struct dc_context *ctx,
0492     struct resource_straps *straps)
0493 {
0494     REG_GET_2(CC_DC_HDMI_STRAPS,
0495             HDMI_DISABLE, &straps->hdmi_disable,
0496             AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
0497 
0498     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
0499 }
0500 
0501 static struct audio *create_audio(
0502         struct dc_context *ctx, unsigned int inst)
0503 {
0504     return dce_audio_create(ctx, inst,
0505             &audio_regs[inst], &audio_shift, &audio_mask);
0506 }
0507 
0508 static struct timing_generator *dce110_timing_generator_create(
0509         struct dc_context *ctx,
0510         uint32_t instance,
0511         const struct dce110_timing_generator_offsets *offsets)
0512 {
0513     struct dce110_timing_generator *tg110 =
0514         kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
0515 
0516     if (!tg110)
0517         return NULL;
0518 
0519     dce110_timing_generator_construct(tg110, ctx, instance, offsets);
0520     return &tg110->base;
0521 }
0522 
0523 static struct stream_encoder *dce110_stream_encoder_create(
0524     enum engine_id eng_id,
0525     struct dc_context *ctx)
0526 {
0527     struct dce110_stream_encoder *enc110 =
0528         kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
0529 
0530     if (!enc110)
0531         return NULL;
0532 
0533     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
0534                     &stream_enc_regs[eng_id],
0535                     &se_shift, &se_mask);
0536     return &enc110->base;
0537 }
0538 
0539 #define SRII(reg_name, block, id)\
0540     .reg_name[id] = mm ## block ## id ## _ ## reg_name
0541 
0542 static const struct dce_hwseq_registers hwseq_stoney_reg = {
0543         HWSEQ_ST_REG_LIST()
0544 };
0545 
0546 static const struct dce_hwseq_registers hwseq_cz_reg = {
0547         HWSEQ_CZ_REG_LIST()
0548 };
0549 
0550 static const struct dce_hwseq_shift hwseq_shift = {
0551         HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
0552 };
0553 
0554 static const struct dce_hwseq_mask hwseq_mask = {
0555         HWSEQ_DCE11_MASK_SH_LIST(_MASK),
0556 };
0557 
0558 static struct dce_hwseq *dce110_hwseq_create(
0559     struct dc_context *ctx)
0560 {
0561     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0562 
0563     if (hws) {
0564         hws->ctx = ctx;
0565         hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
0566                 &hwseq_stoney_reg : &hwseq_cz_reg;
0567         hws->shifts = &hwseq_shift;
0568         hws->masks = &hwseq_mask;
0569         hws->wa.blnd_crtc_trigger = true;
0570     }
0571     return hws;
0572 }
0573 
0574 static const struct resource_create_funcs res_create_funcs = {
0575     .read_dce_straps = read_dce_straps,
0576     .create_audio = create_audio,
0577     .create_stream_encoder = dce110_stream_encoder_create,
0578     .create_hwseq = dce110_hwseq_create,
0579 };
0580 
0581 #define mi_inst_regs(id) { \
0582     MI_DCE11_REG_LIST(id), \
0583     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
0584 }
0585 static const struct dce_mem_input_registers mi_regs[] = {
0586         mi_inst_regs(0),
0587         mi_inst_regs(1),
0588         mi_inst_regs(2),
0589 };
0590 
0591 static const struct dce_mem_input_shift mi_shifts = {
0592         MI_DCE11_MASK_SH_LIST(__SHIFT),
0593         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
0594 };
0595 
0596 static const struct dce_mem_input_mask mi_masks = {
0597         MI_DCE11_MASK_SH_LIST(_MASK),
0598         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
0599 };
0600 
0601 
0602 static struct mem_input *dce110_mem_input_create(
0603     struct dc_context *ctx,
0604     uint32_t inst)
0605 {
0606     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
0607                            GFP_KERNEL);
0608 
0609     if (!dce_mi) {
0610         BREAK_TO_DEBUGGER();
0611         return NULL;
0612     }
0613 
0614     dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
0615     dce_mi->wa.single_head_rdreq_dmif_limit = 3;
0616     return &dce_mi->base;
0617 }
0618 
0619 static void dce110_transform_destroy(struct transform **xfm)
0620 {
0621     kfree(TO_DCE_TRANSFORM(*xfm));
0622     *xfm = NULL;
0623 }
0624 
0625 static struct transform *dce110_transform_create(
0626     struct dc_context *ctx,
0627     uint32_t inst)
0628 {
0629     struct dce_transform *transform =
0630         kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
0631 
0632     if (!transform)
0633         return NULL;
0634 
0635     dce_transform_construct(transform, ctx, inst,
0636                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
0637     return &transform->base;
0638 }
0639 
0640 static struct input_pixel_processor *dce110_ipp_create(
0641     struct dc_context *ctx, uint32_t inst)
0642 {
0643     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
0644 
0645     if (!ipp) {
0646         BREAK_TO_DEBUGGER();
0647         return NULL;
0648     }
0649 
0650     dce_ipp_construct(ipp, ctx, inst,
0651             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0652     return &ipp->base;
0653 }
0654 
0655 static const struct encoder_feature_support link_enc_feature = {
0656         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0657         .max_hdmi_pixel_clock = 300000,
0658         .flags.bits.IS_HBR2_CAPABLE = true,
0659         .flags.bits.IS_TPS3_CAPABLE = true
0660 };
0661 
0662 static struct link_encoder *dce110_link_encoder_create(
0663     struct dc_context *ctx,
0664     const struct encoder_init_data *enc_init_data)
0665 {
0666     struct dce110_link_encoder *enc110 =
0667         kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
0668     int link_regs_id;
0669 
0670     if (!enc110)
0671         return NULL;
0672 
0673     link_regs_id =
0674         map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
0675 
0676     dce110_link_encoder_construct(enc110,
0677                       enc_init_data,
0678                       &link_enc_feature,
0679                       &link_enc_regs[link_regs_id],
0680                       &link_enc_aux_regs[enc_init_data->channel - 1],
0681                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
0682     return &enc110->base;
0683 }
0684 
0685 static struct panel_cntl *dce110_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0686 {
0687     struct dce_panel_cntl *panel_cntl =
0688         kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0689 
0690     if (!panel_cntl)
0691         return NULL;
0692 
0693     dce_panel_cntl_construct(panel_cntl,
0694             init_data,
0695             &panel_cntl_regs[init_data->inst],
0696             &panel_cntl_shift,
0697             &panel_cntl_mask);
0698 
0699     return &panel_cntl->base;
0700 }
0701 
0702 static struct output_pixel_processor *dce110_opp_create(
0703     struct dc_context *ctx,
0704     uint32_t inst)
0705 {
0706     struct dce110_opp *opp =
0707         kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
0708 
0709     if (!opp)
0710         return NULL;
0711 
0712     dce110_opp_construct(opp,
0713                  ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0714     return &opp->base;
0715 }
0716 
0717 static struct dce_aux *dce110_aux_engine_create(
0718     struct dc_context *ctx,
0719     uint32_t inst)
0720 {
0721     struct aux_engine_dce110 *aux_engine =
0722         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0723 
0724     if (!aux_engine)
0725         return NULL;
0726 
0727     dce110_aux_engine_construct(aux_engine, ctx, inst,
0728                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0729                     &aux_engine_regs[inst],
0730                     &aux_mask,
0731                     &aux_shift,
0732                     ctx->dc->caps.extended_aux_timeout_support);
0733 
0734     return &aux_engine->base;
0735 }
0736 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0737 
0738 static const struct dce_i2c_registers i2c_hw_regs[] = {
0739         i2c_inst_regs(1),
0740         i2c_inst_regs(2),
0741         i2c_inst_regs(3),
0742         i2c_inst_regs(4),
0743         i2c_inst_regs(5),
0744         i2c_inst_regs(6),
0745 };
0746 
0747 static const struct dce_i2c_shift i2c_shifts = {
0748         I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
0749 };
0750 
0751 static const struct dce_i2c_mask i2c_masks = {
0752         I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
0753 };
0754 
0755 static struct dce_i2c_hw *dce110_i2c_hw_create(
0756     struct dc_context *ctx,
0757     uint32_t inst)
0758 {
0759     struct dce_i2c_hw *dce_i2c_hw =
0760         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0761 
0762     if (!dce_i2c_hw)
0763         return NULL;
0764 
0765     dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0766                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0767 
0768     return dce_i2c_hw;
0769 }
0770 static struct clock_source *dce110_clock_source_create(
0771     struct dc_context *ctx,
0772     struct dc_bios *bios,
0773     enum clock_source_id id,
0774     const struct dce110_clk_src_regs *regs,
0775     bool dp_clk_src)
0776 {
0777     struct dce110_clk_src *clk_src =
0778         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0779 
0780     if (!clk_src)
0781         return NULL;
0782 
0783     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
0784             regs, &cs_shift, &cs_mask)) {
0785         clk_src->base.dp_clk_src = dp_clk_src;
0786         return &clk_src->base;
0787     }
0788 
0789     kfree(clk_src);
0790     BREAK_TO_DEBUGGER();
0791     return NULL;
0792 }
0793 
0794 static void dce110_clock_source_destroy(struct clock_source **clk_src)
0795 {
0796     struct dce110_clk_src *dce110_clk_src;
0797 
0798     if (!clk_src)
0799         return;
0800 
0801     dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);
0802 
0803     kfree(dce110_clk_src->dp_ss_params);
0804     kfree(dce110_clk_src->hdmi_ss_params);
0805     kfree(dce110_clk_src->dvi_ss_params);
0806 
0807     kfree(dce110_clk_src);
0808     *clk_src = NULL;
0809 }
0810 
0811 static void dce110_resource_destruct(struct dce110_resource_pool *pool)
0812 {
0813     unsigned int i;
0814 
0815     for (i = 0; i < pool->base.pipe_count; i++) {
0816         if (pool->base.opps[i] != NULL)
0817             dce110_opp_destroy(&pool->base.opps[i]);
0818 
0819         if (pool->base.transforms[i] != NULL)
0820             dce110_transform_destroy(&pool->base.transforms[i]);
0821 
0822         if (pool->base.ipps[i] != NULL)
0823             dce_ipp_destroy(&pool->base.ipps[i]);
0824 
0825         if (pool->base.mis[i] != NULL) {
0826             kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
0827             pool->base.mis[i] = NULL;
0828         }
0829 
0830         if (pool->base.timing_generators[i] != NULL)    {
0831             kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
0832             pool->base.timing_generators[i] = NULL;
0833         }
0834     }
0835 
0836     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
0837         if (pool->base.engines[i] != NULL)
0838             dce110_engine_destroy(&pool->base.engines[i]);
0839         if (pool->base.hw_i2cs[i] != NULL) {
0840             kfree(pool->base.hw_i2cs[i]);
0841             pool->base.hw_i2cs[i] = NULL;
0842         }
0843         if (pool->base.sw_i2cs[i] != NULL) {
0844             kfree(pool->base.sw_i2cs[i]);
0845             pool->base.sw_i2cs[i] = NULL;
0846         }
0847     }
0848 
0849     for (i = 0; i < pool->base.stream_enc_count; i++) {
0850         if (pool->base.stream_enc[i] != NULL)
0851             kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0852     }
0853 
0854     for (i = 0; i < pool->base.clk_src_count; i++) {
0855         if (pool->base.clock_sources[i] != NULL) {
0856             dce110_clock_source_destroy(&pool->base.clock_sources[i]);
0857         }
0858     }
0859 
0860     if (pool->base.dp_clock_source != NULL)
0861         dce110_clock_source_destroy(&pool->base.dp_clock_source);
0862 
0863     for (i = 0; i < pool->base.audio_count; i++)    {
0864         if (pool->base.audios[i] != NULL) {
0865             dce_aud_destroy(&pool->base.audios[i]);
0866         }
0867     }
0868 
0869     if (pool->base.abm != NULL)
0870         dce_abm_destroy(&pool->base.abm);
0871 
0872     if (pool->base.dmcu != NULL)
0873         dce_dmcu_destroy(&pool->base.dmcu);
0874 
0875     if (pool->base.irqs != NULL) {
0876         dal_irq_service_destroy(&pool->base.irqs);
0877     }
0878 }
0879 
0880 
0881 static void get_pixel_clock_parameters(
0882     const struct pipe_ctx *pipe_ctx,
0883     struct pixel_clk_params *pixel_clk_params)
0884 {
0885     const struct dc_stream_state *stream = pipe_ctx->stream;
0886 
0887     /*TODO: is this halved for YCbCr 420? in that case we might want to move
0888      * the pixel clock normalization for hdmi up to here instead of doing it
0889      * in pll_adjust_pix_clk
0890      */
0891     pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
0892     pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
0893     pixel_clk_params->signal_type = pipe_ctx->stream->signal;
0894     pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
0895     /* TODO: un-hardcode*/
0896     pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
0897                         LINK_RATE_REF_FREQ_IN_KHZ;
0898     pixel_clk_params->flags.ENABLE_SS = 0;
0899     pixel_clk_params->color_depth =
0900         stream->timing.display_color_depth;
0901     pixel_clk_params->flags.DISPLAY_BLANKED = 1;
0902     pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
0903             PIXEL_ENCODING_YCBCR420);
0904     pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
0905     if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0906         pixel_clk_params->color_depth = COLOR_DEPTH_888;
0907     }
0908     if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
0909         pixel_clk_params->requested_pix_clk_100hz  = pixel_clk_params->requested_pix_clk_100hz / 2;
0910     }
0911     if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
0912         pixel_clk_params->requested_pix_clk_100hz *= 2;
0913 
0914 }
0915 
0916 void dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
0917 {
0918     get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
0919     pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
0920         pipe_ctx->clock_source,
0921         &pipe_ctx->stream_res.pix_clk_params,
0922         &pipe_ctx->pll_settings);
0923     resource_build_bit_depth_reduction_params(pipe_ctx->stream,
0924             &pipe_ctx->stream->bit_depth_params);
0925     pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
0926 }
0927 
0928 static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
0929 {
0930     if (pipe_ctx->pipe_idx != underlay_idx)
0931         return true;
0932     if (!pipe_ctx->plane_state)
0933         return false;
0934     if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
0935         return false;
0936     return true;
0937 }
0938 
0939 static enum dc_status build_mapped_resource(
0940         const struct dc *dc,
0941         struct dc_state *context,
0942         struct dc_stream_state *stream)
0943 {
0944     struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
0945 
0946     if (!pipe_ctx)
0947         return DC_ERROR_UNEXPECTED;
0948 
0949     if (!is_surface_pixel_format_supported(pipe_ctx,
0950             dc->res_pool->underlay_pipe_index))
0951         return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
0952 
0953     dce110_resource_build_pipe_hw_param(pipe_ctx);
0954 
0955     /* TODO: validate audio ASIC caps, encoder */
0956 
0957     resource_build_info_frame(pipe_ctx);
0958 
0959     return DC_OK;
0960 }
0961 
0962 static bool dce110_validate_bandwidth(
0963     struct dc *dc,
0964     struct dc_state *context,
0965     bool fast_validate)
0966 {
0967     bool result = false;
0968 
0969     DC_LOG_BANDWIDTH_CALCS(
0970         "%s: start",
0971         __func__);
0972 
0973     if (bw_calcs(
0974             dc->ctx,
0975             dc->bw_dceip,
0976             dc->bw_vbios,
0977             context->res_ctx.pipe_ctx,
0978             dc->res_pool->pipe_count,
0979             &context->bw_ctx.bw.dce))
0980         result =  true;
0981 
0982     if (!result)
0983         DC_LOG_BANDWIDTH_VALIDATION("%s: %dx%d@%d Bandwidth validation failed!\n",
0984             __func__,
0985             context->streams[0]->timing.h_addressable,
0986             context->streams[0]->timing.v_addressable,
0987             context->streams[0]->timing.pix_clk_100hz / 10);
0988 
0989     if (memcmp(&dc->current_state->bw_ctx.bw.dce,
0990             &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
0991 
0992         DC_LOG_BANDWIDTH_CALCS(
0993             "%s: finish,\n"
0994             "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
0995             "stutMark_b: %d stutMark_a: %d\n"
0996             "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
0997             "stutMark_b: %d stutMark_a: %d\n"
0998             "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
0999             "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
1000             "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
1001             "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
1002             ,
1003             __func__,
1004             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
1005             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
1006             context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
1007             context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
1008             context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
1009             context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark,
1010             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark,
1011             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark,
1012             context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark,
1013             context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark,
1014             context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark,
1015             context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark,
1016             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark,
1017             context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark,
1018             context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark,
1019             context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark,
1020             context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark,
1021             context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark,
1022             context->bw_ctx.bw.dce.stutter_mode_enable,
1023             context->bw_ctx.bw.dce.cpuc_state_change_enable,
1024             context->bw_ctx.bw.dce.cpup_state_change_enable,
1025             context->bw_ctx.bw.dce.nbp_state_change_enable,
1026             context->bw_ctx.bw.dce.all_displays_in_sync,
1027             context->bw_ctx.bw.dce.dispclk_khz,
1028             context->bw_ctx.bw.dce.sclk_khz,
1029             context->bw_ctx.bw.dce.sclk_deep_sleep_khz,
1030             context->bw_ctx.bw.dce.yclk_khz,
1031             context->bw_ctx.bw.dce.blackout_recovery_time_us);
1032     }
1033     return result;
1034 }
1035 
1036 static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
1037                         struct dc_caps *caps)
1038 {
1039     if (((plane_state->dst_rect.width * 2) < plane_state->src_rect.width) ||
1040         ((plane_state->dst_rect.height * 2) < plane_state->src_rect.height))
1041         return DC_FAIL_SURFACE_VALIDATE;
1042 
1043     return DC_OK;
1044 }
1045 
1046 static bool dce110_validate_surface_sets(
1047         struct dc_state *context)
1048 {
1049     int i, j;
1050 
1051     for (i = 0; i < context->stream_count; i++) {
1052         if (context->stream_status[i].plane_count == 0)
1053             continue;
1054 
1055         if (context->stream_status[i].plane_count > 2)
1056             return false;
1057 
1058         for (j = 0; j < context->stream_status[i].plane_count; j++) {
1059             struct dc_plane_state *plane =
1060                 context->stream_status[i].plane_states[j];
1061 
1062             /* underlay validation */
1063             if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1064 
1065                 if ((plane->src_rect.width > 1920 ||
1066                     plane->src_rect.height > 1080))
1067                     return false;
1068 
1069                 /* we don't have the logic to support underlay
1070                  * only yet so block the use case where we get
1071                  * NV12 plane as top layer
1072                  */
1073                 if (j == 0)
1074                     return false;
1075 
1076                 /* irrespective of plane format,
1077                  * stream should be RGB encoded
1078                  */
1079                 if (context->streams[i]->timing.pixel_encoding
1080                         != PIXEL_ENCODING_RGB)
1081                     return false;
1082 
1083             }
1084 
1085         }
1086     }
1087 
1088     return true;
1089 }
1090 
1091 static enum dc_status dce110_validate_global(
1092         struct dc *dc,
1093         struct dc_state *context)
1094 {
1095     if (!dce110_validate_surface_sets(context))
1096         return DC_FAIL_SURFACE_VALIDATE;
1097 
1098     return DC_OK;
1099 }
1100 
1101 static enum dc_status dce110_add_stream_to_ctx(
1102         struct dc *dc,
1103         struct dc_state *new_ctx,
1104         struct dc_stream_state *dc_stream)
1105 {
1106     enum dc_status result = DC_ERROR_UNEXPECTED;
1107 
1108     result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1109 
1110     if (result == DC_OK)
1111         result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1112 
1113 
1114     if (result == DC_OK)
1115         result = build_mapped_resource(dc, new_ctx, dc_stream);
1116 
1117     return result;
1118 }
1119 
1120 static struct pipe_ctx *dce110_acquire_underlay(
1121         struct dc_state *context,
1122         const struct resource_pool *pool,
1123         struct dc_stream_state *stream)
1124 {
1125     struct dc *dc = stream->ctx->dc;
1126     struct dce_hwseq *hws = dc->hwseq;
1127     struct resource_context *res_ctx = &context->res_ctx;
1128     unsigned int underlay_idx = pool->underlay_pipe_index;
1129     struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];
1130 
1131     if (res_ctx->pipe_ctx[underlay_idx].stream)
1132         return NULL;
1133 
1134     pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
1135     pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
1136     /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
1137     pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
1138     pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
1139     pipe_ctx->pipe_idx = underlay_idx;
1140 
1141     pipe_ctx->stream = stream;
1142 
1143     if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) {
1144         struct tg_color black_color = {0};
1145         struct dc_bios *dcb = dc->ctx->dc_bios;
1146 
1147         hws->funcs.enable_display_power_gating(
1148                 dc,
1149                 pipe_ctx->stream_res.tg->inst,
1150                 dcb, PIPE_GATING_CONTROL_DISABLE);
1151 
1152         /*
1153          * This is for powering on underlay, so crtc does not
1154          * need to be enabled
1155          */
1156 
1157         pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
1158                 &stream->timing,
1159                 0,
1160                 0,
1161                 0,
1162                 0,
1163                 pipe_ctx->stream->signal,
1164                 false);
1165 
1166         pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
1167                 pipe_ctx->stream_res.tg,
1168                 true,
1169                 &stream->timing);
1170 
1171         pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1172                 stream->timing.h_total,
1173                 stream->timing.v_total,
1174                 stream->timing.pix_clk_100hz / 10,
1175                 context->stream_count);
1176 
1177         color_space_to_black_color(dc,
1178                 COLOR_SPACE_YCBCR601, &black_color);
1179         pipe_ctx->stream_res.tg->funcs->set_blank_color(
1180                 pipe_ctx->stream_res.tg,
1181                 &black_color);
1182     }
1183 
1184     return pipe_ctx;
1185 }
1186 
1187 static void dce110_destroy_resource_pool(struct resource_pool **pool)
1188 {
1189     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
1190 
1191     dce110_resource_destruct(dce110_pool);
1192     kfree(dce110_pool);
1193     *pool = NULL;
1194 }
1195 
1196 struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link(
1197         struct resource_context *res_ctx,
1198         const struct resource_pool *pool,
1199         struct dc_stream_state *stream)
1200 {
1201     int i;
1202     int j = -1;
1203     struct dc_link *link = stream->link;
1204 
1205     for (i = 0; i < pool->stream_enc_count; i++) {
1206         if (!res_ctx->is_stream_enc_acquired[i] &&
1207                 pool->stream_enc[i]) {
1208             /* Store first available for MST second display
1209              * in daisy chain use case
1210              */
1211             j = i;
1212             if (pool->stream_enc[i]->id ==
1213                     link->link_enc->preferred_engine)
1214                 return pool->stream_enc[i];
1215         }
1216     }
1217 
1218     /*
1219      * For CZ and later, we can allow DIG FE and BE to differ for all display types
1220      */
1221 
1222     if (j >= 0)
1223         return pool->stream_enc[j];
1224 
1225     return NULL;
1226 }
1227 
1228 
1229 static const struct resource_funcs dce110_res_pool_funcs = {
1230     .destroy = dce110_destroy_resource_pool,
1231     .link_enc_create = dce110_link_encoder_create,
1232     .panel_cntl_create = dce110_panel_cntl_create,
1233     .validate_bandwidth = dce110_validate_bandwidth,
1234     .validate_plane = dce110_validate_plane,
1235     .acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1236     .add_stream_to_ctx = dce110_add_stream_to_ctx,
1237     .validate_global = dce110_validate_global,
1238     .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
1239 };
1240 
1241 static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1242 {
1243     struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv),
1244                                  GFP_KERNEL);
1245     struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv),
1246                             GFP_KERNEL);
1247     struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv),
1248                            GFP_KERNEL);
1249     struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv),
1250                          GFP_KERNEL);
1251 
1252     if (!dce110_tgv || !dce110_xfmv || !dce110_miv || !dce110_oppv) {
1253         kfree(dce110_tgv);
1254         kfree(dce110_xfmv);
1255         kfree(dce110_miv);
1256         kfree(dce110_oppv);
1257         return false;
1258     }
1259 
1260     dce110_opp_v_construct(dce110_oppv, ctx);
1261 
1262     dce110_timing_generator_v_construct(dce110_tgv, ctx);
1263     dce110_mem_input_v_construct(dce110_miv, ctx);
1264     dce110_transform_v_construct(dce110_xfmv, ctx);
1265 
1266     pool->opps[pool->pipe_count] = &dce110_oppv->base;
1267     pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
1268     pool->mis[pool->pipe_count] = &dce110_miv->base;
1269     pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
1270     pool->pipe_count++;
1271 
1272     /* update the public caps to indicate an underlay is available */
1273     ctx->dc->caps.max_slave_planes = 1;
1274     ctx->dc->caps.max_slave_yuv_planes = 1;
1275     ctx->dc->caps.max_slave_rgb_planes = 0;
1276 
1277     return true;
1278 }
1279 
1280 static void bw_calcs_data_update_from_pplib(struct dc *dc)
1281 {
1282     struct dm_pp_clock_levels clks = {0};
1283 
1284     /*do system clock*/
1285     dm_pp_get_clock_levels_by_type(
1286             dc->ctx,
1287             DM_PP_CLOCK_TYPE_ENGINE_CLK,
1288             &clks);
1289     /* convert all the clock fro kHz to fix point mHz */
1290     dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1291             clks.clocks_in_khz[clks.num_levels-1], 1000);
1292     dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1293             clks.clocks_in_khz[clks.num_levels/8], 1000);
1294     dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1295             clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1296     dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1297             clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1298     dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1299             clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1300     dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1301             clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1302     dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1303             clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1304     dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1305             clks.clocks_in_khz[0], 1000);
1306     dc->sclk_lvls = clks;
1307 
1308     /*do display clock*/
1309     dm_pp_get_clock_levels_by_type(
1310             dc->ctx,
1311             DM_PP_CLOCK_TYPE_DISPLAY_CLK,
1312             &clks);
1313     dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1314             clks.clocks_in_khz[clks.num_levels-1], 1000);
1315     dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
1316             clks.clocks_in_khz[clks.num_levels>>1], 1000);
1317     dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
1318             clks.clocks_in_khz[0], 1000);
1319 
1320     /*do memory clock*/
1321     dm_pp_get_clock_levels_by_type(
1322             dc->ctx,
1323             DM_PP_CLOCK_TYPE_MEMORY_CLK,
1324             &clks);
1325 
1326     dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1327         clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000);
1328     dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1329         clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ,
1330         1000);
1331     dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1332         clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ,
1333         1000);
1334 }
1335 
1336 static const struct resource_caps *dce110_resource_cap(
1337     struct hw_asic_id *asic_id)
1338 {
1339     if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
1340         return &stoney_resource_cap;
1341     else
1342         return &carrizo_resource_cap;
1343 }
1344 
1345 static bool dce110_resource_construct(
1346     uint8_t num_virtual_links,
1347     struct dc *dc,
1348     struct dce110_resource_pool *pool,
1349     struct hw_asic_id asic_id)
1350 {
1351     unsigned int i;
1352     struct dc_context *ctx = dc->ctx;
1353     struct dc_bios *bp;
1354 
1355     ctx->dc_bios->regs = &bios_regs;
1356 
1357     pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
1358     pool->base.funcs = &dce110_res_pool_funcs;
1359 
1360     /*************************************************
1361      *  Resource + asic cap harcoding                *
1362      *************************************************/
1363 
1364     pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1365     pool->base.underlay_pipe_index = pool->base.pipe_count;
1366     pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1367     dc->caps.max_downscale_ratio = 150;
1368     dc->caps.i2c_speed_in_khz = 40;
1369     dc->caps.i2c_speed_in_khz_hdcp = 40;
1370     dc->caps.max_cursor_size = 128;
1371     dc->caps.min_horizontal_blanking_period = 80;
1372     dc->caps.is_apu = true;
1373     dc->caps.extended_aux_timeout_support = false;
1374 
1375     /*************************************************
1376      *  Create resources                             *
1377      *************************************************/
1378 
1379     bp = ctx->dc_bios;
1380 
1381     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1382         pool->base.dp_clock_source =
1383                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1384 
1385         pool->base.clock_sources[0] =
1386                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
1387                         &clk_src_regs[0], false);
1388         pool->base.clock_sources[1] =
1389                 dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
1390                         &clk_src_regs[1], false);
1391 
1392         pool->base.clk_src_count = 2;
1393 
1394         /* TODO: find out if CZ support 3 PLLs */
1395     }
1396 
1397     if (pool->base.dp_clock_source == NULL) {
1398         dm_error("DC: failed to create dp clock source!\n");
1399         BREAK_TO_DEBUGGER();
1400         goto res_create_fail;
1401     }
1402 
1403     for (i = 0; i < pool->base.clk_src_count; i++) {
1404         if (pool->base.clock_sources[i] == NULL) {
1405             dm_error("DC: failed to create clock sources!\n");
1406             BREAK_TO_DEBUGGER();
1407             goto res_create_fail;
1408         }
1409     }
1410 
1411     pool->base.dmcu = dce_dmcu_create(ctx,
1412             &dmcu_regs,
1413             &dmcu_shift,
1414             &dmcu_mask);
1415     if (pool->base.dmcu == NULL) {
1416         dm_error("DC: failed to create dmcu!\n");
1417         BREAK_TO_DEBUGGER();
1418         goto res_create_fail;
1419     }
1420 
1421     pool->base.abm = dce_abm_create(ctx,
1422             &abm_regs,
1423             &abm_shift,
1424             &abm_mask);
1425     if (pool->base.abm == NULL) {
1426         dm_error("DC: failed to create abm!\n");
1427         BREAK_TO_DEBUGGER();
1428         goto res_create_fail;
1429     }
1430 
1431     {
1432         struct irq_service_init_data init_data;
1433         init_data.ctx = dc->ctx;
1434         pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1435         if (!pool->base.irqs)
1436             goto res_create_fail;
1437     }
1438 
1439     for (i = 0; i < pool->base.pipe_count; i++) {
1440         pool->base.timing_generators[i] = dce110_timing_generator_create(
1441                 ctx, i, &dce110_tg_offsets[i]);
1442         if (pool->base.timing_generators[i] == NULL) {
1443             BREAK_TO_DEBUGGER();
1444             dm_error("DC: failed to create tg!\n");
1445             goto res_create_fail;
1446         }
1447 
1448         pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1449         if (pool->base.mis[i] == NULL) {
1450             BREAK_TO_DEBUGGER();
1451             dm_error(
1452                 "DC: failed to create memory input!\n");
1453             goto res_create_fail;
1454         }
1455 
1456         pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1457         if (pool->base.ipps[i] == NULL) {
1458             BREAK_TO_DEBUGGER();
1459             dm_error(
1460                 "DC: failed to create input pixel processor!\n");
1461             goto res_create_fail;
1462         }
1463 
1464         pool->base.transforms[i] = dce110_transform_create(ctx, i);
1465         if (pool->base.transforms[i] == NULL) {
1466             BREAK_TO_DEBUGGER();
1467             dm_error(
1468                 "DC: failed to create transform!\n");
1469             goto res_create_fail;
1470         }
1471 
1472         pool->base.opps[i] = dce110_opp_create(ctx, i);
1473         if (pool->base.opps[i] == NULL) {
1474             BREAK_TO_DEBUGGER();
1475             dm_error(
1476                 "DC: failed to create output pixel processor!\n");
1477             goto res_create_fail;
1478         }
1479     }
1480 
1481     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1482         pool->base.engines[i] = dce110_aux_engine_create(ctx, i);
1483         if (pool->base.engines[i] == NULL) {
1484             BREAK_TO_DEBUGGER();
1485             dm_error(
1486                 "DC:failed to create aux engine!!\n");
1487             goto res_create_fail;
1488         }
1489         pool->base.hw_i2cs[i] = dce110_i2c_hw_create(ctx, i);
1490         if (pool->base.hw_i2cs[i] == NULL) {
1491             BREAK_TO_DEBUGGER();
1492             dm_error(
1493                 "DC:failed to create i2c engine!!\n");
1494             goto res_create_fail;
1495         }
1496         pool->base.sw_i2cs[i] = NULL;
1497     }
1498 
1499     if (dc->config.fbc_support)
1500         dc->fbc_compressor = dce110_compressor_create(ctx);
1501 
1502     if (!underlay_create(ctx, &pool->base))
1503         goto res_create_fail;
1504 
1505     if (!resource_construct(num_virtual_links, dc, &pool->base,
1506             &res_create_funcs))
1507         goto res_create_fail;
1508 
1509     /* Create hardware sequencer */
1510     dce110_hw_sequencer_construct(dc);
1511 
1512     dc->caps.max_planes =  pool->base.pipe_count;
1513 
1514     for (i = 0; i < pool->base.underlay_pipe_index; ++i)
1515         dc->caps.planes[i] = plane_cap;
1516 
1517     dc->caps.planes[pool->base.underlay_pipe_index] = underlay_plane_cap;
1518 
1519     bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1520 
1521     bw_calcs_data_update_from_pplib(dc);
1522 
1523     return true;
1524 
1525 res_create_fail:
1526     dce110_resource_destruct(pool);
1527     return false;
1528 }
1529 
1530 struct resource_pool *dce110_create_resource_pool(
1531     uint8_t num_virtual_links,
1532     struct dc *dc,
1533     struct hw_asic_id asic_id)
1534 {
1535     struct dce110_resource_pool *pool =
1536         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1537 
1538     if (!pool)
1539         return NULL;
1540 
1541     if (dce110_resource_construct(num_virtual_links, dc, pool, asic_id))
1542         return &pool->base;
1543 
1544     kfree(pool);
1545     BREAK_TO_DEBUGGER();
1546     return NULL;
1547 }
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