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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dm_services.h"
0027 
0028 #include "link_encoder.h"
0029 #include "stream_encoder.h"
0030 
0031 #include "resource.h"
0032 #include "include/irq_service_interface.h"
0033 #include "../virtual/virtual_stream_encoder.h"
0034 #include "dce110/dce110_resource.h"
0035 #include "dce110/dce110_timing_generator.h"
0036 #include "irq/dce110/irq_service_dce110.h"
0037 #include "dce/dce_link_encoder.h"
0038 #include "dce/dce_stream_encoder.h"
0039 #include "dce/dce_mem_input.h"
0040 #include "dce/dce_ipp.h"
0041 #include "dce/dce_transform.h"
0042 #include "dce/dce_opp.h"
0043 #include "dce/dce_clock_source.h"
0044 #include "dce/dce_audio.h"
0045 #include "dce/dce_hwseq.h"
0046 #include "dce100/dce100_hw_sequencer.h"
0047 #include "dce/dce_panel_cntl.h"
0048 
0049 #include "reg_helper.h"
0050 
0051 #include "dce/dce_10_0_d.h"
0052 #include "dce/dce_10_0_sh_mask.h"
0053 
0054 #include "dce/dce_dmcu.h"
0055 #include "dce/dce_aux.h"
0056 #include "dce/dce_abm.h"
0057 #include "dce/dce_i2c.h"
0058 
0059 #include "dce100_resource.h"
0060 
0061 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
0062 #include "gmc/gmc_8_2_d.h"
0063 #include "gmc/gmc_8_2_sh_mask.h"
0064 #endif
0065 
0066 #ifndef mmDP_DPHY_INTERNAL_CTRL
0067     #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
0068     #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
0069     #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
0070     #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
0071     #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
0072     #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
0073     #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
0074     #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
0075     #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
0076     #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
0077 #endif
0078 
0079 #ifndef mmBIOS_SCRATCH_2
0080     #define mmBIOS_SCRATCH_2 0x05CB
0081     #define mmBIOS_SCRATCH_3 0x05CC
0082     #define mmBIOS_SCRATCH_6 0x05CF
0083 #endif
0084 
0085 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
0086     #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
0087     #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
0088     #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
0089     #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
0090     #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
0091     #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
0092     #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
0093     #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
0094 #endif
0095 
0096 #ifndef mmDP_DPHY_FAST_TRAINING
0097     #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
0098     #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
0099     #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
0100     #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
0101     #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
0102     #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
0103     #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
0104     #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
0105 #endif
0106 
0107 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
0108     {
0109         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
0110         .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
0111     },
0112     {
0113         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
0114         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
0115     },
0116     {
0117         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
0118         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
0119     },
0120     {
0121         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
0122         .dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
0123     },
0124     {
0125         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
0126         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
0127     },
0128     {
0129         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
0130         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
0131     }
0132 };
0133 
0134 /* set register offset */
0135 #define SR(reg_name)\
0136     .reg_name = mm ## reg_name
0137 
0138 /* set register offset with instance */
0139 #define SRI(reg_name, block, id)\
0140     .reg_name = mm ## block ## id ## _ ## reg_name
0141 
0142 #define ipp_regs(id)\
0143 [id] = {\
0144         IPP_DCE100_REG_LIST_DCE_BASE(id)\
0145 }
0146 
0147 static const struct dce_ipp_registers ipp_regs[] = {
0148         ipp_regs(0),
0149         ipp_regs(1),
0150         ipp_regs(2),
0151         ipp_regs(3),
0152         ipp_regs(4),
0153         ipp_regs(5)
0154 };
0155 
0156 static const struct dce_ipp_shift ipp_shift = {
0157         IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0158 };
0159 
0160 static const struct dce_ipp_mask ipp_mask = {
0161         IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0162 };
0163 
0164 #define transform_regs(id)\
0165 [id] = {\
0166         XFM_COMMON_REG_LIST_DCE100(id)\
0167 }
0168 
0169 static const struct dce_transform_registers xfm_regs[] = {
0170         transform_regs(0),
0171         transform_regs(1),
0172         transform_regs(2),
0173         transform_regs(3),
0174         transform_regs(4),
0175         transform_regs(5)
0176 };
0177 
0178 static const struct dce_transform_shift xfm_shift = {
0179         XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
0180 };
0181 
0182 static const struct dce_transform_mask xfm_mask = {
0183         XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
0184 };
0185 
0186 #define aux_regs(id)\
0187 [id] = {\
0188     AUX_REG_LIST(id)\
0189 }
0190 
0191 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
0192         aux_regs(0),
0193         aux_regs(1),
0194         aux_regs(2),
0195         aux_regs(3),
0196         aux_regs(4),
0197         aux_regs(5)
0198 };
0199 
0200 #define hpd_regs(id)\
0201 [id] = {\
0202     HPD_REG_LIST(id)\
0203 }
0204 
0205 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
0206         hpd_regs(0),
0207         hpd_regs(1),
0208         hpd_regs(2),
0209         hpd_regs(3),
0210         hpd_regs(4),
0211         hpd_regs(5)
0212 };
0213 
0214 #define link_regs(id)\
0215 [id] = {\
0216     LE_DCE100_REG_LIST(id)\
0217 }
0218 
0219 static const struct dce110_link_enc_registers link_enc_regs[] = {
0220     link_regs(0),
0221     link_regs(1),
0222     link_regs(2),
0223     link_regs(3),
0224     link_regs(4),
0225     link_regs(5),
0226     link_regs(6),
0227 };
0228 
0229 #define stream_enc_regs(id)\
0230 [id] = {\
0231     SE_COMMON_REG_LIST_DCE_BASE(id),\
0232     .AFMT_CNTL = 0,\
0233 }
0234 
0235 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
0236     stream_enc_regs(0),
0237     stream_enc_regs(1),
0238     stream_enc_regs(2),
0239     stream_enc_regs(3),
0240     stream_enc_regs(4),
0241     stream_enc_regs(5),
0242     stream_enc_regs(6)
0243 };
0244 
0245 static const struct dce_stream_encoder_shift se_shift = {
0246         SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
0247 };
0248 
0249 static const struct dce_stream_encoder_mask se_mask = {
0250         SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
0251 };
0252 
0253 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
0254     { DCE_PANEL_CNTL_REG_LIST() }
0255 };
0256 
0257 static const struct dce_panel_cntl_shift panel_cntl_shift = {
0258     DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
0259 };
0260 
0261 static const struct dce_panel_cntl_mask panel_cntl_mask = {
0262     DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
0263 };
0264 
0265 #define opp_regs(id)\
0266 [id] = {\
0267     OPP_DCE_100_REG_LIST(id),\
0268 }
0269 
0270 static const struct dce_opp_registers opp_regs[] = {
0271     opp_regs(0),
0272     opp_regs(1),
0273     opp_regs(2),
0274     opp_regs(3),
0275     opp_regs(4),
0276     opp_regs(5)
0277 };
0278 
0279 static const struct dce_opp_shift opp_shift = {
0280     OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
0281 };
0282 
0283 static const struct dce_opp_mask opp_mask = {
0284     OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
0285 };
0286 #define aux_engine_regs(id)\
0287 [id] = {\
0288     AUX_COMMON_REG_LIST(id), \
0289     .AUX_RESET_MASK = 0 \
0290 }
0291 
0292 static const struct dce110_aux_registers aux_engine_regs[] = {
0293         aux_engine_regs(0),
0294         aux_engine_regs(1),
0295         aux_engine_regs(2),
0296         aux_engine_regs(3),
0297         aux_engine_regs(4),
0298         aux_engine_regs(5)
0299 };
0300 
0301 #define audio_regs(id)\
0302 [id] = {\
0303     AUD_COMMON_REG_LIST(id)\
0304 }
0305 
0306 static const struct dce_audio_registers audio_regs[] = {
0307     audio_regs(0),
0308     audio_regs(1),
0309     audio_regs(2),
0310     audio_regs(3),
0311     audio_regs(4),
0312     audio_regs(5),
0313     audio_regs(6),
0314 };
0315 
0316 static const struct dce_audio_shift audio_shift = {
0317         AUD_COMMON_MASK_SH_LIST(__SHIFT)
0318 };
0319 
0320 static const struct dce_audio_mask audio_mask = {
0321         AUD_COMMON_MASK_SH_LIST(_MASK)
0322 };
0323 
0324 #define clk_src_regs(id)\
0325 [id] = {\
0326     CS_COMMON_REG_LIST_DCE_100_110(id),\
0327 }
0328 
0329 static const struct dce110_clk_src_regs clk_src_regs[] = {
0330     clk_src_regs(0),
0331     clk_src_regs(1),
0332     clk_src_regs(2)
0333 };
0334 
0335 static const struct dce110_clk_src_shift cs_shift = {
0336         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0337 };
0338 
0339 static const struct dce110_clk_src_mask cs_mask = {
0340         CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0341 };
0342 
0343 static const struct dce_dmcu_registers dmcu_regs = {
0344         DMCU_DCE110_COMMON_REG_LIST()
0345 };
0346 
0347 static const struct dce_dmcu_shift dmcu_shift = {
0348         DMCU_MASK_SH_LIST_DCE110(__SHIFT)
0349 };
0350 
0351 static const struct dce_dmcu_mask dmcu_mask = {
0352         DMCU_MASK_SH_LIST_DCE110(_MASK)
0353 };
0354 
0355 static const struct dce_abm_registers abm_regs = {
0356         ABM_DCE110_COMMON_REG_LIST()
0357 };
0358 
0359 static const struct dce_abm_shift abm_shift = {
0360         ABM_MASK_SH_LIST_DCE110(__SHIFT)
0361 };
0362 
0363 static const struct dce_abm_mask abm_mask = {
0364         ABM_MASK_SH_LIST_DCE110(_MASK)
0365 };
0366 
0367 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
0368 
0369 static const struct bios_registers bios_regs = {
0370     .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
0371     .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
0372 };
0373 
0374 static const struct resource_caps res_cap = {
0375     .num_timing_generator = 6,
0376     .num_audio = 6,
0377     .num_stream_encoder = 6,
0378     .num_pll = 3,
0379     .num_ddc = 6,
0380 };
0381 
0382 static const struct dc_plane_cap plane_cap = {
0383     .type = DC_PLANE_TYPE_DCE_RGB,
0384 
0385     .pixel_format_support = {
0386             .argb8888 = true,
0387             .nv12 = false,
0388             .fp16 = true
0389     },
0390 
0391     .max_upscale_factor = {
0392             .argb8888 = 16000,
0393             .nv12 = 1,
0394             .fp16 = 1
0395     },
0396 
0397     .max_downscale_factor = {
0398             .argb8888 = 250,
0399             .nv12 = 1,
0400             .fp16 = 1
0401     }
0402 };
0403 
0404 #define CTX  ctx
0405 #define REG(reg) mm ## reg
0406 
0407 #ifndef mmCC_DC_HDMI_STRAPS
0408 #define mmCC_DC_HDMI_STRAPS 0x1918
0409 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
0410 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
0411 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
0412 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
0413 #endif
0414 
0415 static int map_transmitter_id_to_phy_instance(
0416     enum transmitter transmitter)
0417 {
0418     switch (transmitter) {
0419     case TRANSMITTER_UNIPHY_A:
0420         return 0;
0421     case TRANSMITTER_UNIPHY_B:
0422         return 1;
0423     case TRANSMITTER_UNIPHY_C:
0424         return 2;
0425     case TRANSMITTER_UNIPHY_D:
0426         return 3;
0427     case TRANSMITTER_UNIPHY_E:
0428         return 4;
0429     case TRANSMITTER_UNIPHY_F:
0430         return 5;
0431     case TRANSMITTER_UNIPHY_G:
0432         return 6;
0433     default:
0434         ASSERT(0);
0435         return 0;
0436     }
0437 }
0438 
0439 static void read_dce_straps(
0440     struct dc_context *ctx,
0441     struct resource_straps *straps)
0442 {
0443     REG_GET_2(CC_DC_HDMI_STRAPS,
0444             HDMI_DISABLE, &straps->hdmi_disable,
0445             AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
0446 
0447     REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
0448 }
0449 
0450 static struct audio *create_audio(
0451         struct dc_context *ctx, unsigned int inst)
0452 {
0453     return dce_audio_create(ctx, inst,
0454             &audio_regs[inst], &audio_shift, &audio_mask);
0455 }
0456 
0457 static struct timing_generator *dce100_timing_generator_create(
0458         struct dc_context *ctx,
0459         uint32_t instance,
0460         const struct dce110_timing_generator_offsets *offsets)
0461 {
0462     struct dce110_timing_generator *tg110 =
0463         kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
0464 
0465     if (!tg110)
0466         return NULL;
0467 
0468     dce110_timing_generator_construct(tg110, ctx, instance, offsets);
0469     return &tg110->base;
0470 }
0471 
0472 static struct stream_encoder *dce100_stream_encoder_create(
0473     enum engine_id eng_id,
0474     struct dc_context *ctx)
0475 {
0476     struct dce110_stream_encoder *enc110 =
0477         kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
0478 
0479     if (!enc110)
0480         return NULL;
0481 
0482     dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
0483                     &stream_enc_regs[eng_id], &se_shift, &se_mask);
0484     return &enc110->base;
0485 }
0486 
0487 #define SRII(reg_name, block, id)\
0488     .reg_name[id] = mm ## block ## id ## _ ## reg_name
0489 
0490 static const struct dce_hwseq_registers hwseq_reg = {
0491         HWSEQ_DCE10_REG_LIST()
0492 };
0493 
0494 static const struct dce_hwseq_shift hwseq_shift = {
0495         HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
0496 };
0497 
0498 static const struct dce_hwseq_mask hwseq_mask = {
0499         HWSEQ_DCE10_MASK_SH_LIST(_MASK)
0500 };
0501 
0502 static struct dce_hwseq *dce100_hwseq_create(
0503     struct dc_context *ctx)
0504 {
0505     struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
0506 
0507     if (hws) {
0508         hws->ctx = ctx;
0509         hws->regs = &hwseq_reg;
0510         hws->shifts = &hwseq_shift;
0511         hws->masks = &hwseq_mask;
0512     }
0513     return hws;
0514 }
0515 
0516 static const struct resource_create_funcs res_create_funcs = {
0517     .read_dce_straps = read_dce_straps,
0518     .create_audio = create_audio,
0519     .create_stream_encoder = dce100_stream_encoder_create,
0520     .create_hwseq = dce100_hwseq_create,
0521 };
0522 
0523 #define mi_inst_regs(id) { \
0524     MI_DCE8_REG_LIST(id), \
0525     .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
0526 }
0527 static const struct dce_mem_input_registers mi_regs[] = {
0528         mi_inst_regs(0),
0529         mi_inst_regs(1),
0530         mi_inst_regs(2),
0531         mi_inst_regs(3),
0532         mi_inst_regs(4),
0533         mi_inst_regs(5),
0534 };
0535 
0536 static const struct dce_mem_input_shift mi_shifts = {
0537         MI_DCE8_MASK_SH_LIST(__SHIFT),
0538         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
0539 };
0540 
0541 static const struct dce_mem_input_mask mi_masks = {
0542         MI_DCE8_MASK_SH_LIST(_MASK),
0543         .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
0544 };
0545 
0546 static const struct dce110_aux_registers_shift aux_shift = {
0547     DCE10_AUX_MASK_SH_LIST(__SHIFT)
0548 };
0549 
0550 static const struct dce110_aux_registers_mask aux_mask = {
0551     DCE10_AUX_MASK_SH_LIST(_MASK)
0552 };
0553 
0554 static struct mem_input *dce100_mem_input_create(
0555     struct dc_context *ctx,
0556     uint32_t inst)
0557 {
0558     struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
0559                            GFP_KERNEL);
0560 
0561     if (!dce_mi) {
0562         BREAK_TO_DEBUGGER();
0563         return NULL;
0564     }
0565 
0566     dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
0567     dce_mi->wa.single_head_rdreq_dmif_limit = 2;
0568     return &dce_mi->base;
0569 }
0570 
0571 static void dce100_transform_destroy(struct transform **xfm)
0572 {
0573     kfree(TO_DCE_TRANSFORM(*xfm));
0574     *xfm = NULL;
0575 }
0576 
0577 static struct transform *dce100_transform_create(
0578     struct dc_context *ctx,
0579     uint32_t inst)
0580 {
0581     struct dce_transform *transform =
0582         kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
0583 
0584     if (!transform)
0585         return NULL;
0586 
0587     dce_transform_construct(transform, ctx, inst,
0588                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
0589     return &transform->base;
0590 }
0591 
0592 static struct input_pixel_processor *dce100_ipp_create(
0593     struct dc_context *ctx, uint32_t inst)
0594 {
0595     struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
0596 
0597     if (!ipp) {
0598         BREAK_TO_DEBUGGER();
0599         return NULL;
0600     }
0601 
0602     dce_ipp_construct(ipp, ctx, inst,
0603             &ipp_regs[inst], &ipp_shift, &ipp_mask);
0604     return &ipp->base;
0605 }
0606 
0607 static const struct encoder_feature_support link_enc_feature = {
0608         .max_hdmi_deep_color = COLOR_DEPTH_121212,
0609         .max_hdmi_pixel_clock = 300000,
0610         .flags.bits.IS_HBR2_CAPABLE = true,
0611         .flags.bits.IS_TPS3_CAPABLE = true
0612 };
0613 
0614 static struct link_encoder *dce100_link_encoder_create(
0615     struct dc_context *ctx,
0616     const struct encoder_init_data *enc_init_data)
0617 {
0618     struct dce110_link_encoder *enc110 =
0619         kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
0620     int link_regs_id;
0621 
0622     if (!enc110)
0623         return NULL;
0624 
0625     link_regs_id =
0626         map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
0627 
0628     dce110_link_encoder_construct(enc110,
0629                       enc_init_data,
0630                       &link_enc_feature,
0631                       &link_enc_regs[link_regs_id],
0632                       &link_enc_aux_regs[enc_init_data->channel - 1],
0633                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
0634     return &enc110->base;
0635 }
0636 
0637 static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
0638 {
0639     struct dce_panel_cntl *panel_cntl =
0640         kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
0641 
0642     if (!panel_cntl)
0643         return NULL;
0644 
0645     dce_panel_cntl_construct(panel_cntl,
0646             init_data,
0647             &panel_cntl_regs[init_data->inst],
0648             &panel_cntl_shift,
0649             &panel_cntl_mask);
0650 
0651     return &panel_cntl->base;
0652 }
0653 
0654 static struct output_pixel_processor *dce100_opp_create(
0655     struct dc_context *ctx,
0656     uint32_t inst)
0657 {
0658     struct dce110_opp *opp =
0659         kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
0660 
0661     if (!opp)
0662         return NULL;
0663 
0664     dce110_opp_construct(opp,
0665                  ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
0666     return &opp->base;
0667 }
0668 
0669 static struct dce_aux *dce100_aux_engine_create(
0670     struct dc_context *ctx,
0671     uint32_t inst)
0672 {
0673     struct aux_engine_dce110 *aux_engine =
0674         kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
0675 
0676     if (!aux_engine)
0677         return NULL;
0678 
0679     dce110_aux_engine_construct(aux_engine, ctx, inst,
0680                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
0681                     &aux_engine_regs[inst],
0682                     &aux_mask,
0683                     &aux_shift,
0684                     ctx->dc->caps.extended_aux_timeout_support);
0685 
0686     return &aux_engine->base;
0687 }
0688 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
0689 
0690 static const struct dce_i2c_registers i2c_hw_regs[] = {
0691         i2c_inst_regs(1),
0692         i2c_inst_regs(2),
0693         i2c_inst_regs(3),
0694         i2c_inst_regs(4),
0695         i2c_inst_regs(5),
0696         i2c_inst_regs(6),
0697 };
0698 
0699 static const struct dce_i2c_shift i2c_shifts = {
0700         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
0701 };
0702 
0703 static const struct dce_i2c_mask i2c_masks = {
0704         I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
0705 };
0706 
0707 static struct dce_i2c_hw *dce100_i2c_hw_create(
0708     struct dc_context *ctx,
0709     uint32_t inst)
0710 {
0711     struct dce_i2c_hw *dce_i2c_hw =
0712         kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
0713 
0714     if (!dce_i2c_hw)
0715         return NULL;
0716 
0717     dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
0718                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
0719 
0720     return dce_i2c_hw;
0721 }
0722 static struct clock_source *dce100_clock_source_create(
0723     struct dc_context *ctx,
0724     struct dc_bios *bios,
0725     enum clock_source_id id,
0726     const struct dce110_clk_src_regs *regs,
0727     bool dp_clk_src)
0728 {
0729     struct dce110_clk_src *clk_src =
0730         kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
0731 
0732     if (!clk_src)
0733         return NULL;
0734 
0735     if (dce110_clk_src_construct(clk_src, ctx, bios, id,
0736             regs, &cs_shift, &cs_mask)) {
0737         clk_src->base.dp_clk_src = dp_clk_src;
0738         return &clk_src->base;
0739     }
0740 
0741     kfree(clk_src);
0742     BREAK_TO_DEBUGGER();
0743     return NULL;
0744 }
0745 
0746 static void dce100_clock_source_destroy(struct clock_source **clk_src)
0747 {
0748     kfree(TO_DCE110_CLK_SRC(*clk_src));
0749     *clk_src = NULL;
0750 }
0751 
0752 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
0753 {
0754     unsigned int i;
0755 
0756     for (i = 0; i < pool->base.pipe_count; i++) {
0757         if (pool->base.opps[i] != NULL)
0758             dce110_opp_destroy(&pool->base.opps[i]);
0759 
0760         if (pool->base.transforms[i] != NULL)
0761             dce100_transform_destroy(&pool->base.transforms[i]);
0762 
0763         if (pool->base.ipps[i] != NULL)
0764             dce_ipp_destroy(&pool->base.ipps[i]);
0765 
0766         if (pool->base.mis[i] != NULL) {
0767             kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
0768             pool->base.mis[i] = NULL;
0769         }
0770 
0771         if (pool->base.timing_generators[i] != NULL)    {
0772             kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
0773             pool->base.timing_generators[i] = NULL;
0774         }
0775     }
0776 
0777     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
0778         if (pool->base.engines[i] != NULL)
0779             dce110_engine_destroy(&pool->base.engines[i]);
0780         if (pool->base.hw_i2cs[i] != NULL) {
0781             kfree(pool->base.hw_i2cs[i]);
0782             pool->base.hw_i2cs[i] = NULL;
0783         }
0784         if (pool->base.sw_i2cs[i] != NULL) {
0785             kfree(pool->base.sw_i2cs[i]);
0786             pool->base.sw_i2cs[i] = NULL;
0787         }
0788     }
0789 
0790     for (i = 0; i < pool->base.stream_enc_count; i++) {
0791         if (pool->base.stream_enc[i] != NULL)
0792             kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
0793     }
0794 
0795     for (i = 0; i < pool->base.clk_src_count; i++) {
0796         if (pool->base.clock_sources[i] != NULL)
0797             dce100_clock_source_destroy(&pool->base.clock_sources[i]);
0798     }
0799 
0800     if (pool->base.dp_clock_source != NULL)
0801         dce100_clock_source_destroy(&pool->base.dp_clock_source);
0802 
0803     for (i = 0; i < pool->base.audio_count; i++)    {
0804         if (pool->base.audios[i] != NULL)
0805             dce_aud_destroy(&pool->base.audios[i]);
0806     }
0807 
0808     if (pool->base.abm != NULL)
0809                 dce_abm_destroy(&pool->base.abm);
0810 
0811     if (pool->base.dmcu != NULL)
0812             dce_dmcu_destroy(&pool->base.dmcu);
0813 
0814     if (pool->base.irqs != NULL)
0815         dal_irq_service_destroy(&pool->base.irqs);
0816 }
0817 
0818 static enum dc_status build_mapped_resource(
0819         const struct dc  *dc,
0820         struct dc_state *context,
0821         struct dc_stream_state *stream)
0822 {
0823     struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
0824 
0825     if (!pipe_ctx)
0826         return DC_ERROR_UNEXPECTED;
0827 
0828     dce110_resource_build_pipe_hw_param(pipe_ctx);
0829 
0830     resource_build_info_frame(pipe_ctx);
0831 
0832     return DC_OK;
0833 }
0834 
0835 static bool dce100_validate_bandwidth(
0836     struct dc  *dc,
0837     struct dc_state *context,
0838     bool fast_validate)
0839 {
0840     int i;
0841     bool at_least_one_pipe = false;
0842 
0843     for (i = 0; i < dc->res_pool->pipe_count; i++) {
0844         if (context->res_ctx.pipe_ctx[i].stream)
0845             at_least_one_pipe = true;
0846     }
0847 
0848     if (at_least_one_pipe) {
0849         /* TODO implement when needed but for now hardcode max value*/
0850         context->bw_ctx.bw.dce.dispclk_khz = 681000;
0851         context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
0852     } else {
0853         context->bw_ctx.bw.dce.dispclk_khz = 0;
0854         context->bw_ctx.bw.dce.yclk_khz = 0;
0855     }
0856 
0857     return true;
0858 }
0859 
0860 static bool dce100_validate_surface_sets(
0861         struct dc_state *context)
0862 {
0863     int i;
0864 
0865     for (i = 0; i < context->stream_count; i++) {
0866         if (context->stream_status[i].plane_count == 0)
0867             continue;
0868 
0869         if (context->stream_status[i].plane_count > 1)
0870             return false;
0871 
0872         if (context->stream_status[i].plane_states[0]->format
0873                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
0874             return false;
0875     }
0876 
0877     return true;
0878 }
0879 
0880 static enum dc_status dce100_validate_global(
0881         struct dc  *dc,
0882         struct dc_state *context)
0883 {
0884     if (!dce100_validate_surface_sets(context))
0885         return DC_FAIL_SURFACE_VALIDATE;
0886 
0887     return DC_OK;
0888 }
0889 
0890 enum dc_status dce100_add_stream_to_ctx(
0891         struct dc *dc,
0892         struct dc_state *new_ctx,
0893         struct dc_stream_state *dc_stream)
0894 {
0895     enum dc_status result = DC_ERROR_UNEXPECTED;
0896 
0897     result = resource_map_pool_resources(dc, new_ctx, dc_stream);
0898 
0899     if (result == DC_OK)
0900         result = resource_map_clock_resources(dc, new_ctx, dc_stream);
0901 
0902     if (result == DC_OK)
0903         result = build_mapped_resource(dc, new_ctx, dc_stream);
0904 
0905     return result;
0906 }
0907 
0908 static void dce100_destroy_resource_pool(struct resource_pool **pool)
0909 {
0910     struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
0911 
0912     dce100_resource_destruct(dce110_pool);
0913     kfree(dce110_pool);
0914     *pool = NULL;
0915 }
0916 
0917 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
0918 {
0919 
0920     if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
0921         return DC_OK;
0922 
0923     return DC_FAIL_SURFACE_VALIDATE;
0924 }
0925 
0926 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
0927         struct resource_context *res_ctx,
0928         const struct resource_pool *pool,
0929         struct dc_stream_state *stream)
0930 {
0931     int i;
0932     int j = -1;
0933     struct dc_link *link = stream->link;
0934 
0935     for (i = 0; i < pool->stream_enc_count; i++) {
0936         if (!res_ctx->is_stream_enc_acquired[i] &&
0937                 pool->stream_enc[i]) {
0938             /* Store first available for MST second display
0939              * in daisy chain use case
0940              */
0941             j = i;
0942             if (pool->stream_enc[i]->id ==
0943                     link->link_enc->preferred_engine)
0944                 return pool->stream_enc[i];
0945         }
0946     }
0947 
0948     /*
0949      * below can happen in cases when stream encoder is acquired:
0950      * 1) for second MST display in chain, so preferred engine already
0951      * acquired;
0952      * 2) for another link, which preferred engine already acquired by any
0953      * MST configuration.
0954      *
0955      * If signal is of DP type and preferred engine not found, return last available
0956      *
0957      * TODO - This is just a patch up and a generic solution is
0958      * required for non DP connectors.
0959      */
0960 
0961     if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
0962         return pool->stream_enc[j];
0963 
0964     return NULL;
0965 }
0966 
0967 static const struct resource_funcs dce100_res_pool_funcs = {
0968     .destroy = dce100_destroy_resource_pool,
0969     .link_enc_create = dce100_link_encoder_create,
0970     .panel_cntl_create = dce100_panel_cntl_create,
0971     .validate_bandwidth = dce100_validate_bandwidth,
0972     .validate_plane = dce100_validate_plane,
0973     .add_stream_to_ctx = dce100_add_stream_to_ctx,
0974     .validate_global = dce100_validate_global,
0975     .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
0976 };
0977 
0978 static bool dce100_resource_construct(
0979     uint8_t num_virtual_links,
0980     struct dc  *dc,
0981     struct dce110_resource_pool *pool)
0982 {
0983     unsigned int i;
0984     struct dc_context *ctx = dc->ctx;
0985     struct dc_bios *bp;
0986 
0987     ctx->dc_bios->regs = &bios_regs;
0988 
0989     pool->base.res_cap = &res_cap;
0990     pool->base.funcs = &dce100_res_pool_funcs;
0991     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
0992 
0993     bp = ctx->dc_bios;
0994 
0995     if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
0996         pool->base.dp_clock_source =
0997                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
0998 
0999         pool->base.clock_sources[0] =
1000                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1001         pool->base.clock_sources[1] =
1002                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1003         pool->base.clock_sources[2] =
1004                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1005         pool->base.clk_src_count = 3;
1006 
1007     } else {
1008         pool->base.dp_clock_source =
1009                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1010 
1011         pool->base.clock_sources[0] =
1012                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1013         pool->base.clock_sources[1] =
1014                 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1015         pool->base.clk_src_count = 2;
1016     }
1017 
1018     if (pool->base.dp_clock_source == NULL) {
1019         dm_error("DC: failed to create dp clock source!\n");
1020         BREAK_TO_DEBUGGER();
1021         goto res_create_fail;
1022     }
1023 
1024     for (i = 0; i < pool->base.clk_src_count; i++) {
1025         if (pool->base.clock_sources[i] == NULL) {
1026             dm_error("DC: failed to create clock sources!\n");
1027             BREAK_TO_DEBUGGER();
1028             goto res_create_fail;
1029         }
1030     }
1031 
1032     pool->base.dmcu = dce_dmcu_create(ctx,
1033             &dmcu_regs,
1034             &dmcu_shift,
1035             &dmcu_mask);
1036     if (pool->base.dmcu == NULL) {
1037         dm_error("DC: failed to create dmcu!\n");
1038         BREAK_TO_DEBUGGER();
1039         goto res_create_fail;
1040     }
1041 
1042     pool->base.abm = dce_abm_create(ctx,
1043                 &abm_regs,
1044                 &abm_shift,
1045                 &abm_mask);
1046     if (pool->base.abm == NULL) {
1047         dm_error("DC: failed to create abm!\n");
1048         BREAK_TO_DEBUGGER();
1049         goto res_create_fail;
1050     }
1051 
1052     {
1053         struct irq_service_init_data init_data;
1054         init_data.ctx = dc->ctx;
1055         pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1056         if (!pool->base.irqs)
1057             goto res_create_fail;
1058     }
1059 
1060     /*************************************************
1061     *  Resource + asic cap harcoding                *
1062     *************************************************/
1063     pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1064     pool->base.pipe_count = res_cap.num_timing_generator;
1065     pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1066     dc->caps.max_downscale_ratio = 200;
1067     dc->caps.i2c_speed_in_khz = 40;
1068     dc->caps.i2c_speed_in_khz = 40;
1069     dc->caps.max_cursor_size = 128;
1070     dc->caps.min_horizontal_blanking_period = 80;
1071     dc->caps.dual_link_dvi = true;
1072     dc->caps.disable_dp_clk_share = true;
1073     dc->caps.extended_aux_timeout_support = false;
1074 
1075     for (i = 0; i < pool->base.pipe_count; i++) {
1076         pool->base.timing_generators[i] =
1077             dce100_timing_generator_create(
1078                 ctx,
1079                 i,
1080                 &dce100_tg_offsets[i]);
1081         if (pool->base.timing_generators[i] == NULL) {
1082             BREAK_TO_DEBUGGER();
1083             dm_error("DC: failed to create tg!\n");
1084             goto res_create_fail;
1085         }
1086 
1087         pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1088         if (pool->base.mis[i] == NULL) {
1089             BREAK_TO_DEBUGGER();
1090             dm_error(
1091                 "DC: failed to create memory input!\n");
1092             goto res_create_fail;
1093         }
1094 
1095         pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1096         if (pool->base.ipps[i] == NULL) {
1097             BREAK_TO_DEBUGGER();
1098             dm_error(
1099                 "DC: failed to create input pixel processor!\n");
1100             goto res_create_fail;
1101         }
1102 
1103         pool->base.transforms[i] = dce100_transform_create(ctx, i);
1104         if (pool->base.transforms[i] == NULL) {
1105             BREAK_TO_DEBUGGER();
1106             dm_error(
1107                 "DC: failed to create transform!\n");
1108             goto res_create_fail;
1109         }
1110 
1111         pool->base.opps[i] = dce100_opp_create(ctx, i);
1112         if (pool->base.opps[i] == NULL) {
1113             BREAK_TO_DEBUGGER();
1114             dm_error(
1115                 "DC: failed to create output pixel processor!\n");
1116             goto res_create_fail;
1117         }
1118     }
1119 
1120     for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1121         pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1122         if (pool->base.engines[i] == NULL) {
1123             BREAK_TO_DEBUGGER();
1124             dm_error(
1125                 "DC:failed to create aux engine!!\n");
1126             goto res_create_fail;
1127         }
1128         pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1129         if (pool->base.hw_i2cs[i] == NULL) {
1130             BREAK_TO_DEBUGGER();
1131             dm_error(
1132                 "DC:failed to create i2c engine!!\n");
1133             goto res_create_fail;
1134         }
1135         pool->base.sw_i2cs[i] = NULL;
1136     }
1137 
1138     dc->caps.max_planes =  pool->base.pipe_count;
1139 
1140     for (i = 0; i < dc->caps.max_planes; ++i)
1141         dc->caps.planes[i] = plane_cap;
1142 
1143     if (!resource_construct(num_virtual_links, dc, &pool->base,
1144             &res_create_funcs))
1145         goto res_create_fail;
1146 
1147     /* Create hardware sequencer */
1148     dce100_hw_sequencer_construct(dc);
1149     return true;
1150 
1151 res_create_fail:
1152     dce100_resource_destruct(pool);
1153 
1154     return false;
1155 }
1156 
1157 struct resource_pool *dce100_create_resource_pool(
1158     uint8_t num_virtual_links,
1159     struct dc  *dc)
1160 {
1161     struct dce110_resource_pool *pool =
1162         kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1163 
1164     if (!pool)
1165         return NULL;
1166 
1167     if (dce100_resource_construct(num_virtual_links, dc, pool))
1168         return &pool->base;
1169 
1170     kfree(pool);
1171     BREAK_TO_DEBUGGER();
1172     return NULL;
1173 }
1174
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