dc/dce100/dce100_hw_sequencer.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #include "dm_services.h"
0026 #include "dc.h"
0027 #include "core_types.h"
0028 #include "clk_mgr.h"
0029 #include "dce100_hw_sequencer.h"
0030 #include "resource.h"
0031
0032 #include "dce110/dce110_hw_sequencer.h"
0033
0034 /* include DCE10 register header files */
0035 #include "dce/dce_10_0_d.h"
0036 #include "dce/dce_10_0_sh_mask.h"
0037
0038 struct dce100_hw_seq_reg_offsets {
0039     uint32_t blnd;
0040     uint32_t crtc;
0041 };
0042
0043 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
0044 {
0045     .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0046 },
0047 {
0048     .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0049 },
0050 {
0051     .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0052 },
0053 {
0054     .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0055 },
0056 {
0057     .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0058 },
0059 {
0060     .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
0061 }
0062 };
0063
0064 #define HW_REG_CRTC(reg, id)\
0065     (reg + reg_offsets[id].crtc)
0066
0067 /*******************************************************************************
0068  * Private definitions
0069  ******************************************************************************/
0070 /***************************PIPE_CONTROL***********************************/
0071
0072 bool dce100_enable_display_power_gating(
0073     struct dc *dc,
0074     uint8_t controller_id,
0075     struct dc_bios *dcb,
0076     enum pipe_gating_control power_gating)
0077 {
0078     enum bp_result bp_result = BP_RESULT_OK;
0079     enum bp_pipe_control_action cntl;
0080     struct dc_context *ctx = dc->ctx;
0081
0082     if (power_gating == PIPE_GATING_CONTROL_INIT)
0083         cntl = ASIC_PIPE_INIT;
0084     else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
0085         cntl = ASIC_PIPE_ENABLE;
0086     else
0087         cntl = ASIC_PIPE_DISABLE;
0088
0089     if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
0090
0091         bp_result = dcb->funcs->enable_disp_power_gating(
0092                         dcb, controller_id + 1, cntl);
0093
0094         /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
0095          * by default when command table is called
0096          */
0097         dm_write_reg(ctx,
0098             HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
0099             0);
0100     }
0101
0102     if (bp_result == BP_RESULT_OK)
0103         return true;
0104     else
0105         return false;
0106 }
0107
0108 void dce100_prepare_bandwidth(
0109         struct dc *dc,
0110         struct dc_state *context)
0111 {
0112     dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
0113
0114     dc->clk_mgr->funcs->update_clocks(
0115             dc->clk_mgr,
0116             context,
0117             false);
0118 }
0119
0120 void dce100_optimize_bandwidth(
0121         struct dc *dc,
0122         struct dc_state *context)
0123 {
0124     dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
0125
0126     dc->clk_mgr->funcs->update_clocks(
0127             dc->clk_mgr,
0128             context,
0129             true);
0130 }
0131
0132 /**************************************************************************/
0133
0134 void dce100_hw_sequencer_construct(struct dc *dc)
0135 {
0136     dce110_hw_sequencer_construct(dc);
0137
0138     dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
0139     dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
0140     dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
0141 }
0142