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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2012-16 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #ifndef _DCE_DCE_TRANSFORM_H_
0027 #define _DCE_DCE_TRANSFORM_H_
0028 
0029 
0030 #include "transform.h"
0031 
0032 #define TO_DCE_TRANSFORM(transform)\
0033     container_of(transform, struct dce_transform, base)
0034 
0035 #define LB_TOTAL_NUMBER_OF_ENTRIES 1712
0036 #define LB_BITS_PER_ENTRY 144
0037 
0038 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \
0039     SRI(LB_DATA_FORMAT, LB, id), \
0040     SRI(GAMUT_REMAP_CONTROL, DCP, id), \
0041     SRI(GAMUT_REMAP_C11_C12, DCP, id), \
0042     SRI(GAMUT_REMAP_C13_C14, DCP, id), \
0043     SRI(GAMUT_REMAP_C21_C22, DCP, id), \
0044     SRI(GAMUT_REMAP_C23_C24, DCP, id), \
0045     SRI(GAMUT_REMAP_C31_C32, DCP, id), \
0046     SRI(GAMUT_REMAP_C33_C34, DCP, id), \
0047     SRI(OUTPUT_CSC_C11_C12, DCP, id), \
0048     SRI(OUTPUT_CSC_C13_C14, DCP, id), \
0049     SRI(OUTPUT_CSC_C21_C22, DCP, id), \
0050     SRI(OUTPUT_CSC_C23_C24, DCP, id), \
0051     SRI(OUTPUT_CSC_C31_C32, DCP, id), \
0052     SRI(OUTPUT_CSC_C33_C34, DCP, id), \
0053     SRI(OUTPUT_CSC_CONTROL, DCP, id), \
0054     SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
0055     SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
0056     SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
0057     SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
0058     SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
0059     SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
0060     SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
0061     SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
0062     SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
0063     SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
0064     SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
0065     SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
0066     SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
0067     SRI(REGAMMA_LUT_INDEX, DCP, id), \
0068     SRI(REGAMMA_LUT_DATA, DCP, id), \
0069     SRI(REGAMMA_CONTROL, DCP, id), \
0070     SRI(DENORM_CONTROL, DCP, id), \
0071     SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
0072     SRI(OUT_ROUND_CONTROL, DCP, id), \
0073     SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
0074     SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
0075     SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
0076     SRI(SCL_MODE, SCL, id), \
0077     SRI(SCL_TAP_CONTROL, SCL, id), \
0078     SRI(SCL_CONTROL, SCL, id), \
0079     SRI(SCL_BYPASS_CONTROL, SCL, id), \
0080     SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
0081     SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
0082     SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
0083     SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
0084     SRI(SCL_COEF_RAM_SELECT, SCL, id), \
0085     SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
0086     SRI(VIEWPORT_START, SCL, id), \
0087     SRI(VIEWPORT_SIZE, SCL, id), \
0088     SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
0089     SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
0090     SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
0091     SRI(SCL_VERT_FILTER_INIT, SCL, id), \
0092     SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
0093     SRI(LB_MEMORY_CTRL, LB, id), \
0094     SRI(SCL_UPDATE, SCL, id), \
0095     SRI(SCL_F_SHARP_CONTROL, SCL, id)
0096 
0097 #define XFM_COMMON_REG_LIST_DCE80(id) \
0098     XFM_COMMON_REG_LIST_DCE_BASE(id), \
0099     SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
0100 
0101 #define XFM_COMMON_REG_LIST_DCE100(id) \
0102     XFM_COMMON_REG_LIST_DCE_BASE(id), \
0103     SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
0104     SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
0105 
0106 #define XFM_COMMON_REG_LIST_DCE110(id) \
0107     XFM_COMMON_REG_LIST_DCE_BASE(id), \
0108     SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
0109     SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
0110 
0111 #if defined(CONFIG_DRM_AMD_DC_SI)
0112 #define XFM_COMMON_REG_LIST_DCE60_BASE(id) \
0113     SRI(DATA_FORMAT, LB, id), \
0114     SRI(GAMUT_REMAP_CONTROL, DCP, id), \
0115     SRI(GAMUT_REMAP_C11_C12, DCP, id), \
0116     SRI(GAMUT_REMAP_C13_C14, DCP, id), \
0117     SRI(GAMUT_REMAP_C21_C22, DCP, id), \
0118     SRI(GAMUT_REMAP_C23_C24, DCP, id), \
0119     SRI(GAMUT_REMAP_C31_C32, DCP, id), \
0120     SRI(GAMUT_REMAP_C33_C34, DCP, id), \
0121     SRI(OUTPUT_CSC_C11_C12, DCP, id), \
0122     SRI(OUTPUT_CSC_C13_C14, DCP, id), \
0123     SRI(OUTPUT_CSC_C21_C22, DCP, id), \
0124     SRI(OUTPUT_CSC_C23_C24, DCP, id), \
0125     SRI(OUTPUT_CSC_C31_C32, DCP, id), \
0126     SRI(OUTPUT_CSC_C33_C34, DCP, id), \
0127     SRI(OUTPUT_CSC_CONTROL, DCP, id), \
0128     SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
0129     SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
0130     SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
0131     SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
0132     SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
0133     SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
0134     SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
0135     SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
0136     SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
0137     SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
0138     SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
0139     SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
0140     SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
0141     SRI(REGAMMA_LUT_INDEX, DCP, id), \
0142     SRI(REGAMMA_LUT_DATA, DCP, id), \
0143     SRI(REGAMMA_CONTROL, DCP, id), \
0144     SRI(DENORM_CONTROL, DCP, id), \
0145     SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
0146     SRI(OUT_ROUND_CONTROL, DCP, id), \
0147     SRI(SCL_TAP_CONTROL, SCL, id), \
0148     SRI(SCL_CONTROL, SCL, id), \
0149     SRI(SCL_BYPASS_CONTROL, SCL, id), \
0150     SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
0151     SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
0152     SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
0153     SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
0154     SRI(SCL_COEF_RAM_SELECT, SCL, id), \
0155     SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
0156     SRI(VIEWPORT_START, SCL, id), \
0157     SRI(VIEWPORT_SIZE, SCL, id), \
0158     SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
0159     SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
0160     SRI(SCL_VERT_FILTER_INIT, SCL, id), \
0161     SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
0162     SRI(DC_LB_MEMORY_SPLIT, LB, id), \
0163     SRI(DC_LB_MEM_SIZE, LB, id), \
0164     SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
0165     SRI(SCL_UPDATE, SCL, id), \
0166     SRI(SCL_F_SHARP_CONTROL, SCL, id)
0167 
0168 #define XFM_COMMON_REG_LIST_DCE60(id) \
0169     XFM_COMMON_REG_LIST_DCE60_BASE(id), \
0170     SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
0171 #endif
0172 
0173 #define XFM_SF(reg_name, field_name, post_fix)\
0174     .field_name = reg_name ## __ ## field_name ## post_fix
0175 
0176 #define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0177     XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
0178     XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
0179     XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
0180     XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
0181     XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
0182     XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
0183     XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
0184     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
0185     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
0186     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
0187     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
0188     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
0189     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
0190     XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
0191     XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
0192     XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
0193     XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
0194     XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
0195     XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
0196     XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
0197     XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
0198     XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
0199     XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
0200     XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
0201     XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
0202     XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
0203     XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
0204     XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
0205     XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
0206     XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
0207     XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
0208     XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
0209     XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
0210     XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
0211     XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
0212     XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
0213     XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
0214     XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
0215     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0216     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0217     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0218     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0219     XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
0220     XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
0221     XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
0222     XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
0223     XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
0224     XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
0225     XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
0226     XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
0227     XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
0228     XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
0229     XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
0230     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
0231     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
0232     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
0233     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
0234     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
0235     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
0236     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
0237     XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
0238     XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
0239     XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
0240     XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
0241     XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
0242     XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
0243     XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
0244     XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
0245     XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
0246     XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
0247     XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
0248     XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
0249     XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
0250     XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
0251     XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
0252     XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
0253 
0254 #define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \
0255     XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0256     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
0257     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
0258     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
0259 
0260 #define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
0261     XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0262     XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
0263     XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
0264     XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
0265     XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
0266     XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
0267     XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
0268 
0269 #if defined(CONFIG_DRM_AMD_DC_SI)
0270 #define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \
0271     XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh), \
0272     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
0273     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
0274     OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
0275 
0276 #define XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
0277     XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
0278     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
0279     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
0280     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
0281     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
0282     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
0283     XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
0284     XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
0285     XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \
0286     XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
0287     XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
0288     XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
0289     XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
0290     XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
0291     XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
0292     XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
0293     XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
0294     XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
0295     XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
0296     XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
0297     XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
0298     XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
0299     XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
0300     XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
0301     XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
0302     XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
0303     XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
0304     XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
0305     XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
0306     XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
0307     XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
0308     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0309     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0310     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0311     XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0312     XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
0313     XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
0314     XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
0315     XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
0316     XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
0317     XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
0318     XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
0319     XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
0320     XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
0321     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
0322     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
0323     XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
0324     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
0325     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
0326     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
0327     XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
0328     XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
0329     XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
0330     XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
0331     XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
0332     XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
0333     XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
0334     XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_INT_RGB_Y, mask_sh), \
0335     XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_FRAC_RGB_Y, mask_sh), \
0336     XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_INT_CBCR, mask_sh), \
0337     XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_FRAC_CBCR, mask_sh), \
0338     XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
0339     XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
0340     XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_FILTER_PICK_NEAREST, mask_sh), \
0341     XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_FILTER_PICK_NEAREST, mask_sh), \
0342     XFM_SF(DC_LB_MEMORY_SPLIT, DC_LB_MEMORY_CONFIG, mask_sh), \
0343     XFM_SF(DC_LB_MEM_SIZE, DC_LB_MEM_SIZE, mask_sh)
0344 #endif
0345 
0346 #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
0347     XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
0348     XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
0349     XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
0350     XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
0351     XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
0352     XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
0353     XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
0354     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
0355     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
0356     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
0357     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
0358     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
0359     XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
0360     XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \
0361     XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
0362     XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
0363     XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
0364     XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
0365     XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
0366     XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
0367     XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
0368     XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
0369     XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
0370     XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
0371     XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
0372     XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
0373     XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
0374     XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
0375     XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
0376     XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
0377     XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
0378     XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
0379     XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
0380     XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
0381     XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
0382     XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
0383     XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
0384     XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
0385     XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
0386     XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
0387     XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
0388     XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
0389     XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
0390     XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
0391     XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
0392     XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
0393     XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
0394     XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
0395     XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
0396     XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
0397     XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
0398     XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
0399     XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
0400     XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
0401     XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
0402     XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
0403     XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
0404     XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
0405     XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
0406     XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
0407     XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
0408     XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
0409     XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
0410     XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
0411     XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
0412     XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
0413     XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
0414     XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
0415     XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
0416     XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
0417     XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
0418     XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
0419     XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
0420     XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
0421     XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
0422     XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \
0423     XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
0424     XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
0425     XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
0426     XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
0427     XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
0428 
0429 #define XFM_REG_FIELD_LIST(type) \
0430     type OUT_CLAMP_MIN_B_CB; \
0431     type OUT_CLAMP_MAX_B_CB; \
0432     type OUT_CLAMP_MIN_G_Y; \
0433     type OUT_CLAMP_MAX_G_Y; \
0434     type OUT_CLAMP_MIN_R_CR; \
0435     type OUT_CLAMP_MAX_R_CR; \
0436     type OUT_ROUND_TRUNC_MODE; \
0437     type DCP_SPATIAL_DITHER_EN; \
0438     type DCP_SPATIAL_DITHER_MODE; \
0439     type DCP_SPATIAL_DITHER_DEPTH; \
0440     type DCP_FRAME_RANDOM_ENABLE; \
0441     type DCP_RGB_RANDOM_ENABLE; \
0442     type DCP_HIGHPASS_RANDOM_ENABLE; \
0443     type DENORM_MODE; \
0444     type INTERLEAVE_EN; \
0445     type PIXEL_DEPTH; \
0446     type PIXEL_EXPAN_MODE; \
0447     type GAMUT_REMAP_C11; \
0448     type GAMUT_REMAP_C12; \
0449     type GAMUT_REMAP_C13; \
0450     type GAMUT_REMAP_C14; \
0451     type GAMUT_REMAP_C21; \
0452     type GAMUT_REMAP_C22; \
0453     type GAMUT_REMAP_C23; \
0454     type GAMUT_REMAP_C24; \
0455     type GAMUT_REMAP_C31; \
0456     type GAMUT_REMAP_C32; \
0457     type GAMUT_REMAP_C33; \
0458     type GAMUT_REMAP_C34; \
0459     type GRPH_GAMUT_REMAP_MODE; \
0460     type OUTPUT_CSC_C11; \
0461     type OUTPUT_CSC_C12; \
0462     type OUTPUT_CSC_GRPH_MODE; \
0463     type DCP_REGAMMA_MEM_PWR_DIS; \
0464     type DCP_LUT_MEM_PWR_DIS; \
0465     type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
0466     type DCP_LUT_LIGHT_SLEEP_DIS; \
0467     type REGAMMA_CNTLA_EXP_REGION_START; \
0468     type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
0469     type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
0470     type REGAMMA_CNTLA_EXP_REGION_END; \
0471     type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
0472     type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
0473     type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
0474     type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
0475     type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
0476     type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
0477     type DCP_REGAMMA_MEM_PWR_STATE; \
0478     type REGAMMA_LUT_MEM_PWR_STATE; \
0479     type REGAMMA_LUT_WRITE_EN_MASK; \
0480     type GRPH_REGAMMA_MODE; \
0481     type SCL_MODE; \
0482     type SCL_BYPASS_MODE; \
0483     type SCL_PSCL_EN; \
0484     type SCL_H_NUM_OF_TAPS; \
0485     type SCL_V_NUM_OF_TAPS; \
0486     type SCL_BOUNDARY_MODE; \
0487     type EXT_OVERSCAN_LEFT; \
0488     type EXT_OVERSCAN_RIGHT; \
0489     type EXT_OVERSCAN_TOP; \
0490     type EXT_OVERSCAN_BOTTOM; \
0491     type SCL_COEFF_MEM_PWR_DIS; \
0492     type SCL_COEFF_MEM_PWR_STATE; \
0493     type SCL_C_RAM_FILTER_TYPE; \
0494     type SCL_C_RAM_PHASE; \
0495     type SCL_C_RAM_TAP_PAIR_IDX; \
0496     type SCL_C_RAM_EVEN_TAP_COEF_EN; \
0497     type SCL_C_RAM_EVEN_TAP_COEF; \
0498     type SCL_C_RAM_ODD_TAP_COEF_EN; \
0499     type SCL_C_RAM_ODD_TAP_COEF; \
0500     type VIEWPORT_X_START; \
0501     type VIEWPORT_Y_START; \
0502     type VIEWPORT_HEIGHT; \
0503     type VIEWPORT_WIDTH; \
0504     type SCL_H_SCALE_RATIO; \
0505     type SCL_V_SCALE_RATIO; \
0506     type SCL_H_INIT_INT; \
0507     type SCL_H_INIT_FRAC; \
0508     type SCL_H_INIT_INT_RGB_Y; \
0509     type SCL_H_INIT_FRAC_RGB_Y; \
0510     type SCL_H_INIT_INT_CBCR; \
0511     type SCL_H_INIT_FRAC_CBCR; \
0512     type SCL_V_INIT_INT; \
0513     type SCL_V_INIT_FRAC; \
0514     type DC_LB_MEMORY_CONFIG; \
0515     type DC_LB_MEM_SIZE; \
0516     type LB_MEMORY_CONFIG; \
0517     type LB_MEMORY_SIZE; \
0518     type SCL_V_2TAP_HARDCODE_COEF_EN; \
0519     type SCL_H_2TAP_HARDCODE_COEF_EN; \
0520     type SCL_V_FILTER_PICK_NEAREST; \
0521     type SCL_H_FILTER_PICK_NEAREST; \
0522     type SCL_COEF_UPDATE_COMPLETE; \
0523     type ALPHA_EN
0524 
0525 struct dce_transform_shift {
0526     XFM_REG_FIELD_LIST(uint8_t);
0527 };
0528 
0529 struct dce_transform_mask {
0530     XFM_REG_FIELD_LIST(uint32_t);
0531 };
0532 
0533 struct dce_transform_registers {
0534 #if defined(CONFIG_DRM_AMD_DC_SI)
0535     uint32_t DATA_FORMAT;
0536 #endif
0537     uint32_t LB_DATA_FORMAT;
0538     uint32_t GAMUT_REMAP_CONTROL;
0539     uint32_t GAMUT_REMAP_C11_C12;
0540     uint32_t GAMUT_REMAP_C13_C14;
0541     uint32_t GAMUT_REMAP_C21_C22;
0542     uint32_t GAMUT_REMAP_C23_C24;
0543     uint32_t GAMUT_REMAP_C31_C32;
0544     uint32_t GAMUT_REMAP_C33_C34;
0545     uint32_t OUTPUT_CSC_C11_C12;
0546     uint32_t OUTPUT_CSC_C13_C14;
0547     uint32_t OUTPUT_CSC_C21_C22;
0548     uint32_t OUTPUT_CSC_C23_C24;
0549     uint32_t OUTPUT_CSC_C31_C32;
0550     uint32_t OUTPUT_CSC_C33_C34;
0551     uint32_t OUTPUT_CSC_CONTROL;
0552     uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
0553     uint32_t REGAMMA_CNTLA_START_CNTL;
0554     uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
0555     uint32_t REGAMMA_CNTLA_END_CNTL1;
0556     uint32_t REGAMMA_CNTLA_END_CNTL2;
0557     uint32_t REGAMMA_CNTLA_REGION_0_1;
0558     uint32_t REGAMMA_CNTLA_REGION_2_3;
0559     uint32_t REGAMMA_CNTLA_REGION_4_5;
0560     uint32_t REGAMMA_CNTLA_REGION_6_7;
0561     uint32_t REGAMMA_CNTLA_REGION_8_9;
0562     uint32_t REGAMMA_CNTLA_REGION_10_11;
0563     uint32_t REGAMMA_CNTLA_REGION_12_13;
0564     uint32_t REGAMMA_CNTLA_REGION_14_15;
0565     uint32_t REGAMMA_LUT_WRITE_EN_MASK;
0566     uint32_t REGAMMA_LUT_INDEX;
0567     uint32_t REGAMMA_LUT_DATA;
0568     uint32_t REGAMMA_CONTROL;
0569     uint32_t DENORM_CONTROL;
0570     uint32_t DCP_SPATIAL_DITHER_CNTL;
0571     uint32_t OUT_ROUND_CONTROL;
0572     uint32_t OUT_CLAMP_CONTROL_R_CR;
0573     uint32_t OUT_CLAMP_CONTROL_G_Y;
0574     uint32_t OUT_CLAMP_CONTROL_B_CB;
0575     uint32_t SCL_MODE;
0576     uint32_t SCL_TAP_CONTROL;
0577     uint32_t SCL_CONTROL;
0578     uint32_t SCL_BYPASS_CONTROL;
0579     uint32_t EXT_OVERSCAN_LEFT_RIGHT;
0580     uint32_t EXT_OVERSCAN_TOP_BOTTOM;
0581     uint32_t SCL_VERT_FILTER_CONTROL;
0582     uint32_t SCL_HORZ_FILTER_CONTROL;
0583     uint32_t DCFE_MEM_PWR_CTRL;
0584     uint32_t DCFE_MEM_PWR_STATUS;
0585     uint32_t SCL_COEF_RAM_SELECT;
0586     uint32_t SCL_COEF_RAM_TAP_DATA;
0587     uint32_t VIEWPORT_START;
0588     uint32_t VIEWPORT_SIZE;
0589     uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
0590     uint32_t SCL_VERT_FILTER_SCALE_RATIO;
0591     uint32_t SCL_HORZ_FILTER_INIT;
0592 #if defined(CONFIG_DRM_AMD_DC_SI)
0593     uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;
0594     uint32_t SCL_HORZ_FILTER_INIT_CHROMA;
0595 #endif
0596     uint32_t SCL_VERT_FILTER_INIT;
0597     uint32_t SCL_AUTOMATIC_MODE_CONTROL;
0598 #if defined(CONFIG_DRM_AMD_DC_SI)
0599     uint32_t DC_LB_MEMORY_SPLIT;
0600     uint32_t DC_LB_MEM_SIZE;
0601 #endif
0602     uint32_t LB_MEMORY_CTRL;
0603     uint32_t SCL_UPDATE;
0604     uint32_t SCL_F_SHARP_CONTROL;
0605 };
0606 
0607 struct init_int_and_frac {
0608     uint32_t integer;
0609     uint32_t fraction;
0610 };
0611 
0612 struct scl_ratios_inits {
0613     uint32_t h_int_scale_ratio;
0614     uint32_t v_int_scale_ratio;
0615     struct init_int_and_frac h_init;
0616     struct init_int_and_frac v_init;
0617 };
0618 
0619 #if defined(CONFIG_DRM_AMD_DC_SI)
0620 struct sclh_ratios_inits {
0621     uint32_t h_int_scale_ratio;
0622     uint32_t v_int_scale_ratio;
0623     struct init_int_and_frac h_init_luma;
0624     struct init_int_and_frac h_init_chroma;
0625     struct init_int_and_frac v_init;
0626 };
0627 #endif
0628 
0629 enum ram_filter_type {
0630     FILTER_TYPE_RGB_Y_VERTICAL  = 0, /* 0 - RGB/Y Vertical filter */
0631     FILTER_TYPE_CBCR_VERTICAL   = 1, /* 1 - CbCr  Vertical filter */
0632     FILTER_TYPE_RGB_Y_HORIZONTAL    = 2, /* 1 - RGB/Y Horizontal filter */
0633     FILTER_TYPE_CBCR_HORIZONTAL = 3, /* 3 - CbCr  Horizontal filter */
0634     FILTER_TYPE_ALPHA_VERTICAL  = 4, /* 4 - Alpha Vertical filter. */
0635     FILTER_TYPE_ALPHA_HORIZONTAL    = 5, /* 5 - Alpha Horizontal filter. */
0636 };
0637 
0638 struct dce_transform {
0639     struct transform base;
0640     const struct dce_transform_registers *regs;
0641     const struct dce_transform_shift *xfm_shift;
0642     const struct dce_transform_mask *xfm_mask;
0643 
0644     const uint16_t *filter_v;
0645     const uint16_t *filter_h;
0646     const uint16_t *filter_v_c;
0647     const uint16_t *filter_h_c;
0648     int lb_pixel_depth_supported;
0649     int lb_memory_size;
0650     int lb_bits_per_entry;
0651     bool prescaler_on;
0652 };
0653 
0654 void dce_transform_construct(struct dce_transform *xfm_dce,
0655     struct dc_context *ctx,
0656     uint32_t inst,
0657     const struct dce_transform_registers *regs,
0658     const struct dce_transform_shift *xfm_shift,
0659     const struct dce_transform_mask *xfm_mask);
0660 
0661 #if defined(CONFIG_DRM_AMD_DC_SI)
0662 void dce60_transform_construct(struct dce_transform *xfm_dce,
0663     struct dc_context *ctx,
0664     uint32_t inst,
0665     const struct dce_transform_registers *regs,
0666     const struct dce_transform_shift *xfm_shift,
0667     const struct dce_transform_mask *xfm_mask);
0668 #endif
0669 
0670 bool dce_transform_get_optimal_number_of_taps(
0671     struct transform *xfm,
0672     struct scaler_data *scl_data,
0673     const struct scaling_taps *in_taps);
0674 
0675 void dce110_opp_set_csc_adjustment(
0676     struct transform *xfm,
0677     const struct out_csc_color_matrix *tbl_entry);
0678 
0679 void dce110_opp_set_csc_default(
0680     struct transform *xfm,
0681     const struct default_adjustment *default_adjust);
0682 
0683 /* REGAMMA RELATED */
0684 void dce110_opp_power_on_regamma_lut(
0685     struct transform *xfm,
0686     bool power_on);
0687 
0688 void dce110_opp_program_regamma_pwl(
0689     struct transform *xfm,
0690     const struct pwl_params *params);
0691 
0692 void dce110_opp_set_regamma_mode(struct transform *xfm,
0693         enum opp_regamma mode);
0694 
0695 #endif /* _DCE_DCE_TRANSFORM_H_ */
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