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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #ifndef __DC_STREAM_ENCODER_DCE110_H__
0027 #define __DC_STREAM_ENCODER_DCE110_H__
0028 
0029 #include "stream_encoder.h"
0030 
0031 #define DCE110STRENC_FROM_STRENC(stream_encoder)\
0032     container_of(stream_encoder, struct dce110_stream_encoder, base)
0033 
0034 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
0035     #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
0036     #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
0037     #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
0038     #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
0039 #endif
0040 
0041 
0042 #define SE_COMMON_REG_LIST_DCE_BASE(id) \
0043     SE_COMMON_REG_LIST_BASE(id),\
0044     SRI(AFMT_AVI_INFO0, DIG, id), \
0045     SRI(AFMT_AVI_INFO1, DIG, id), \
0046     SRI(AFMT_AVI_INFO2, DIG, id), \
0047     SRI(AFMT_AVI_INFO3, DIG, id)
0048 
0049 #define SE_COMMON_REG_LIST_BASE(id) \
0050     SRI(AFMT_GENERIC_0, DIG, id), \
0051     SRI(AFMT_GENERIC_1, DIG, id), \
0052     SRI(AFMT_GENERIC_2, DIG, id), \
0053     SRI(AFMT_GENERIC_3, DIG, id), \
0054     SRI(AFMT_GENERIC_4, DIG, id), \
0055     SRI(AFMT_GENERIC_5, DIG, id), \
0056     SRI(AFMT_GENERIC_6, DIG, id), \
0057     SRI(AFMT_GENERIC_7, DIG, id), \
0058     SRI(AFMT_GENERIC_HDR, DIG, id), \
0059     SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
0060     SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
0061     SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
0062     SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
0063     SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
0064     SRI(AFMT_60958_0, DIG, id), \
0065     SRI(AFMT_60958_1, DIG, id), \
0066     SRI(AFMT_60958_2, DIG, id), \
0067     SRI(DIG_FE_CNTL, DIG, id), \
0068     SRI(HDMI_CONTROL, DIG, id), \
0069     SRI(HDMI_GC, DIG, id), \
0070     SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
0071     SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
0072     SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
0073     SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
0074     SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
0075     SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
0076     SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
0077     SRI(HDMI_ACR_32_0, DIG, id),\
0078     SRI(HDMI_ACR_32_1, DIG, id),\
0079     SRI(HDMI_ACR_44_0, DIG, id),\
0080     SRI(HDMI_ACR_44_1, DIG, id),\
0081     SRI(HDMI_ACR_48_0, DIG, id),\
0082     SRI(HDMI_ACR_48_1, DIG, id),\
0083     SRI(TMDS_CNTL, DIG, id), \
0084     SRI(DP_MSE_RATE_CNTL, DP, id), \
0085     SRI(DP_MSE_RATE_UPDATE, DP, id), \
0086     SRI(DP_PIXEL_FORMAT, DP, id), \
0087     SRI(DP_SEC_CNTL, DP, id), \
0088     SRI(DP_STEER_FIFO, DP, id), \
0089     SRI(DP_VID_M, DP, id), \
0090     SRI(DP_VID_N, DP, id), \
0091     SRI(DP_VID_STREAM_CNTL, DP, id), \
0092     SRI(DP_VID_TIMING, DP, id), \
0093     SRI(DP_SEC_AUD_N, DP, id), \
0094     SRI(DP_SEC_TIMESTAMP, DP, id)
0095 
0096 #define SE_COMMON_REG_LIST(id)\
0097     SE_COMMON_REG_LIST_DCE_BASE(id), \
0098     SRI(AFMT_CNTL, DIG, id)
0099 
0100 #define SE_DCN_REG_LIST(id)\
0101     SE_COMMON_REG_LIST_BASE(id),\
0102     SRI(AFMT_CNTL, DIG, id),\
0103     SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
0104     SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
0105     SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
0106     SRI(DP_DB_CNTL, DP, id), \
0107     SRI(DP_MSA_MISC, DP, id), \
0108     SRI(DP_MSA_COLORIMETRY, DP, id), \
0109     SRI(DP_MSA_TIMING_PARAM1, DP, id), \
0110     SRI(DP_MSA_TIMING_PARAM2, DP, id), \
0111     SRI(DP_MSA_TIMING_PARAM3, DP, id), \
0112     SRI(DP_MSA_TIMING_PARAM4, DP, id), \
0113     SRI(HDMI_DB_CONTROL, DIG, id)
0114 
0115 #define SE_SF(reg_name, field_name, post_fix)\
0116     .field_name = reg_name ## __ ## field_name ## post_fix
0117 
0118 #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
0119     SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
0120     SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
0121     SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
0122     SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
0123     SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
0124     SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
0125     SE_SF(AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
0126     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
0127     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
0128     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
0129     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
0130     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
0131     SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
0132     SE_SF(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
0133     SE_SF(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
0134     SE_SF(DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
0135     SE_SF(DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
0136     SE_SF(HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
0137     SE_SF(HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
0138     SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
0139     SE_SF(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
0140     SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
0141     SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
0142     SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
0143     SE_SF(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
0144     SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
0145     SE_SF(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
0146     SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
0147     SE_SF(HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
0148     SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
0149     SE_SF(DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
0150     SE_SF(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
0151     SE_SF(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
0152     SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
0153     SE_SF(HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
0154     SE_SF(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
0155     SE_SF(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
0156     SE_SF(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
0157     SE_SF(DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
0158     SE_SF(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
0159     SE_SF(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
0160     SE_SF(DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
0161     SE_SF(DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
0162     SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
0163     SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
0164     SE_SF(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
0165     SE_SF(DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
0166     SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
0167     SE_SF(DP_VID_N, DP_VID_N, mask_sh),\
0168     SE_SF(DP_VID_M, DP_VID_M, mask_sh),\
0169     SE_SF(DIG_FE_CNTL, DIG_START, mask_sh),\
0170     SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
0171     SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
0172     SE_SF(AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
0173     SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
0174     SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
0175     SE_SF(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
0176     SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
0177     SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
0178     SE_SF(AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
0179     SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
0180     SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
0181     SE_SF(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
0182     SE_SF(HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
0183     SE_SF(HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
0184     SE_SF(HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
0185     SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
0186     SE_SF(HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
0187     SE_SF(HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
0188     SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
0189     SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
0190     SE_SF(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
0191     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
0192     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
0193     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
0194     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
0195     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
0196     SE_SF(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
0197     SE_SF(DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
0198     SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
0199     SE_SF(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
0200     SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
0201     SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
0202     SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
0203     SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
0204     SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
0205 
0206 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
0207     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
0208     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
0209     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
0210     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
0211     SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
0212     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
0213     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
0214     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
0215     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
0216     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
0217     SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\
0218     SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
0219     SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
0220     SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
0221     SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
0222     SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
0223     SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
0224     SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
0225     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
0226     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
0227     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
0228     SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
0229     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
0230     SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
0231     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
0232     SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
0233     SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
0234     SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
0235     SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
0236     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
0237     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
0238     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
0239     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
0240     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
0241     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
0242     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
0243     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
0244     SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
0245     SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
0246     SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
0247     SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
0248     SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
0249     SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
0250     SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
0251     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
0252     SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
0253     SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
0254     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
0255     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
0256     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
0257     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
0258     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
0259     SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
0260     SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
0261     SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
0262     SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
0263     SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
0264     SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
0265     SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
0266     SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
0267     SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
0268     SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
0269     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
0270     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
0271     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
0272     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
0273     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
0274     SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
0275     SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
0276     SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
0277     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
0278     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
0279     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
0280     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
0281     SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
0282     SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
0283     SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
0284     SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
0285     SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
0286     SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
0287     SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
0288     SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
0289 
0290 #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\
0291     SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
0292     SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
0293     SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh)
0294 
0295 #define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
0296     SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
0297     SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
0298     SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
0299     SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
0300     SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
0301     SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
0302     SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
0303     SE_SF(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
0304 
0305 #define SE_COMMON_MASK_SH_LIST_DCE112(mask_sh)\
0306     SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
0307     SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
0308     SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
0309     SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
0310     SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
0311     SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
0312     SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
0313 
0314 #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\
0315     SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
0316     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
0317     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
0318     SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\
0319     SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\
0320     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\
0321     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\
0322     SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\
0323     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\
0324     SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\
0325     SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
0326 
0327 #define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
0328     SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
0329     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
0330     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
0331     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
0332     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
0333     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
0334     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
0335     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
0336     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
0337     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
0338     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
0339     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
0340     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
0341     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
0342     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
0343     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
0344     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
0345     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
0346     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
0347     SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
0348     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
0349     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
0350     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
0351     SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
0352     SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
0353     SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
0354     SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
0355     SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
0356     SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
0357     SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
0358     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
0359     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
0360     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
0361     SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
0362     SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
0363     SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
0364     SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
0365     SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
0366 
0367 struct dce_stream_encoder_shift {
0368     uint8_t AFMT_GENERIC_INDEX;
0369     uint8_t AFMT_GENERIC0_UPDATE;
0370     uint8_t AFMT_GENERIC2_UPDATE;
0371     uint8_t AFMT_GENERIC_HB0;
0372     uint8_t AFMT_GENERIC_HB1;
0373     uint8_t AFMT_GENERIC_HB2;
0374     uint8_t AFMT_GENERIC_HB3;
0375     uint8_t AFMT_GENERIC_LOCK_STATUS;
0376     uint8_t AFMT_GENERIC_CONFLICT;
0377     uint8_t AFMT_GENERIC_CONFLICT_CLR;
0378     uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
0379     uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
0380     uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
0381     uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
0382     uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
0383     uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
0384     uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
0385     uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
0386     uint8_t AFMT_GENERIC0_FRAME_UPDATE;
0387     uint8_t AFMT_GENERIC1_FRAME_UPDATE;
0388     uint8_t AFMT_GENERIC2_FRAME_UPDATE;
0389     uint8_t AFMT_GENERIC3_FRAME_UPDATE;
0390     uint8_t AFMT_GENERIC4_FRAME_UPDATE;
0391     uint8_t AFMT_GENERIC5_FRAME_UPDATE;
0392     uint8_t AFMT_GENERIC6_FRAME_UPDATE;
0393     uint8_t AFMT_GENERIC7_FRAME_UPDATE;
0394     uint8_t HDMI_GENERIC0_CONT;
0395     uint8_t HDMI_GENERIC0_SEND;
0396     uint8_t HDMI_GENERIC0_LINE;
0397     uint8_t HDMI_GENERIC1_CONT;
0398     uint8_t HDMI_GENERIC1_SEND;
0399     uint8_t HDMI_GENERIC1_LINE;
0400     uint8_t DP_PIXEL_ENCODING;
0401     uint8_t DP_COMPONENT_DEPTH;
0402     uint8_t DP_DYN_RANGE;
0403     uint8_t DP_YCBCR_RANGE;
0404     uint8_t HDMI_PACKET_GEN_VERSION;
0405     uint8_t HDMI_KEEPOUT_MODE;
0406     uint8_t HDMI_DEEP_COLOR_ENABLE;
0407     uint8_t HDMI_CLOCK_CHANNEL_RATE;
0408     uint8_t HDMI_DEEP_COLOR_DEPTH;
0409     uint8_t HDMI_GC_CONT;
0410     uint8_t HDMI_GC_SEND;
0411     uint8_t HDMI_NULL_SEND;
0412     uint8_t HDMI_DATA_SCRAMBLE_EN;
0413     uint8_t HDMI_ACP_SEND;
0414     uint8_t HDMI_AUDIO_INFO_SEND;
0415     uint8_t AFMT_AUDIO_INFO_UPDATE;
0416     uint8_t HDMI_AUDIO_INFO_LINE;
0417     uint8_t HDMI_GC_AVMUTE;
0418     uint8_t DP_MSE_RATE_X;
0419     uint8_t DP_MSE_RATE_Y;
0420     uint8_t DP_MSE_RATE_UPDATE_PENDING;
0421     uint8_t AFMT_AVI_INFO_VERSION;
0422     uint8_t HDMI_AVI_INFO_SEND;
0423     uint8_t HDMI_AVI_INFO_CONT;
0424     uint8_t HDMI_AVI_INFO_LINE;
0425     uint8_t DP_SEC_GSP0_ENABLE;
0426     uint8_t DP_SEC_STREAM_ENABLE;
0427     uint8_t DP_SEC_GSP1_ENABLE;
0428     uint8_t DP_SEC_GSP2_ENABLE;
0429     uint8_t DP_SEC_GSP3_ENABLE;
0430     uint8_t DP_SEC_GSP4_ENABLE;
0431     uint8_t DP_SEC_GSP5_ENABLE;
0432     uint8_t DP_SEC_GSP6_ENABLE;
0433     uint8_t DP_SEC_GSP7_ENABLE;
0434     uint8_t DP_SEC_AVI_ENABLE;
0435     uint8_t DP_SEC_MPG_ENABLE;
0436     uint8_t DP_VID_STREAM_DIS_DEFER;
0437     uint8_t DP_VID_STREAM_ENABLE;
0438     uint8_t DP_VID_STREAM_STATUS;
0439     uint8_t DP_STEER_FIFO_RESET;
0440     uint8_t DP_VID_M_N_GEN_EN;
0441     uint8_t DP_VID_N;
0442     uint8_t DP_VID_M;
0443     uint8_t DIG_START;
0444     uint8_t AFMT_AUDIO_SRC_SELECT;
0445     uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
0446     uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
0447     uint8_t HDMI_AUDIO_DELAY_EN;
0448     uint8_t AFMT_60958_CS_UPDATE;
0449     uint8_t AFMT_AUDIO_LAYOUT_OVRD;
0450     uint8_t AFMT_60958_OSF_OVRD;
0451     uint8_t HDMI_ACR_AUTO_SEND;
0452     uint8_t HDMI_ACR_SOURCE;
0453     uint8_t HDMI_ACR_AUDIO_PRIORITY;
0454     uint8_t HDMI_ACR_CTS_32;
0455     uint8_t HDMI_ACR_N_32;
0456     uint8_t HDMI_ACR_CTS_44;
0457     uint8_t HDMI_ACR_N_44;
0458     uint8_t HDMI_ACR_CTS_48;
0459     uint8_t HDMI_ACR_N_48;
0460     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
0461     uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
0462     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
0463     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
0464     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
0465     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
0466     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
0467     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
0468     uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
0469     uint8_t DP_SEC_AUD_N;
0470     uint8_t DP_SEC_TIMESTAMP_MODE;
0471     uint8_t DP_SEC_ASP_ENABLE;
0472     uint8_t DP_SEC_ATP_ENABLE;
0473     uint8_t DP_SEC_AIP_ENABLE;
0474     uint8_t DP_SEC_ACM_ENABLE;
0475     uint8_t AFMT_AUDIO_SAMPLE_SEND;
0476     uint8_t AFMT_AUDIO_CLOCK_EN;
0477     uint8_t TMDS_PIXEL_ENCODING;
0478     uint8_t TMDS_COLOR_FORMAT;
0479     uint8_t DIG_STEREOSYNC_SELECT;
0480     uint8_t DIG_STEREOSYNC_GATE_EN;
0481     uint8_t DP_DB_DISABLE;
0482     uint8_t DP_MSA_MISC0;
0483     uint8_t DP_MSA_HTOTAL;
0484     uint8_t DP_MSA_VTOTAL;
0485     uint8_t DP_MSA_HSTART;
0486     uint8_t DP_MSA_VSTART;
0487     uint8_t DP_MSA_HSYNCWIDTH;
0488     uint8_t DP_MSA_HSYNCPOLARITY;
0489     uint8_t DP_MSA_VSYNCWIDTH;
0490     uint8_t DP_MSA_VSYNCPOLARITY;
0491     uint8_t DP_MSA_HWIDTH;
0492     uint8_t DP_MSA_VHEIGHT;
0493     uint8_t HDMI_DB_DISABLE;
0494     uint8_t DP_VID_N_MUL;
0495     uint8_t DP_VID_M_DOUBLE_VALUE_EN;
0496     uint8_t DIG_SOURCE_SELECT;
0497 };
0498 
0499 struct dce_stream_encoder_mask {
0500     uint32_t AFMT_GENERIC_INDEX;
0501     uint32_t AFMT_GENERIC0_UPDATE;
0502     uint32_t AFMT_GENERIC2_UPDATE;
0503     uint32_t AFMT_GENERIC_HB0;
0504     uint32_t AFMT_GENERIC_HB1;
0505     uint32_t AFMT_GENERIC_HB2;
0506     uint32_t AFMT_GENERIC_HB3;
0507     uint32_t AFMT_GENERIC_LOCK_STATUS;
0508     uint32_t AFMT_GENERIC_CONFLICT;
0509     uint32_t AFMT_GENERIC_CONFLICT_CLR;
0510     uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
0511     uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
0512     uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
0513     uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
0514     uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
0515     uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
0516     uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
0517     uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
0518     uint32_t AFMT_GENERIC0_FRAME_UPDATE;
0519     uint32_t AFMT_GENERIC1_FRAME_UPDATE;
0520     uint32_t AFMT_GENERIC2_FRAME_UPDATE;
0521     uint32_t AFMT_GENERIC3_FRAME_UPDATE;
0522     uint32_t AFMT_GENERIC4_FRAME_UPDATE;
0523     uint32_t AFMT_GENERIC5_FRAME_UPDATE;
0524     uint32_t AFMT_GENERIC6_FRAME_UPDATE;
0525     uint32_t AFMT_GENERIC7_FRAME_UPDATE;
0526     uint32_t HDMI_GENERIC0_CONT;
0527     uint32_t HDMI_GENERIC0_SEND;
0528     uint32_t HDMI_GENERIC0_LINE;
0529     uint32_t HDMI_GENERIC1_CONT;
0530     uint32_t HDMI_GENERIC1_SEND;
0531     uint32_t HDMI_GENERIC1_LINE;
0532     uint32_t DP_PIXEL_ENCODING;
0533     uint32_t DP_COMPONENT_DEPTH;
0534     uint32_t DP_DYN_RANGE;
0535     uint32_t DP_YCBCR_RANGE;
0536     uint32_t HDMI_PACKET_GEN_VERSION;
0537     uint32_t HDMI_KEEPOUT_MODE;
0538     uint32_t HDMI_DEEP_COLOR_ENABLE;
0539     uint32_t HDMI_CLOCK_CHANNEL_RATE;
0540     uint32_t HDMI_DEEP_COLOR_DEPTH;
0541     uint32_t HDMI_GC_CONT;
0542     uint32_t HDMI_GC_SEND;
0543     uint32_t HDMI_NULL_SEND;
0544     uint32_t HDMI_DATA_SCRAMBLE_EN;
0545     uint32_t HDMI_ACP_SEND;
0546     uint32_t HDMI_AUDIO_INFO_SEND;
0547     uint32_t AFMT_AUDIO_INFO_UPDATE;
0548     uint32_t HDMI_AUDIO_INFO_LINE;
0549     uint32_t HDMI_GC_AVMUTE;
0550     uint32_t DP_MSE_RATE_X;
0551     uint32_t DP_MSE_RATE_Y;
0552     uint32_t DP_MSE_RATE_UPDATE_PENDING;
0553     uint32_t AFMT_AVI_INFO_VERSION;
0554     uint32_t HDMI_AVI_INFO_SEND;
0555     uint32_t HDMI_AVI_INFO_CONT;
0556     uint32_t HDMI_AVI_INFO_LINE;
0557     uint32_t DP_SEC_GSP0_ENABLE;
0558     uint32_t DP_SEC_STREAM_ENABLE;
0559     uint32_t DP_SEC_GSP1_ENABLE;
0560     uint32_t DP_SEC_GSP2_ENABLE;
0561     uint32_t DP_SEC_GSP3_ENABLE;
0562     uint32_t DP_SEC_GSP4_ENABLE;
0563     uint32_t DP_SEC_GSP5_ENABLE;
0564     uint32_t DP_SEC_GSP6_ENABLE;
0565     uint32_t DP_SEC_GSP7_ENABLE;
0566     uint32_t DP_SEC_AVI_ENABLE;
0567     uint32_t DP_SEC_MPG_ENABLE;
0568     uint32_t DP_VID_STREAM_DIS_DEFER;
0569     uint32_t DP_VID_STREAM_ENABLE;
0570     uint32_t DP_VID_STREAM_STATUS;
0571     uint32_t DP_STEER_FIFO_RESET;
0572     uint32_t DP_VID_M_N_GEN_EN;
0573     uint32_t DP_VID_N;
0574     uint32_t DP_VID_M;
0575     uint32_t DIG_START;
0576     uint32_t AFMT_AUDIO_SRC_SELECT;
0577     uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
0578     uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
0579     uint32_t HDMI_AUDIO_DELAY_EN;
0580     uint32_t AFMT_60958_CS_UPDATE;
0581     uint32_t AFMT_AUDIO_LAYOUT_OVRD;
0582     uint32_t AFMT_60958_OSF_OVRD;
0583     uint32_t HDMI_ACR_AUTO_SEND;
0584     uint32_t HDMI_ACR_SOURCE;
0585     uint32_t HDMI_ACR_AUDIO_PRIORITY;
0586     uint32_t HDMI_ACR_CTS_32;
0587     uint32_t HDMI_ACR_N_32;
0588     uint32_t HDMI_ACR_CTS_44;
0589     uint32_t HDMI_ACR_N_44;
0590     uint32_t HDMI_ACR_CTS_48;
0591     uint32_t HDMI_ACR_N_48;
0592     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
0593     uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
0594     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
0595     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
0596     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
0597     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
0598     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
0599     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
0600     uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
0601     uint32_t DP_SEC_AUD_N;
0602     uint32_t DP_SEC_TIMESTAMP_MODE;
0603     uint32_t DP_SEC_ASP_ENABLE;
0604     uint32_t DP_SEC_ATP_ENABLE;
0605     uint32_t DP_SEC_AIP_ENABLE;
0606     uint32_t DP_SEC_ACM_ENABLE;
0607     uint32_t AFMT_AUDIO_SAMPLE_SEND;
0608     uint32_t AFMT_AUDIO_CLOCK_EN;
0609     uint32_t TMDS_PIXEL_ENCODING;
0610     uint32_t DIG_STEREOSYNC_SELECT;
0611     uint32_t DIG_STEREOSYNC_GATE_EN;
0612     uint32_t TMDS_COLOR_FORMAT;
0613     uint32_t DP_DB_DISABLE;
0614     uint32_t DP_MSA_MISC0;
0615     uint32_t DP_MSA_HTOTAL;
0616     uint32_t DP_MSA_VTOTAL;
0617     uint32_t DP_MSA_HSTART;
0618     uint32_t DP_MSA_VSTART;
0619     uint32_t DP_MSA_HSYNCWIDTH;
0620     uint32_t DP_MSA_HSYNCPOLARITY;
0621     uint32_t DP_MSA_VSYNCWIDTH;
0622     uint32_t DP_MSA_VSYNCPOLARITY;
0623     uint32_t DP_MSA_HWIDTH;
0624     uint32_t DP_MSA_VHEIGHT;
0625     uint32_t HDMI_DB_DISABLE;
0626     uint32_t DP_VID_N_MUL;
0627     uint32_t DP_VID_M_DOUBLE_VALUE_EN;
0628     uint32_t DIG_SOURCE_SELECT;
0629 };
0630 
0631 struct dce110_stream_enc_registers {
0632     uint32_t AFMT_CNTL;
0633     uint32_t AFMT_AVI_INFO0;
0634     uint32_t AFMT_AVI_INFO1;
0635     uint32_t AFMT_AVI_INFO2;
0636     uint32_t AFMT_AVI_INFO3;
0637     uint32_t AFMT_GENERIC_0;
0638     uint32_t AFMT_GENERIC_1;
0639     uint32_t AFMT_GENERIC_2;
0640     uint32_t AFMT_GENERIC_3;
0641     uint32_t AFMT_GENERIC_4;
0642     uint32_t AFMT_GENERIC_5;
0643     uint32_t AFMT_GENERIC_6;
0644     uint32_t AFMT_GENERIC_7;
0645     uint32_t AFMT_GENERIC_HDR;
0646     uint32_t AFMT_INFOFRAME_CONTROL0;
0647     uint32_t AFMT_VBI_PACKET_CONTROL;
0648     uint32_t AFMT_VBI_PACKET_CONTROL1;
0649     uint32_t AFMT_AUDIO_PACKET_CONTROL;
0650     uint32_t AFMT_AUDIO_PACKET_CONTROL2;
0651     uint32_t AFMT_AUDIO_SRC_CONTROL;
0652     uint32_t AFMT_60958_0;
0653     uint32_t AFMT_60958_1;
0654     uint32_t AFMT_60958_2;
0655     uint32_t DIG_FE_CNTL;
0656     uint32_t DP_MSE_RATE_CNTL;
0657     uint32_t DP_MSE_RATE_UPDATE;
0658     uint32_t DP_PIXEL_FORMAT;
0659     uint32_t DP_SEC_CNTL;
0660     uint32_t DP_STEER_FIFO;
0661     uint32_t DP_VID_M;
0662     uint32_t DP_VID_N;
0663     uint32_t DP_VID_STREAM_CNTL;
0664     uint32_t DP_VID_TIMING;
0665     uint32_t DP_SEC_AUD_N;
0666     uint32_t DP_SEC_TIMESTAMP;
0667     uint32_t HDMI_CONTROL;
0668     uint32_t HDMI_GC;
0669     uint32_t HDMI_GENERIC_PACKET_CONTROL0;
0670     uint32_t HDMI_GENERIC_PACKET_CONTROL1;
0671     uint32_t HDMI_GENERIC_PACKET_CONTROL2;
0672     uint32_t HDMI_GENERIC_PACKET_CONTROL3;
0673     uint32_t HDMI_INFOFRAME_CONTROL0;
0674     uint32_t HDMI_INFOFRAME_CONTROL1;
0675     uint32_t HDMI_VBI_PACKET_CONTROL;
0676     uint32_t HDMI_AUDIO_PACKET_CONTROL;
0677     uint32_t HDMI_ACR_PACKET_CONTROL;
0678     uint32_t HDMI_ACR_32_0;
0679     uint32_t HDMI_ACR_32_1;
0680     uint32_t HDMI_ACR_44_0;
0681     uint32_t HDMI_ACR_44_1;
0682     uint32_t HDMI_ACR_48_0;
0683     uint32_t HDMI_ACR_48_1;
0684     uint32_t TMDS_CNTL;
0685     uint32_t DP_DB_CNTL;
0686     uint32_t DP_MSA_MISC;
0687     uint32_t DP_MSA_COLORIMETRY;
0688     uint32_t DP_MSA_TIMING_PARAM1;
0689     uint32_t DP_MSA_TIMING_PARAM2;
0690     uint32_t DP_MSA_TIMING_PARAM3;
0691     uint32_t DP_MSA_TIMING_PARAM4;
0692     uint32_t HDMI_DB_CONTROL;
0693 };
0694 
0695 struct dce110_stream_encoder {
0696     struct stream_encoder base;
0697     const struct dce110_stream_enc_registers *regs;
0698     const struct dce_stream_encoder_shift *se_shift;
0699     const struct dce_stream_encoder_mask *se_mask;
0700 };
0701 
0702 void dce110_stream_encoder_construct(
0703     struct dce110_stream_encoder *enc110,
0704     struct dc_context *ctx,
0705     struct dc_bios *bp,
0706     enum engine_id eng_id,
0707     const struct dce110_stream_enc_registers *regs,
0708     const struct dce_stream_encoder_shift *se_shift,
0709     const struct dce_stream_encoder_mask *se_mask);
0710 
0711 
0712 void dce110_se_audio_mute_control(
0713     struct stream_encoder *enc, bool mute);
0714 
0715 void dce110_se_dp_audio_setup(
0716     struct stream_encoder *enc,
0717     unsigned int az_inst,
0718     struct audio_info *info);
0719 
0720 void dce110_se_dp_audio_enable(
0721         struct stream_encoder *enc);
0722 
0723 void dce110_se_dp_audio_disable(
0724         struct stream_encoder *enc);
0725 
0726 void dce110_se_hdmi_audio_setup(
0727     struct stream_encoder *enc,
0728     unsigned int az_inst,
0729     struct audio_info *info,
0730     struct audio_crtc_info *audio_crtc_info);
0731 
0732 void dce110_se_hdmi_audio_disable(
0733     struct stream_encoder *enc);
0734 
0735 #endif /* __DC_STREAM_ENCODER_DCE110_H__ */
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