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0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #include "dc_bios_types.h"
0027 #include "dce_stream_encoder.h"
0028 #include "reg_helper.h"
0029 #include "hw_shared.h"
0030 
0031 #define DC_LOGGER \
0032         enc110->base.ctx->logger
0033 
0034 #define REG(reg)\
0035     (enc110->regs->reg)
0036 
0037 #undef FN
0038 #define FN(reg_name, field_name) \
0039     enc110->se_shift->field_name, enc110->se_mask->field_name
0040 
0041 #define VBI_LINE_0 0
0042 #define DP_BLANK_MAX_RETRY 20
0043 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
0044 
0045 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
0046     #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
0047     #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
0048     #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT     0x00000004
0049     #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT       0x00000008
0050 #endif
0051 
0052 enum {
0053     DP_MST_UPDATE_MAX_RETRY = 50
0054 };
0055 
0056 #define DCE110_SE(audio)\
0057     container_of(audio, struct dce110_stream_encoder, base)
0058 
0059 #define CTX \
0060     enc110->base.ctx
0061 
0062 static void dce110_update_generic_info_packet(
0063     struct dce110_stream_encoder *enc110,
0064     uint32_t packet_index,
0065     const struct dc_info_packet *info_packet)
0066 {
0067     /* TODOFPGA Figure out a proper number for max_retries polling for lock
0068      * use 50 for now.
0069      */
0070     uint32_t max_retries = 50;
0071 
0072     /*we need turn on clock before programming AFMT block*/
0073     if (REG(AFMT_CNTL))
0074         REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0075 
0076     if (REG(AFMT_VBI_PACKET_CONTROL1)) {
0077         if (packet_index >= 8)
0078             ASSERT(0);
0079 
0080         /* poll dig_update_lock is not locked -> asic internal signal
0081          * assume otg master lock will unlock it
0082          */
0083 /*      REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
0084                 0, 10, max_retries);*/
0085 
0086         /* check if HW reading GSP memory */
0087         REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
0088                 0, 10, max_retries);
0089 
0090         /* HW does is not reading GSP memory not reading too long ->
0091          * something wrong. clear GPS memory access and notify?
0092          * hw SW is writing to GSP memory
0093          */
0094         REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
0095     }
0096     /* choose which generic packet to use */
0097     {
0098         REG_READ(AFMT_VBI_PACKET_CONTROL);
0099         REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
0100                 AFMT_GENERIC_INDEX, packet_index);
0101     }
0102 
0103     /* write generic packet header
0104      * (4th byte is for GENERIC0 only) */
0105     {
0106         REG_SET_4(AFMT_GENERIC_HDR, 0,
0107                 AFMT_GENERIC_HB0, info_packet->hb0,
0108                 AFMT_GENERIC_HB1, info_packet->hb1,
0109                 AFMT_GENERIC_HB2, info_packet->hb2,
0110                 AFMT_GENERIC_HB3, info_packet->hb3);
0111     }
0112 
0113     /* write generic packet contents
0114      * (we never use last 4 bytes)
0115      * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
0116     {
0117         const uint32_t *content =
0118             (const uint32_t *) &info_packet->sb[0];
0119 
0120         REG_WRITE(AFMT_GENERIC_0, *content++);
0121         REG_WRITE(AFMT_GENERIC_1, *content++);
0122         REG_WRITE(AFMT_GENERIC_2, *content++);
0123         REG_WRITE(AFMT_GENERIC_3, *content++);
0124         REG_WRITE(AFMT_GENERIC_4, *content++);
0125         REG_WRITE(AFMT_GENERIC_5, *content++);
0126         REG_WRITE(AFMT_GENERIC_6, *content++);
0127         REG_WRITE(AFMT_GENERIC_7, *content);
0128     }
0129 
0130     if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
0131         /* force double-buffered packet update */
0132         REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
0133             AFMT_GENERIC0_UPDATE, (packet_index == 0),
0134             AFMT_GENERIC2_UPDATE, (packet_index == 2));
0135     }
0136 
0137     if (REG(AFMT_VBI_PACKET_CONTROL1)) {
0138         switch (packet_index) {
0139         case 0:
0140             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0141                     AFMT_GENERIC0_FRAME_UPDATE, 1);
0142             break;
0143         case 1:
0144             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0145                     AFMT_GENERIC1_FRAME_UPDATE, 1);
0146             break;
0147         case 2:
0148             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0149                     AFMT_GENERIC2_FRAME_UPDATE, 1);
0150             break;
0151         case 3:
0152             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0153                     AFMT_GENERIC3_FRAME_UPDATE, 1);
0154             break;
0155         case 4:
0156             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0157                     AFMT_GENERIC4_FRAME_UPDATE, 1);
0158             break;
0159         case 5:
0160             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0161                     AFMT_GENERIC5_FRAME_UPDATE, 1);
0162             break;
0163         case 6:
0164             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0165                     AFMT_GENERIC6_FRAME_UPDATE, 1);
0166             break;
0167         case 7:
0168             REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
0169                     AFMT_GENERIC7_FRAME_UPDATE, 1);
0170             break;
0171         default:
0172             break;
0173         }
0174     }
0175 }
0176 
0177 static void dce110_update_hdmi_info_packet(
0178     struct dce110_stream_encoder *enc110,
0179     uint32_t packet_index,
0180     const struct dc_info_packet *info_packet)
0181 {
0182     uint32_t cont, send, line;
0183 
0184     if (info_packet->valid) {
0185         dce110_update_generic_info_packet(
0186             enc110,
0187             packet_index,
0188             info_packet);
0189 
0190         /* enable transmission of packet(s) -
0191          * packet transmission begins on the next frame */
0192         cont = 1;
0193         /* send packet(s) every frame */
0194         send = 1;
0195         /* select line number to send packets on */
0196         line = 2;
0197     } else {
0198         cont = 0;
0199         send = 0;
0200         line = 0;
0201     }
0202 
0203     /* choose which generic packet control to use */
0204     switch (packet_index) {
0205     case 0:
0206         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
0207                 HDMI_GENERIC0_CONT, cont,
0208                 HDMI_GENERIC0_SEND, send,
0209                 HDMI_GENERIC0_LINE, line);
0210         break;
0211     case 1:
0212         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
0213                 HDMI_GENERIC1_CONT, cont,
0214                 HDMI_GENERIC1_SEND, send,
0215                 HDMI_GENERIC1_LINE, line);
0216         break;
0217     case 2:
0218         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
0219                 HDMI_GENERIC0_CONT, cont,
0220                 HDMI_GENERIC0_SEND, send,
0221                 HDMI_GENERIC0_LINE, line);
0222         break;
0223     case 3:
0224         REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
0225                 HDMI_GENERIC1_CONT, cont,
0226                 HDMI_GENERIC1_SEND, send,
0227                 HDMI_GENERIC1_LINE, line);
0228         break;
0229     case 4:
0230         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
0231             REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
0232                     HDMI_GENERIC0_CONT, cont,
0233                     HDMI_GENERIC0_SEND, send,
0234                     HDMI_GENERIC0_LINE, line);
0235         break;
0236     case 5:
0237         if (REG(HDMI_GENERIC_PACKET_CONTROL2))
0238             REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
0239                     HDMI_GENERIC1_CONT, cont,
0240                     HDMI_GENERIC1_SEND, send,
0241                     HDMI_GENERIC1_LINE, line);
0242         break;
0243     case 6:
0244         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
0245             REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
0246                     HDMI_GENERIC0_CONT, cont,
0247                     HDMI_GENERIC0_SEND, send,
0248                     HDMI_GENERIC0_LINE, line);
0249         break;
0250     case 7:
0251         if (REG(HDMI_GENERIC_PACKET_CONTROL3))
0252             REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
0253                     HDMI_GENERIC1_CONT, cont,
0254                     HDMI_GENERIC1_SEND, send,
0255                     HDMI_GENERIC1_LINE, line);
0256         break;
0257     default:
0258         /* invalid HW packet index */
0259         DC_LOG_WARNING(
0260             "Invalid HW packet index: %s()\n",
0261             __func__);
0262         return;
0263     }
0264 }
0265 
0266 /* setup stream encoder in dp mode */
0267 static void dce110_stream_encoder_dp_set_stream_attribute(
0268     struct stream_encoder *enc,
0269     struct dc_crtc_timing *crtc_timing,
0270     enum dc_color_space output_color_space,
0271     bool use_vsc_sdp_for_colorimetry,
0272     uint32_t enable_sdp_splitting)
0273 {
0274     uint32_t h_active_start;
0275     uint32_t v_active_start;
0276     uint32_t misc0 = 0;
0277     uint32_t misc1 = 0;
0278     uint32_t h_blank;
0279     uint32_t h_back_porch;
0280     uint8_t synchronous_clock = 0; /* asynchronous mode */
0281     uint8_t colorimetry_bpc;
0282     uint8_t dynamic_range_rgb = 0; /*full range*/
0283     uint8_t dynamic_range_ycbcr = 1; /*bt709*/
0284 
0285     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0286     struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
0287     if (hw_crtc_timing.flags.INTERLACE) {
0288         /*the input timing is in VESA spec format with Interlace flag =1*/
0289         hw_crtc_timing.v_total /= 2;
0290         hw_crtc_timing.v_border_top /= 2;
0291         hw_crtc_timing.v_addressable /= 2;
0292         hw_crtc_timing.v_border_bottom /= 2;
0293         hw_crtc_timing.v_front_porch /= 2;
0294         hw_crtc_timing.v_sync_width /= 2;
0295     }
0296     /* set pixel encoding */
0297     switch (hw_crtc_timing.pixel_encoding) {
0298     case PIXEL_ENCODING_YCBCR422:
0299         REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
0300                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
0301         break;
0302     case PIXEL_ENCODING_YCBCR444:
0303         REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
0304                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
0305 
0306         if (hw_crtc_timing.flags.Y_ONLY)
0307             if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
0308                 /* HW testing only, no use case yet.
0309                  * Color depth of Y-only could be
0310                  * 8, 10, 12, 16 bits */
0311                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
0312                         DP_PIXEL_ENCODING_TYPE_Y_ONLY);
0313         /* Note: DP_MSA_MISC1 bit 7 is the indicator
0314          * of Y-only mode.
0315          * This bit is set in HW if register
0316          * DP_PIXEL_ENCODING is programmed to 0x4 */
0317         break;
0318     case PIXEL_ENCODING_YCBCR420:
0319         REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
0320                 DP_PIXEL_ENCODING_TYPE_YCBCR420);
0321         if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
0322             REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
0323 
0324         if (enc110->se_mask->DP_VID_N_MUL)
0325             REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
0326         break;
0327     default:
0328         REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
0329                 DP_PIXEL_ENCODING_TYPE_RGB444);
0330         break;
0331     }
0332 
0333     if (REG(DP_MSA_MISC))
0334         misc1 = REG_READ(DP_MSA_MISC);
0335 
0336     /* set color depth */
0337 
0338     switch (hw_crtc_timing.display_color_depth) {
0339     case COLOR_DEPTH_666:
0340         REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
0341                 0);
0342         break;
0343     case COLOR_DEPTH_888:
0344         REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
0345                 DP_COMPONENT_PIXEL_DEPTH_8BPC);
0346         break;
0347     case COLOR_DEPTH_101010:
0348         REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
0349                 DP_COMPONENT_PIXEL_DEPTH_10BPC);
0350 
0351         break;
0352     case COLOR_DEPTH_121212:
0353         REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
0354                 DP_COMPONENT_PIXEL_DEPTH_12BPC);
0355         break;
0356     default:
0357         REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
0358                 DP_COMPONENT_PIXEL_DEPTH_6BPC);
0359         break;
0360     }
0361 
0362     /* set dynamic range and YCbCr range */
0363 
0364 
0365     switch (hw_crtc_timing.display_color_depth) {
0366     case COLOR_DEPTH_666:
0367         colorimetry_bpc = 0;
0368         break;
0369     case COLOR_DEPTH_888:
0370         colorimetry_bpc = 1;
0371         break;
0372     case COLOR_DEPTH_101010:
0373         colorimetry_bpc = 2;
0374         break;
0375     case COLOR_DEPTH_121212:
0376         colorimetry_bpc = 3;
0377         break;
0378     default:
0379         colorimetry_bpc = 0;
0380         break;
0381     }
0382 
0383     misc0 = misc0 | synchronous_clock;
0384     misc0 = colorimetry_bpc << 5;
0385 
0386     if (REG(DP_MSA_TIMING_PARAM1)) {
0387         switch (output_color_space) {
0388         case COLOR_SPACE_SRGB:
0389             misc0 = misc0 | 0x0;
0390             misc1 = misc1 & ~0x80; /* bit7 = 0*/
0391             dynamic_range_rgb = 0; /*full range*/
0392             break;
0393         case COLOR_SPACE_SRGB_LIMITED:
0394             misc0 = misc0 | 0x8; /* bit3=1 */
0395             misc1 = misc1 & ~0x80; /* bit7 = 0*/
0396             dynamic_range_rgb = 1; /*limited range*/
0397             break;
0398         case COLOR_SPACE_YCBCR601:
0399         case COLOR_SPACE_YCBCR601_LIMITED:
0400             misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
0401             misc1 = misc1 & ~0x80; /* bit7 = 0*/
0402             dynamic_range_ycbcr = 0; /*bt601*/
0403             if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
0404                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
0405             else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
0406                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
0407             break;
0408         case COLOR_SPACE_YCBCR709:
0409         case COLOR_SPACE_YCBCR709_LIMITED:
0410         case COLOR_SPACE_YCBCR709_BLACK:
0411             misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
0412             misc1 = misc1 & ~0x80; /* bit7 = 0*/
0413             dynamic_range_ycbcr = 1; /*bt709*/
0414             if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
0415                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
0416             else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
0417                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
0418             break;
0419         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
0420             dynamic_range_rgb = 1; /*limited range*/
0421             break;
0422         case COLOR_SPACE_2020_RGB_FULLRANGE:
0423         case COLOR_SPACE_2020_YCBCR:
0424         case COLOR_SPACE_XR_RGB:
0425         case COLOR_SPACE_MSREF_SCRGB:
0426         case COLOR_SPACE_ADOBERGB:
0427         case COLOR_SPACE_DCIP3:
0428         case COLOR_SPACE_XV_YCC_709:
0429         case COLOR_SPACE_XV_YCC_601:
0430         case COLOR_SPACE_DISPLAYNATIVE:
0431         case COLOR_SPACE_DOLBYVISION:
0432         case COLOR_SPACE_APPCTRL:
0433         case COLOR_SPACE_CUSTOMPOINTS:
0434         case COLOR_SPACE_UNKNOWN:
0435             /* do nothing */
0436             break;
0437         }
0438         if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
0439             REG_UPDATE_2(
0440                 DP_PIXEL_FORMAT,
0441                 DP_DYN_RANGE, dynamic_range_rgb,
0442                 DP_YCBCR_RANGE, dynamic_range_ycbcr);
0443 
0444         if (REG(DP_MSA_COLORIMETRY))
0445             REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
0446 
0447         if (REG(DP_MSA_MISC))
0448             REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
0449 
0450     /* dcn new register
0451      * dc_crtc_timing is vesa dmt struct. data from edid
0452      */
0453         if (REG(DP_MSA_TIMING_PARAM1))
0454             REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
0455                     DP_MSA_HTOTAL, hw_crtc_timing.h_total,
0456                     DP_MSA_VTOTAL, hw_crtc_timing.v_total);
0457 
0458         /* calcuate from vesa timing parameters
0459          * h_active_start related to leading edge of sync
0460          */
0461 
0462         h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
0463                 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
0464 
0465         h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
0466                 hw_crtc_timing.h_sync_width;
0467 
0468         /* start at begining of left border */
0469         h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
0470 
0471 
0472         v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
0473                 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
0474                 hw_crtc_timing.v_front_porch;
0475 
0476 
0477         /* start at begining of left border */
0478         if (REG(DP_MSA_TIMING_PARAM2))
0479             REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
0480                 DP_MSA_HSTART, h_active_start,
0481                 DP_MSA_VSTART, v_active_start);
0482 
0483         if (REG(DP_MSA_TIMING_PARAM3))
0484             REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
0485                     DP_MSA_HSYNCWIDTH,
0486                     hw_crtc_timing.h_sync_width,
0487                     DP_MSA_HSYNCPOLARITY,
0488                     !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
0489                     DP_MSA_VSYNCWIDTH,
0490                     hw_crtc_timing.v_sync_width,
0491                     DP_MSA_VSYNCPOLARITY,
0492                     !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
0493 
0494         /* HWDITH include border or overscan */
0495         if (REG(DP_MSA_TIMING_PARAM4))
0496             REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
0497                 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
0498                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
0499                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
0500                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
0501     }
0502 }
0503 
0504 static void dce110_stream_encoder_set_stream_attribute_helper(
0505         struct dce110_stream_encoder *enc110,
0506         struct dc_crtc_timing *crtc_timing)
0507 {
0508     if (enc110->regs->TMDS_CNTL) {
0509         switch (crtc_timing->pixel_encoding) {
0510         case PIXEL_ENCODING_YCBCR422:
0511             REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
0512             break;
0513         default:
0514             REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
0515             break;
0516         }
0517         REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
0518     } else if (enc110->regs->DIG_FE_CNTL) {
0519         switch (crtc_timing->pixel_encoding) {
0520         case PIXEL_ENCODING_YCBCR422:
0521             REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
0522             break;
0523         default:
0524             REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
0525             break;
0526         }
0527         REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
0528     }
0529 
0530 }
0531 
0532 /* setup stream encoder in hdmi mode */
0533 static void dce110_stream_encoder_hdmi_set_stream_attribute(
0534     struct stream_encoder *enc,
0535     struct dc_crtc_timing *crtc_timing,
0536     int actual_pix_clk_khz,
0537     bool enable_audio)
0538 {
0539     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0540     struct bp_encoder_control cntl = {0};
0541 
0542     cntl.action = ENCODER_CONTROL_SETUP;
0543     cntl.engine_id = enc110->base.id;
0544     cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
0545     cntl.enable_dp_audio = enable_audio;
0546     cntl.pixel_clock = actual_pix_clk_khz;
0547     cntl.lanes_number = LANE_COUNT_FOUR;
0548     cntl.color_depth = crtc_timing->display_color_depth;
0549 
0550     if (enc110->base.bp->funcs->encoder_control(
0551             enc110->base.bp, &cntl) != BP_RESULT_OK)
0552         return;
0553 
0554     dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
0555 
0556     /* setup HDMI engine */
0557     if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
0558         REG_UPDATE_3(HDMI_CONTROL,
0559             HDMI_PACKET_GEN_VERSION, 1,
0560             HDMI_KEEPOUT_MODE, 1,
0561             HDMI_DEEP_COLOR_ENABLE, 0);
0562     } else if (enc110->regs->DIG_FE_CNTL) {
0563         REG_UPDATE_5(HDMI_CONTROL,
0564             HDMI_PACKET_GEN_VERSION, 1,
0565             HDMI_KEEPOUT_MODE, 1,
0566             HDMI_DEEP_COLOR_ENABLE, 0,
0567             HDMI_DATA_SCRAMBLE_EN, 0,
0568             HDMI_CLOCK_CHANNEL_RATE, 0);
0569     }
0570 
0571     switch (crtc_timing->display_color_depth) {
0572     case COLOR_DEPTH_888:
0573         REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
0574         break;
0575     case COLOR_DEPTH_101010:
0576         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0577             REG_UPDATE_2(HDMI_CONTROL,
0578                     HDMI_DEEP_COLOR_DEPTH, 1,
0579                     HDMI_DEEP_COLOR_ENABLE, 0);
0580         } else {
0581             REG_UPDATE_2(HDMI_CONTROL,
0582                     HDMI_DEEP_COLOR_DEPTH, 1,
0583                     HDMI_DEEP_COLOR_ENABLE, 1);
0584             }
0585         break;
0586     case COLOR_DEPTH_121212:
0587         if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
0588             REG_UPDATE_2(HDMI_CONTROL,
0589                     HDMI_DEEP_COLOR_DEPTH, 2,
0590                     HDMI_DEEP_COLOR_ENABLE, 0);
0591         } else {
0592             REG_UPDATE_2(HDMI_CONTROL,
0593                     HDMI_DEEP_COLOR_DEPTH, 2,
0594                     HDMI_DEEP_COLOR_ENABLE, 1);
0595             }
0596         break;
0597     case COLOR_DEPTH_161616:
0598         REG_UPDATE_2(HDMI_CONTROL,
0599                 HDMI_DEEP_COLOR_DEPTH, 3,
0600                 HDMI_DEEP_COLOR_ENABLE, 1);
0601         break;
0602     default:
0603         break;
0604     }
0605 
0606     if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
0607         if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
0608             /* enable HDMI data scrambler
0609              * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
0610              * Clock channel frequency is 1/4 of character rate.
0611              */
0612             REG_UPDATE_2(HDMI_CONTROL,
0613                 HDMI_DATA_SCRAMBLE_EN, 1,
0614                 HDMI_CLOCK_CHANNEL_RATE, 1);
0615         } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
0616 
0617             /* TODO: New feature for DCE11, still need to implement */
0618 
0619             /* enable HDMI data scrambler
0620              * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
0621              * Clock channel frequency is the same
0622              * as character rate
0623              */
0624             REG_UPDATE_2(HDMI_CONTROL,
0625                 HDMI_DATA_SCRAMBLE_EN, 1,
0626                 HDMI_CLOCK_CHANNEL_RATE, 0);
0627         }
0628     }
0629 
0630     REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
0631         HDMI_GC_CONT, 1,
0632         HDMI_GC_SEND, 1,
0633         HDMI_NULL_SEND, 1);
0634 
0635     REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
0636 
0637     /* following belongs to audio */
0638     REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
0639 
0640     REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
0641 
0642     REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
0643                 VBI_LINE_0 + 2);
0644 
0645     REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
0646 
0647 }
0648 
0649 /* setup stream encoder in dvi mode */
0650 static void dce110_stream_encoder_dvi_set_stream_attribute(
0651     struct stream_encoder *enc,
0652     struct dc_crtc_timing *crtc_timing,
0653     bool is_dual_link)
0654 {
0655     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0656     struct bp_encoder_control cntl = {0};
0657 
0658     cntl.action = ENCODER_CONTROL_SETUP;
0659     cntl.engine_id = enc110->base.id;
0660     cntl.signal = is_dual_link ?
0661             SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
0662     cntl.enable_dp_audio = false;
0663     cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
0664     cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
0665 
0666     if (enc110->base.bp->funcs->encoder_control(
0667             enc110->base.bp, &cntl) != BP_RESULT_OK)
0668         return;
0669 
0670     ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
0671     ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
0672     dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
0673 }
0674 
0675 /* setup stream encoder in LVDS mode */
0676 static void dce110_stream_encoder_lvds_set_stream_attribute(
0677     struct stream_encoder *enc,
0678     struct dc_crtc_timing *crtc_timing)
0679 {
0680     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0681     struct bp_encoder_control cntl = {0};
0682 
0683     cntl.action = ENCODER_CONTROL_SETUP;
0684     cntl.engine_id = enc110->base.id;
0685     cntl.signal = SIGNAL_TYPE_LVDS;
0686     cntl.enable_dp_audio = false;
0687     cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
0688     cntl.lanes_number = LANE_COUNT_FOUR;
0689 
0690     if (enc110->base.bp->funcs->encoder_control(
0691             enc110->base.bp, &cntl) != BP_RESULT_OK)
0692         return;
0693 
0694     ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
0695 }
0696 
0697 static void dce110_stream_encoder_set_throttled_vcp_size(
0698     struct stream_encoder *enc,
0699     struct fixed31_32 avg_time_slots_per_mtp)
0700 {
0701     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0702     uint32_t x = dc_fixpt_floor(
0703         avg_time_slots_per_mtp);
0704     uint32_t y = dc_fixpt_ceil(
0705         dc_fixpt_shl(
0706             dc_fixpt_sub_int(
0707                 avg_time_slots_per_mtp,
0708                 x),
0709             26));
0710 
0711     {
0712         REG_SET_2(DP_MSE_RATE_CNTL, 0,
0713             DP_MSE_RATE_X, x,
0714             DP_MSE_RATE_Y, y);
0715     }
0716 
0717     /* wait for update to be completed on the link */
0718     /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
0719     /* is reset to 0 (not pending) */
0720     REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
0721             0,
0722             10, DP_MST_UPDATE_MAX_RETRY);
0723 }
0724 
0725 static void dce110_stream_encoder_update_hdmi_info_packets(
0726     struct stream_encoder *enc,
0727     const struct encoder_info_frame *info_frame)
0728 {
0729     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0730 
0731     if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
0732             enc110->se_mask->HDMI_AVI_INFO_SEND) {
0733 
0734         if (info_frame->avi.valid) {
0735             const uint32_t *content =
0736                 (const uint32_t *) &info_frame->avi.sb[0];
0737             /*we need turn on clock before programming AFMT block*/
0738             if (REG(AFMT_CNTL))
0739                 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
0740 
0741             REG_WRITE(AFMT_AVI_INFO0, content[0]);
0742 
0743             REG_WRITE(AFMT_AVI_INFO1, content[1]);
0744 
0745             REG_WRITE(AFMT_AVI_INFO2, content[2]);
0746 
0747             REG_WRITE(AFMT_AVI_INFO3, content[3]);
0748 
0749             REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
0750                         info_frame->avi.hb1);
0751 
0752             REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
0753                     HDMI_AVI_INFO_SEND, 1,
0754                     HDMI_AVI_INFO_CONT, 1);
0755 
0756             REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
0757                             VBI_LINE_0 + 2);
0758 
0759         } else {
0760             REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
0761                 HDMI_AVI_INFO_SEND, 0,
0762                 HDMI_AVI_INFO_CONT, 0);
0763         }
0764     }
0765 
0766     if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
0767             enc110->se_mask->HDMI_AVI_INFO_SEND) {
0768         dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
0769         dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
0770         dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
0771         dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
0772     }
0773 
0774     if (enc110->se_mask->HDMI_DB_DISABLE) {
0775         /* for bring up, disable dp double  TODO */
0776         if (REG(HDMI_DB_CONTROL))
0777             REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
0778 
0779         dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
0780         dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
0781         dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
0782         dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
0783         dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
0784     }
0785 }
0786 
0787 static void dce110_stream_encoder_stop_hdmi_info_packets(
0788     struct stream_encoder *enc)
0789 {
0790     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0791 
0792     /* stop generic packets 0 & 1 on HDMI */
0793     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
0794         HDMI_GENERIC1_CONT, 0,
0795         HDMI_GENERIC1_LINE, 0,
0796         HDMI_GENERIC1_SEND, 0,
0797         HDMI_GENERIC0_CONT, 0,
0798         HDMI_GENERIC0_LINE, 0,
0799         HDMI_GENERIC0_SEND, 0);
0800 
0801     /* stop generic packets 2 & 3 on HDMI */
0802     REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
0803         HDMI_GENERIC0_CONT, 0,
0804         HDMI_GENERIC0_LINE, 0,
0805         HDMI_GENERIC0_SEND, 0,
0806         HDMI_GENERIC1_CONT, 0,
0807         HDMI_GENERIC1_LINE, 0,
0808         HDMI_GENERIC1_SEND, 0);
0809 
0810     /* stop generic packets 2 & 3 on HDMI */
0811     if (REG(HDMI_GENERIC_PACKET_CONTROL2))
0812         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
0813             HDMI_GENERIC0_CONT, 0,
0814             HDMI_GENERIC0_LINE, 0,
0815             HDMI_GENERIC0_SEND, 0,
0816             HDMI_GENERIC1_CONT, 0,
0817             HDMI_GENERIC1_LINE, 0,
0818             HDMI_GENERIC1_SEND, 0);
0819 
0820     if (REG(HDMI_GENERIC_PACKET_CONTROL3))
0821         REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
0822             HDMI_GENERIC0_CONT, 0,
0823             HDMI_GENERIC0_LINE, 0,
0824             HDMI_GENERIC0_SEND, 0,
0825             HDMI_GENERIC1_CONT, 0,
0826             HDMI_GENERIC1_LINE, 0,
0827             HDMI_GENERIC1_SEND, 0);
0828 }
0829 
0830 static void dce110_stream_encoder_update_dp_info_packets(
0831     struct stream_encoder *enc,
0832     const struct encoder_info_frame *info_frame)
0833 {
0834     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0835     uint32_t value = 0;
0836 
0837     if (info_frame->vsc.valid)
0838         dce110_update_generic_info_packet(
0839                     enc110,
0840                     0,  /* packetIndex */
0841                     &info_frame->vsc);
0842 
0843     if (info_frame->spd.valid)
0844         dce110_update_generic_info_packet(
0845                 enc110,
0846                 2,  /* packetIndex */
0847                 &info_frame->spd);
0848 
0849     if (info_frame->hdrsmd.valid)
0850         dce110_update_generic_info_packet(
0851                 enc110,
0852                 3,  /* packetIndex */
0853                 &info_frame->hdrsmd);
0854 
0855     /* enable/disable transmission of packet(s).
0856     *  If enabled, packet transmission begins on the next frame
0857     */
0858     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
0859     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
0860     REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
0861 
0862     /* This bit is the master enable bit.
0863     * When enabling secondary stream engine,
0864     * this master bit must also be set.
0865     * This register shared with audio info frame.
0866     * Therefore we need to enable master bit
0867     * if at least on of the fields is not 0
0868     */
0869     value = REG_READ(DP_SEC_CNTL);
0870     if (value)
0871         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0872 }
0873 
0874 static void dce110_stream_encoder_stop_dp_info_packets(
0875     struct stream_encoder *enc)
0876 {
0877     /* stop generic packets on DP */
0878     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0879     uint32_t value = 0;
0880 
0881     if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
0882         REG_SET_7(DP_SEC_CNTL, 0,
0883             DP_SEC_GSP0_ENABLE, 0,
0884             DP_SEC_GSP1_ENABLE, 0,
0885             DP_SEC_GSP2_ENABLE, 0,
0886             DP_SEC_GSP3_ENABLE, 0,
0887             DP_SEC_AVI_ENABLE, 0,
0888             DP_SEC_MPG_ENABLE, 0,
0889             DP_SEC_STREAM_ENABLE, 0);
0890     }
0891 
0892     /* this register shared with audio info frame.
0893      * therefore we need to keep master enabled
0894      * if at least one of the fields is not 0 */
0895     value = REG_READ(DP_SEC_CNTL);
0896     if (value)
0897         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
0898 
0899 }
0900 
0901 static void dce110_stream_encoder_dp_blank(
0902     struct dc_link *link,
0903     struct stream_encoder *enc)
0904 {
0905     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0906     uint32_t  reg1 = 0;
0907     uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
0908 
0909     /* Note: For CZ, we are changing driver default to disable
0910      * stream deferred to next VBLANK. If results are positive, we
0911      * will make the same change to all DCE versions. There are a
0912      * handful of panels that cannot handle disable stream at
0913      * HBLANK and will result in a white line flash across the
0914      * screen on stream disable. */
0915     REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
0916     if ((reg1 & 0x1) == 0)
0917         /*stream not enabled*/
0918         return;
0919     /* Specify the video stream disable point
0920      * (2 = start of the next vertical blank) */
0921     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
0922     /* Larger delay to wait until VBLANK - use max retry of
0923      * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
0924      * a little more because we may not trust delay accuracy.
0925      */
0926     max_retries = DP_BLANK_MAX_RETRY * 150;
0927 
0928     /* disable DP stream */
0929     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
0930 
0931     /* the encoder stops sending the video stream
0932      * at the start of the vertical blanking.
0933      * Poll for DP_VID_STREAM_STATUS == 0
0934      */
0935 
0936     REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
0937             0,
0938             10, max_retries);
0939 
0940     /* Tell the DP encoder to ignore timing from CRTC, must be done after
0941      * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
0942      * complete, stream status will be stuck in video stream enabled state,
0943      * i.e. DP_VID_STREAM_STATUS stuck at 1.
0944      */
0945 
0946     REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
0947 }
0948 
0949 /* output video stream to link encoder */
0950 static void dce110_stream_encoder_dp_unblank(
0951     struct dc_link *link,
0952     struct stream_encoder *enc,
0953     const struct encoder_unblank_param *param)
0954 {
0955     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
0956 
0957     if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
0958         uint32_t n_vid = 0x8000;
0959         uint32_t m_vid;
0960 
0961         /* M / N = Fstream / Flink
0962         * m_vid / n_vid = pixel rate / link rate
0963         */
0964 
0965         uint64_t m_vid_l = n_vid;
0966 
0967         m_vid_l *= param->timing.pix_clk_100hz / 10;
0968         m_vid_l = div_u64(m_vid_l,
0969             param->link_settings.link_rate
0970                 * LINK_RATE_REF_FREQ_IN_KHZ);
0971 
0972         m_vid = (uint32_t) m_vid_l;
0973 
0974         /* enable auto measurement */
0975 
0976         REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
0977 
0978         /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
0979          * therefore program initial value for Mvid and Nvid
0980          */
0981 
0982         REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
0983 
0984         REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
0985 
0986         REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
0987     }
0988 
0989     /* set DIG_START to 0x1 to resync FIFO */
0990 
0991     REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
0992 
0993     /* switch DP encoder to CRTC data */
0994 
0995     REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
0996 
0997     /* wait 100us for DIG/DP logic to prime
0998     * (i.e. a few video lines)
0999     */
1000     udelay(100);
1001 
1002     /* the hardware would start sending video at the start of the next DP
1003     * frame (i.e. rising edge of the vblank).
1004     * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1005     * register has no effect on enable transition! HW always guarantees
1006     * VID_STREAM enable at start of next frame, and this is not
1007     * programmable
1008     */
1009 
1010     REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1011 }
1012 
1013 static void dce110_stream_encoder_set_avmute(
1014     struct stream_encoder *enc,
1015     bool enable)
1016 {
1017     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1018     unsigned int value = enable ? 1 : 0;
1019 
1020     REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1021 }
1022 
1023 
1024 static void dce110_reset_hdmi_stream_attribute(
1025     struct stream_encoder *enc)
1026 {
1027     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1028     if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1029         REG_UPDATE_5(HDMI_CONTROL,
1030             HDMI_PACKET_GEN_VERSION, 1,
1031             HDMI_KEEPOUT_MODE, 1,
1032             HDMI_DEEP_COLOR_ENABLE, 0,
1033             HDMI_DATA_SCRAMBLE_EN, 0,
1034             HDMI_CLOCK_CHANNEL_RATE, 0);
1035     else
1036         REG_UPDATE_3(HDMI_CONTROL,
1037             HDMI_PACKET_GEN_VERSION, 1,
1038             HDMI_KEEPOUT_MODE, 1,
1039             HDMI_DEEP_COLOR_ENABLE, 0);
1040 }
1041 
1042 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1043 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1044 
1045 #include "include/audio_types.h"
1046 
1047 
1048 /* 25.2MHz/1.001*/
1049 /* 25.2MHz/1.001*/
1050 /* 25.2MHz*/
1051 /* 27MHz */
1052 /* 27MHz*1.001*/
1053 /* 27MHz*1.001*/
1054 /* 54MHz*/
1055 /* 54MHz*1.001*/
1056 /* 74.25MHz/1.001*/
1057 /* 74.25MHz*/
1058 /* 148.5MHz/1.001*/
1059 /* 148.5MHz*/
1060 
1061 static const struct audio_clock_info audio_clock_info_table[16] = {
1062     {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1063     {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1064     {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1065     {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1066     {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1067     {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1068     {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1069     {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1070     {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1071     {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1072     {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1073     {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1074     {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1075     {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1076     {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1077     {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1078 };
1079 
1080 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1081     {2517,  9152,  84375,  7007,  48875,  9152,  56250},
1082     {2518,  9152,  84375,  7007,  48875,  9152,  56250},
1083     {2520,  4096,  37800,  6272,  42000,  6144,  37800},
1084     {2700,  4096,  40500,  6272,  45000,  6144,  40500},
1085     {2702,  8192,  81081,  6272,  45045,  8192,  54054},
1086     {2703,  8192,  81081,  6272,  45045,  8192,  54054},
1087     {5400,  4096,  81000,  6272,  90000,  6144,  81000},
1088     {5405,  4096,  81081,  6272,  90090,  6144,  81081},
1089     {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1090     {7425, 4096, 111375,  6272, 123750,  6144, 111375},
1091     {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1092     {14850, 4096, 222750,  6272, 247500,  6144, 222750},
1093     {29670, 5824, 632812,  8918, 703125,  5824, 421875},
1094     {29700, 4096, 445500,  4704, 371250,  5120, 371250}
1095 };
1096 
1097 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1098     {2517,  4576,  56250,  7007,  62500,  6864,  56250},
1099     {2518,  4576,  56250,  7007,  62500,  6864,  56250},
1100     {2520,  4096,  50400,  6272,  56000,  6144,  50400},
1101     {2700,  4096,  54000,  6272,  60000,  6144,  54000},
1102     {2702,  4096,  54054,  6267,  60060,  8192,  54054},
1103     {2703,  4096,  54054,  6272,  60060,  8192,  54054},
1104     {5400,  4096, 108000,  6272, 120000,  6144, 108000},
1105     {5405,  4096, 108108,  6272, 120120,  6144, 108108},
1106     {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1107     {7425,  4096, 148500,  6272, 165000,  6144, 148500},
1108     {14835, 11648, 843750,  8918, 468750, 11648, 281250},
1109     {14850, 4096, 297000,  6272, 330000,  6144, 297000},
1110     {29670, 5824, 843750,  4459, 468750,  5824, 562500},
1111     {29700, 3072, 445500,  4704, 495000,  5120, 495000}
1112 
1113 
1114 };
1115 
1116 static union audio_cea_channels speakers_to_channels(
1117     struct audio_speaker_flags speaker_flags)
1118 {
1119     union audio_cea_channels cea_channels = {0};
1120 
1121     /* these are one to one */
1122     cea_channels.channels.FL = speaker_flags.FL_FR;
1123     cea_channels.channels.FR = speaker_flags.FL_FR;
1124     cea_channels.channels.LFE = speaker_flags.LFE;
1125     cea_channels.channels.FC = speaker_flags.FC;
1126 
1127     /* if Rear Left and Right exist move RC speaker to channel 7
1128      * otherwise to channel 5
1129      */
1130     if (speaker_flags.RL_RR) {
1131         cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1132         cea_channels.channels.RR = speaker_flags.RL_RR;
1133         cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1134     } else {
1135         cea_channels.channels.RL_RC = speaker_flags.RC;
1136     }
1137 
1138     /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1139     if (speaker_flags.FLC_FRC) {
1140         cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1141         cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1142     } else {
1143         cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1144         cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1145     }
1146 
1147     return cea_channels;
1148 }
1149 
1150 static uint32_t calc_max_audio_packets_per_line(
1151     const struct audio_crtc_info *crtc_info)
1152 {
1153     uint32_t max_packets_per_line;
1154 
1155     max_packets_per_line =
1156         crtc_info->h_total - crtc_info->h_active;
1157 
1158     if (crtc_info->pixel_repetition)
1159         max_packets_per_line *= crtc_info->pixel_repetition;
1160 
1161     /* for other hdmi features */
1162     max_packets_per_line -= 58;
1163     /* for Control Period */
1164     max_packets_per_line -= 16;
1165     /* Number of Audio Packets per Line */
1166     max_packets_per_line /= 32;
1167 
1168     return max_packets_per_line;
1169 }
1170 
1171 static void get_audio_clock_info(
1172     enum dc_color_depth color_depth,
1173     uint32_t crtc_pixel_clock_100Hz,
1174     uint32_t actual_pixel_clock_100Hz,
1175     struct audio_clock_info *audio_clock_info)
1176 {
1177     const struct audio_clock_info *clock_info;
1178     uint32_t index;
1179     uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1180     uint32_t audio_array_size;
1181 
1182     switch (color_depth) {
1183     case COLOR_DEPTH_161616:
1184         clock_info = audio_clock_info_table_48bpc;
1185         audio_array_size = ARRAY_SIZE(
1186                 audio_clock_info_table_48bpc);
1187         break;
1188     case COLOR_DEPTH_121212:
1189         clock_info = audio_clock_info_table_36bpc;
1190         audio_array_size = ARRAY_SIZE(
1191                 audio_clock_info_table_36bpc);
1192         break;
1193     default:
1194         clock_info = audio_clock_info_table;
1195         audio_array_size = ARRAY_SIZE(
1196                 audio_clock_info_table);
1197         break;
1198     }
1199 
1200     if (clock_info != NULL) {
1201         /* search for exact pixel clock in table */
1202         for (index = 0; index < audio_array_size; index++) {
1203             if (clock_info[index].pixel_clock_in_10khz >
1204                 crtc_pixel_clock_in_10khz)
1205                 break;  /* not match */
1206             else if (clock_info[index].pixel_clock_in_10khz ==
1207                     crtc_pixel_clock_in_10khz) {
1208                 /* match found */
1209                 *audio_clock_info = clock_info[index];
1210                 return;
1211             }
1212         }
1213     }
1214 
1215     /* not found */
1216     if (actual_pixel_clock_100Hz == 0)
1217         actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1218 
1219     /* See HDMI spec  the table entry under
1220      *  pixel clock of "Other". */
1221     audio_clock_info->pixel_clock_in_10khz =
1222             actual_pixel_clock_100Hz / 100;
1223     audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1224     audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1225     audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1226 
1227     audio_clock_info->n_32khz = 4096;
1228     audio_clock_info->n_44khz = 6272;
1229     audio_clock_info->n_48khz = 6144;
1230 }
1231 
1232 static void dce110_se_audio_setup(
1233     struct stream_encoder *enc,
1234     unsigned int az_inst,
1235     struct audio_info *audio_info)
1236 {
1237     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1238 
1239     uint32_t channels = 0;
1240 
1241     ASSERT(audio_info);
1242     if (audio_info == NULL)
1243         /* This should not happen.it does so we don't get BSOD*/
1244         return;
1245 
1246     channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1247 
1248     /* setup the audio stream source select (audio -> dig mapping) */
1249     REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1250 
1251     /* Channel allocation */
1252     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1253 }
1254 
1255 static void dce110_se_setup_hdmi_audio(
1256     struct stream_encoder *enc,
1257     const struct audio_crtc_info *crtc_info)
1258 {
1259     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1260 
1261     struct audio_clock_info audio_clock_info = {0};
1262     uint32_t max_packets_per_line;
1263 
1264     /* For now still do calculation, although this field is ignored when
1265     above HDMI_PACKET_GEN_VERSION set to 1 */
1266     max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1267 
1268     /* HDMI_AUDIO_PACKET_CONTROL */
1269     REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1270             HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1271             HDMI_AUDIO_DELAY_EN, 1);
1272 
1273     /* AFMT_AUDIO_PACKET_CONTROL */
1274     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1275 
1276     /* AFMT_AUDIO_PACKET_CONTROL2 */
1277     REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1278             AFMT_AUDIO_LAYOUT_OVRD, 0,
1279             AFMT_60958_OSF_OVRD, 0);
1280 
1281     /* HDMI_ACR_PACKET_CONTROL */
1282     REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1283             HDMI_ACR_AUTO_SEND, 1,
1284             HDMI_ACR_SOURCE, 0,
1285             HDMI_ACR_AUDIO_PRIORITY, 0);
1286 
1287     /* Program audio clock sample/regeneration parameters */
1288     get_audio_clock_info(crtc_info->color_depth,
1289                  crtc_info->requested_pixel_clock_100Hz,
1290                  crtc_info->calculated_pixel_clock_100Hz,
1291                  &audio_clock_info);
1292     DC_LOG_HW_AUDIO(
1293             "\n%s:Input::requested_pixel_clock_100Hz = %d"  \
1294             "calculated_pixel_clock_100Hz = %d \n", __func__,   \
1295             crtc_info->requested_pixel_clock_100Hz,     \
1296             crtc_info->calculated_pixel_clock_100Hz);
1297 
1298     /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1299     REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1300 
1301     /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1302     REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1303 
1304     /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1305     REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1306 
1307     /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1308     REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1309 
1310     /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1311     REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1312 
1313     /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1314     REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1315 
1316     /* Video driver cannot know in advance which sample rate will
1317        be used by HD Audio driver
1318        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1319        programmed below in interruppt callback */
1320 
1321     /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1322     AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1323     REG_UPDATE_2(AFMT_60958_0,
1324             AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1325             AFMT_60958_CS_CLOCK_ACCURACY, 0);
1326 
1327     /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1328     REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1329 
1330     /*AFMT_60958_2 now keep this settings until
1331      *  Programming guide comes out*/
1332     REG_UPDATE_6(AFMT_60958_2,
1333             AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1334             AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1335             AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1336             AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1337             AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1338             AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1339 }
1340 
1341 static void dce110_se_setup_dp_audio(
1342     struct stream_encoder *enc)
1343 {
1344     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1345 
1346     /* --- DP Audio packet configurations --- */
1347 
1348     /* ATP Configuration */
1349     REG_SET(DP_SEC_AUD_N, 0,
1350             DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1351 
1352     /* Async/auto-calc timestamp mode */
1353     REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1354             DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1355 
1356     /* --- The following are the registers
1357      *  copied from the SetupHDMI --- */
1358 
1359     /* AFMT_AUDIO_PACKET_CONTROL */
1360     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1361 
1362     /* AFMT_AUDIO_PACKET_CONTROL2 */
1363     /* Program the ATP and AIP next */
1364     REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1365             AFMT_AUDIO_LAYOUT_OVRD, 0,
1366             AFMT_60958_OSF_OVRD, 0);
1367 
1368     /* AFMT_INFOFRAME_CONTROL0 */
1369     REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1370 
1371     /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1372     REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1373 }
1374 
1375 static void dce110_se_enable_audio_clock(
1376     struct stream_encoder *enc,
1377     bool enable)
1378 {
1379     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1380 
1381     if (REG(AFMT_CNTL) == 0)
1382         return;   /* DCE8/10 does not have this register */
1383 
1384     REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1385 
1386     /* wait for AFMT clock to turn on,
1387      * expectation: this should complete in 1-2 reads
1388      *
1389      * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1390      *
1391      * TODO: wait for clock_on does not work well. May need HW
1392      * program sequence. But audio seems work normally even without wait
1393      * for clock_on status change
1394      */
1395 }
1396 
1397 static void dce110_se_enable_dp_audio(
1398     struct stream_encoder *enc)
1399 {
1400     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1401 
1402     /* Enable Audio packets */
1403     REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1404 
1405     /* Program the ATP and AIP next */
1406     REG_UPDATE_2(DP_SEC_CNTL,
1407             DP_SEC_ATP_ENABLE, 1,
1408             DP_SEC_AIP_ENABLE, 1);
1409 
1410     /* Program STREAM_ENABLE after all the other enables. */
1411     REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1412 }
1413 
1414 static void dce110_se_disable_dp_audio(
1415     struct stream_encoder *enc)
1416 {
1417     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1418     uint32_t value = 0;
1419 
1420     /* Disable Audio packets */
1421     REG_UPDATE_5(DP_SEC_CNTL,
1422             DP_SEC_ASP_ENABLE, 0,
1423             DP_SEC_ATP_ENABLE, 0,
1424             DP_SEC_AIP_ENABLE, 0,
1425             DP_SEC_ACM_ENABLE, 0,
1426             DP_SEC_STREAM_ENABLE, 0);
1427 
1428     /* This register shared with encoder info frame. Therefore we need to
1429     keep master enabled if at least on of the fields is not 0 */
1430     value = REG_READ(DP_SEC_CNTL);
1431     if (value != 0)
1432         REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1433 
1434 }
1435 
1436 void dce110_se_audio_mute_control(
1437     struct stream_encoder *enc,
1438     bool mute)
1439 {
1440     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1441 
1442     REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1443 }
1444 
1445 void dce110_se_dp_audio_setup(
1446     struct stream_encoder *enc,
1447     unsigned int az_inst,
1448     struct audio_info *info)
1449 {
1450     dce110_se_audio_setup(enc, az_inst, info);
1451 }
1452 
1453 void dce110_se_dp_audio_enable(
1454     struct stream_encoder *enc)
1455 {
1456     dce110_se_enable_audio_clock(enc, true);
1457     dce110_se_setup_dp_audio(enc);
1458     dce110_se_enable_dp_audio(enc);
1459 }
1460 
1461 void dce110_se_dp_audio_disable(
1462     struct stream_encoder *enc)
1463 {
1464     dce110_se_disable_dp_audio(enc);
1465     dce110_se_enable_audio_clock(enc, false);
1466 }
1467 
1468 void dce110_se_hdmi_audio_setup(
1469     struct stream_encoder *enc,
1470     unsigned int az_inst,
1471     struct audio_info *info,
1472     struct audio_crtc_info *audio_crtc_info)
1473 {
1474     dce110_se_enable_audio_clock(enc, true);
1475     dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1476     dce110_se_audio_setup(enc, az_inst, info);
1477 }
1478 
1479 void dce110_se_hdmi_audio_disable(
1480     struct stream_encoder *enc)
1481 {
1482     dce110_se_enable_audio_clock(enc, false);
1483 }
1484 
1485 
1486 static void setup_stereo_sync(
1487     struct stream_encoder *enc,
1488     int tg_inst, bool enable)
1489 {
1490     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1491     REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1492     REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1493 }
1494 
1495 static void dig_connect_to_otg(
1496     struct stream_encoder *enc,
1497     int tg_inst)
1498 {
1499     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1500 
1501     REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1502 }
1503 
1504 static unsigned int dig_source_otg(
1505     struct stream_encoder *enc)
1506 {
1507     uint32_t tg_inst = 0;
1508     struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1509 
1510     REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1511 
1512     return tg_inst;
1513 }
1514 
1515 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1516     .dp_set_stream_attribute =
1517         dce110_stream_encoder_dp_set_stream_attribute,
1518     .hdmi_set_stream_attribute =
1519         dce110_stream_encoder_hdmi_set_stream_attribute,
1520     .dvi_set_stream_attribute =
1521         dce110_stream_encoder_dvi_set_stream_attribute,
1522     .lvds_set_stream_attribute =
1523         dce110_stream_encoder_lvds_set_stream_attribute,
1524     .set_throttled_vcp_size =
1525         dce110_stream_encoder_set_throttled_vcp_size,
1526     .update_hdmi_info_packets =
1527         dce110_stream_encoder_update_hdmi_info_packets,
1528     .stop_hdmi_info_packets =
1529         dce110_stream_encoder_stop_hdmi_info_packets,
1530     .update_dp_info_packets =
1531         dce110_stream_encoder_update_dp_info_packets,
1532     .stop_dp_info_packets =
1533         dce110_stream_encoder_stop_dp_info_packets,
1534     .dp_blank =
1535         dce110_stream_encoder_dp_blank,
1536     .dp_unblank =
1537         dce110_stream_encoder_dp_unblank,
1538     .audio_mute_control = dce110_se_audio_mute_control,
1539 
1540     .dp_audio_setup = dce110_se_dp_audio_setup,
1541     .dp_audio_enable = dce110_se_dp_audio_enable,
1542     .dp_audio_disable = dce110_se_dp_audio_disable,
1543 
1544     .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1545     .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1546     .setup_stereo_sync  = setup_stereo_sync,
1547     .set_avmute = dce110_stream_encoder_set_avmute,
1548     .dig_connect_to_otg  = dig_connect_to_otg,
1549     .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1550     .dig_source_otg = dig_source_otg,
1551 };
1552 
1553 void dce110_stream_encoder_construct(
1554     struct dce110_stream_encoder *enc110,
1555     struct dc_context *ctx,
1556     struct dc_bios *bp,
1557     enum engine_id eng_id,
1558     const struct dce110_stream_enc_registers *regs,
1559     const struct dce_stream_encoder_shift *se_shift,
1560     const struct dce_stream_encoder_mask *se_mask)
1561 {
1562     enc110->base.funcs = &dce110_str_enc_funcs;
1563     enc110->base.ctx = ctx;
1564     enc110->base.id = eng_id;
1565     enc110->base.bp = bp;
1566     enc110->regs = regs;
1567     enc110->se_shift = se_shift;
1568     enc110->se_mask = se_mask;
1569 }
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