dc/dce/dce_panel_cntl.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_PANEL_CNTL__DCE_H__
0027 #define __DC_PANEL_CNTL__DCE_H__
0028
0029 #include "panel_cntl.h"
0030
0031 /* set register offset with instance */
0032 #define DCE_PANEL_CNTL_SR(reg_name, block)\
0033     .reg_name = mm ## block ## _ ## reg_name
0034
0035 #define DCE_PANEL_CNTL_REG_LIST()\
0036     DCE_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
0037     DCE_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
0038     DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
0039     SR(BL_PWM_CNTL), \
0040     SR(BL_PWM_CNTL2), \
0041     SR(BL_PWM_PERIOD_CNTL), \
0042     SR(BL_PWM_GRP1_REG_LOCK), \
0043     SR(BIOS_SCRATCH_2)
0044
0045 #define DCN_PANEL_CNTL_SR(reg_name, block)\
0046     .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
0047                     mm ## block ## _ ## reg_name
0048
0049 #define DCN_PANEL_CNTL_REG_LIST()\
0050     DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
0051     DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
0052     DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
0053     SR(BL_PWM_CNTL), \
0054     SR(BL_PWM_CNTL2), \
0055     SR(BL_PWM_PERIOD_CNTL), \
0056     SR(BL_PWM_GRP1_REG_LOCK), \
0057     NBIO_SR(BIOS_SCRATCH_2)
0058
0059 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
0060     .field_name = reg_name ## __ ## field_name ## post_fix
0061
0062 #define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
0063     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
0064     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
0065     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
0066     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
0067     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, mask_sh), \
0068     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
0069     DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
0070     DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
0071     DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
0072     DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
0073     DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
0074     DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
0075     DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
0076     DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
0077     DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
0078
0079 #define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
0080     type LVTMA_BLON;\
0081     type LVTMA_BLON_OVRD;\
0082     type LVTMA_DIGON;\
0083     type LVTMA_DIGON_OVRD;\
0084     type LVTMA_PWRSEQ_TARGET_STATE; \
0085     type LVTMA_PWRSEQ_TARGET_STATE_R; \
0086     type BL_PWM_REF_DIV; \
0087     type BL_PWM_EN; \
0088     type BL_ACTIVE_INT_FRAC_CNT; \
0089     type BL_PWM_FRACTIONAL_EN; \
0090     type BL_PWM_PERIOD; \
0091     type BL_PWM_PERIOD_BITCNT; \
0092     type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
0093     type BL_PWM_GRP1_REG_LOCK; \
0094     type BL_PWM_GRP1_REG_UPDATE_PENDING
0095
0096 struct dce_panel_cntl_shift {
0097     DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
0098 };
0099
0100 struct dce_panel_cntl_mask {
0101     DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
0102 };
0103
0104 struct dce_panel_cntl_registers {
0105     uint32_t PWRSEQ_CNTL;
0106     uint32_t PWRSEQ_STATE;
0107     uint32_t BL_PWM_CNTL;
0108     uint32_t BL_PWM_CNTL2;
0109     uint32_t BL_PWM_PERIOD_CNTL;
0110     uint32_t BL_PWM_GRP1_REG_LOCK;
0111     uint32_t PWRSEQ_REF_DIV;
0112     uint32_t BIOS_SCRATCH_2;
0113 };
0114
0115 struct dce_panel_cntl {
0116     struct panel_cntl base;
0117     const struct dce_panel_cntl_registers *regs;
0118     const struct dce_panel_cntl_shift *shift;
0119     const struct dce_panel_cntl_mask *mask;
0120 };
0121
0122 void dce_panel_cntl_construct(
0123     struct dce_panel_cntl *panel_cntl,
0124     const struct panel_cntl_init_data *init_data,
0125     const struct dce_panel_cntl_registers *regs,
0126     const struct dce_panel_cntl_shift *shift,
0127     const struct dce_panel_cntl_mask *mask);
0128
0129 #endif /* __DC_PANEL_CNTL__DCE_H__ */