dc/dce/dce_panel_cntl.c

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "reg_helper.h"
0027 #include "core_types.h"
0028 #include "dc_dmub_srv.h"
0029 #include "panel_cntl.h"
0030 #include "dce_panel_cntl.h"
0031 #include "atom.h"
0032
0033 #define TO_DCE_PANEL_CNTL(panel_cntl)\
0034     container_of(panel_cntl, struct dce_panel_cntl, base)
0035
0036 #define CTX \
0037     dce_panel_cntl->base.ctx
0038
0039 #define DC_LOGGER \
0040     dce_panel_cntl->base.ctx->logger
0041
0042 #define REG(reg)\
0043     dce_panel_cntl->regs->reg
0044
0045 #undef FN
0046 #define FN(reg_name, field_name) \
0047     dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
0048
0049 static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
0050 {
0051     uint64_t current_backlight;
0052     uint32_t bl_period, bl_int_count;
0053     uint32_t bl_pwm, fractional_duty_cycle_en;
0054     uint32_t bl_period_mask, bl_pwm_mask;
0055     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0056
0057     REG_READ(BL_PWM_PERIOD_CNTL);
0058     REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
0059     REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
0060
0061     REG_READ(BL_PWM_CNTL);
0062     REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
0063     REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
0064
0065     if (bl_int_count == 0)
0066         bl_int_count = 16;
0067
0068     bl_period_mask = (1 << bl_int_count) - 1;
0069     bl_period &= bl_period_mask;
0070
0071     bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
0072
0073     if (fractional_duty_cycle_en == 0)
0074         bl_pwm &= bl_pwm_mask;
0075     else
0076         bl_pwm &= 0xFFFF;
0077
0078     current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
0079
0080     if (bl_period == 0)
0081         bl_period = 0xFFFF;
0082
0083     current_backlight = div_u64(current_backlight, bl_period);
0084     current_backlight = (current_backlight + 1) >> 1;
0085
0086     return (uint32_t)(current_backlight);
0087 }
0088
0089 static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
0090 {
0091     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0092     uint32_t value;
0093     uint32_t current_backlight;
0094
0095     /* It must not be 0, so we have to restore them
0096      * Bios bug w/a - period resets to zero,
0097      * restoring to cache values which is always correct
0098      */
0099     REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
0100
0101     if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
0102         REG_WRITE(BL_PWM_CNTL,
0103                 panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
0104         REG_WRITE(BL_PWM_CNTL2,
0105                 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
0106         REG_WRITE(BL_PWM_PERIOD_CNTL,
0107                 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
0108         REG_UPDATE(PWRSEQ_REF_DIV,
0109             BL_PWM_REF_DIV,
0110             panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
0111     } else if ((value != 0) && (value != 1)) {
0112         panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
0113                 REG_READ(BL_PWM_CNTL);
0114         panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
0115                 REG_READ(BL_PWM_CNTL2);
0116         panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
0117                 REG_READ(BL_PWM_PERIOD_CNTL);
0118
0119         REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
0120                 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
0121     } else {
0122         /* TODO: Note: This should not really happen since VBIOS
0123          * should have initialized PWM registers on boot.
0124          */
0125         REG_WRITE(BL_PWM_CNTL, 0x8000FA00);
0126         REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
0127     }
0128
0129     // Have driver take backlight control
0130     // TakeBacklightControl(true)
0131     value = REG_READ(BIOS_SCRATCH_2);
0132     value |= ATOM_S2_VRI_BRIGHT_ENABLE;
0133     REG_WRITE(BIOS_SCRATCH_2, value);
0134
0135     // Enable the backlight output
0136     REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
0137
0138     // Unlock group 2 backlight registers
0139     REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
0140             BL_PWM_GRP1_REG_LOCK, 0);
0141
0142     current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
0143
0144     return current_backlight;
0145 }
0146
0147 static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
0148 {
0149     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0150     uint32_t blon, blon_ovrd, pwrseq_target_state;
0151
0152     REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
0153     REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state);
0154
0155     if (blon_ovrd)
0156         return blon;
0157     else
0158         return pwrseq_target_state;
0159 }
0160
0161 static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
0162 {
0163     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0164     uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
0165
0166     REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
0167
0168     REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
0169
0170     return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
0171 }
0172
0173 static void dce_store_backlight_level(struct panel_cntl *panel_cntl)
0174 {
0175     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0176
0177     panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
0178         REG_READ(BL_PWM_CNTL);
0179     panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
0180         REG_READ(BL_PWM_CNTL2);
0181     panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
0182         REG_READ(BL_PWM_PERIOD_CNTL);
0183
0184     REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
0185         &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
0186 }
0187
0188 static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
0189         uint32_t backlight_pwm_u16_16)
0190 {
0191     uint32_t backlight_16bit;
0192     uint32_t masked_pwm_period;
0193     uint8_t bit_count;
0194     uint64_t active_duty_cycle;
0195     uint32_t pwm_period_bitcnt;
0196     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
0197
0198     /*
0199      * 1. Find  16 bit backlight active duty cycle, where 0 <= backlight
0200      * active duty cycle <= backlight period
0201      */
0202
0203     /* 1.1 Apply bitmask for backlight period value based on value of BITCNT
0204      */
0205     REG_GET_2(BL_PWM_PERIOD_CNTL,
0206             BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
0207             BL_PWM_PERIOD, &masked_pwm_period);
0208
0209     if (pwm_period_bitcnt == 0)
0210         bit_count = 16;
0211     else
0212         bit_count = pwm_period_bitcnt;
0213
0214     /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
0215     masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
0216
0217     /* 1.2 Calculate integer active duty cycle required upper 16 bits
0218      * contain integer component, lower 16 bits contain fractional component
0219      * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
0220      */
0221     active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
0222
0223     /* 1.3 Calculate 16 bit active duty cycle from integer and fractional
0224      * components shift by bitCount then mask 16 bits and add rounding bit
0225      * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
0226      */
0227     backlight_16bit = active_duty_cycle >> bit_count;
0228     backlight_16bit &= 0xFFFF;
0229     backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
0230
0231     /*
0232      * 2. Program register with updated value
0233      */
0234
0235     /* 2.1 Lock group 2 backlight registers */
0236
0237     REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
0238             BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
0239             BL_PWM_GRP1_REG_LOCK, 1);
0240
0241     // 2.2 Write new active duty cycle
0242     REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
0243
0244     /* 2.3 Unlock group 2 backlight registers */
0245     REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
0246             BL_PWM_GRP1_REG_LOCK, 0);
0247
0248     /* 3 Wait for pending bit to be cleared */
0249     REG_WAIT(BL_PWM_GRP1_REG_LOCK,
0250             BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
0251             1, 10000);
0252 }
0253
0254 static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl)
0255 {
0256     struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl);
0257
0258     kfree(dce_panel_cntl);
0259     *panel_cntl = NULL;
0260 }
0261
0262 static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
0263     .destroy = dce_panel_cntl_destroy,
0264     .hw_init = dce_panel_cntl_hw_init,
0265     .is_panel_backlight_on = dce_is_panel_backlight_on,
0266     .is_panel_powered_on = dce_is_panel_powered_on,
0267     .store_backlight_level = dce_store_backlight_level,
0268     .driver_set_backlight = dce_driver_set_backlight,
0269     .get_current_backlight = dce_get_16_bit_backlight_from_pwm,
0270 };
0271
0272 void dce_panel_cntl_construct(
0273     struct dce_panel_cntl *dce_panel_cntl,
0274     const struct panel_cntl_init_data *init_data,
0275     const struct dce_panel_cntl_registers *regs,
0276     const struct dce_panel_cntl_shift *shift,
0277     const struct dce_panel_cntl_mask *mask)
0278 {
0279     struct panel_cntl *base = &dce_panel_cntl->base;
0280
0281     base->stored_backlight_registers.BL_PWM_CNTL = 0;
0282     base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
0283     base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
0284     base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
0285
0286     dce_panel_cntl->regs = regs;
0287     dce_panel_cntl->shift = shift;
0288     dce_panel_cntl->mask = mask;
0289
0290     dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
0291     dce_panel_cntl->base.ctx = init_data->ctx;
0292     dce_panel_cntl->base.inst = init_data->inst;
0293 }