dc/dce/dce_opp.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_OPP_DCE_H__
0026 #define __DC_OPP_DCE_H__
0027
0028 #include "dc_types.h"
0029 #include "opp.h"
0030 #include "core_types.h"
0031
0032 #define FROM_DCE11_OPP(opp)\
0033     container_of(opp, struct dce110_opp, base)
0034
0035 enum dce110_opp_reg_type {
0036     DCE110_OPP_REG_DCP = 0,
0037     DCE110_OPP_REG_DCFE,
0038     DCE110_OPP_REG_FMT,
0039
0040     DCE110_OPP_REG_MAX
0041 };
0042
0043 #define OPP_COMMON_REG_LIST_BASE(id) \
0044     SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
0045     SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
0046     SRI(FMT_CONTROL, FMT, id), \
0047     SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
0048     SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
0049     SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
0050     SRI(FMT_CLAMP_CNTL, FMT, id), \
0051     SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
0052     SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
0053     SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
0054
0055 #define OPP_DCE_80_REG_LIST(id) \
0056     OPP_COMMON_REG_LIST_BASE(id), \
0057     SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
0058     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
0059     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
0060
0061 #define OPP_DCE_100_REG_LIST(id) \
0062     OPP_COMMON_REG_LIST_BASE(id), \
0063     SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
0064     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
0065     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
0066
0067 #define OPP_DCE_110_REG_LIST(id) \
0068     OPP_COMMON_REG_LIST_BASE(id), \
0069     SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
0070     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
0071     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id)
0072
0073 #define OPP_DCE_112_REG_LIST(id) \
0074     OPP_COMMON_REG_LIST_BASE(id), \
0075     SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \
0076     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \
0077     SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \
0078     SRI(CONTROL, FMT_MEMORY, id)
0079
0080 #define OPP_DCE_120_REG_LIST(id) \
0081     OPP_COMMON_REG_LIST_BASE(id), \
0082     SRI(CONTROL, FMT_MEMORY, id)
0083
0084 #if defined(CONFIG_DRM_AMD_DC_SI)
0085 #define OPP_DCE_60_REG_LIST(id) \
0086     SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
0087     SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
0088     SRI(FMT_CONTROL, FMT, id), \
0089     SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
0090     SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
0091     SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
0092     SRI(FMT_CLAMP_CNTL, FMT, id)
0093 #endif
0094
0095 #define OPP_SF(reg_name, field_name, post_fix)\
0096     .field_name = reg_name ## __ ## field_name ## post_fix
0097
0098 #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
0099     OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
0100     OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
0101     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
0102     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
0103     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
0104     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
0105     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
0106     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
0107     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
0108     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
0109     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
0110     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
0111     OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
0112     OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
0113     OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
0114     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
0115     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
0116     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
0117     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
0118     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
0119     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
0120     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
0121     OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
0122     OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
0123     OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
0124     OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\
0125     OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\
0126     OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\
0127     OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\
0128     OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\
0129     OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\
0130     OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
0131     OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
0132     OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh)
0133
0134 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\
0135     OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
0136     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
0137     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
0138     OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
0139
0140 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\
0141     OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
0142     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
0143     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
0144     OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
0145
0146 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
0147     OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
0148     OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
0149     OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
0150     OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
0151     OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
0152     OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\
0153     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
0154     OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
0155     OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
0156
0157 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\
0158     OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
0159
0160 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\
0161     OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
0162     OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
0163     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
0164     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
0165     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
0166     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
0167     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
0168     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
0169     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
0170     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
0171     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
0172     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
0173     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
0174     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
0175     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
0176     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
0177     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
0178     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
0179     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
0180     OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
0181     OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\
0182     OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\
0183     OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\
0184     OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
0185     OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
0186     OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
0187     OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\
0188     OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\
0189     OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\
0190     OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\
0191     OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\
0192     OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
0193     OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
0194     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\
0195     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\
0196     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\
0197     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\
0198     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\
0199     OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\
0200     OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\
0201     OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\
0202     OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
0203     OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
0204
0205 #if defined(CONFIG_DRM_AMD_DC_SI)
0206 #define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\
0207     OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
0208     OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
0209     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
0210     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
0211     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
0212     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
0213     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
0214     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
0215     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
0216     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
0217     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
0218     OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
0219     OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
0220     OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
0221     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
0222     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
0223     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
0224     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
0225     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
0226     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
0227     OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
0228     OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
0229     OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
0230     OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh)
0231 #endif
0232
0233 #define OPP_REG_FIELD_LIST(type) \
0234     type FMT_DYNAMIC_EXP_EN; \
0235     type FMT_DYNAMIC_EXP_MODE; \
0236     type FMT_TRUNCATE_EN; \
0237     type FMT_TRUNCATE_DEPTH; \
0238     type FMT_TRUNCATE_MODE; \
0239     type FMT_SPATIAL_DITHER_EN; \
0240     type FMT_SPATIAL_DITHER_DEPTH; \
0241     type FMT_SPATIAL_DITHER_MODE; \
0242     type FMT_TEMPORAL_DITHER_EN; \
0243     type FMT_TEMPORAL_DITHER_RESET; \
0244     type FMT_TEMPORAL_DITHER_OFFSET; \
0245     type FMT_TEMPORAL_DITHER_DEPTH; \
0246     type FMT_TEMPORAL_LEVEL; \
0247     type FMT_25FRC_SEL; \
0248     type FMT_50FRC_SEL; \
0249     type FMT_75FRC_SEL; \
0250     type FMT_HIGHPASS_RANDOM_ENABLE; \
0251     type FMT_FRAME_RANDOM_ENABLE; \
0252     type FMT_RGB_RANDOM_ENABLE; \
0253     type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \
0254     type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \
0255     type FMT_STEREOSYNC_OVERRIDE; \
0256     type FMT_RAND_R_SEED; \
0257     type FMT_RAND_G_SEED; \
0258     type FMT_RAND_B_SEED; \
0259     type FMT420_MEM0_SOURCE_SEL; \
0260     type FMT420_MEM0_PWR_FORCE; \
0261     type FMT_SRC_SELECT; \
0262     type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \
0263     type FMT_420_PIXEL_PHASE_LOCKED; \
0264     type FMT_CLAMP_DATA_EN; \
0265     type FMT_CLAMP_COLOR_FORMAT; \
0266     type FMT_CLAMP_LOWER_R; \
0267     type FMT_CLAMP_UPPER_R; \
0268     type FMT_CLAMP_LOWER_G; \
0269     type FMT_CLAMP_UPPER_G; \
0270     type FMT_CLAMP_LOWER_B; \
0271     type FMT_CLAMP_UPPER_B; \
0272     type FMT_PIXEL_ENCODING; \
0273     type FMT_SUBSAMPLING_ORDER; \
0274     type FMT_SUBSAMPLING_MODE; \
0275     type FMT_CBCR_BIT_REDUCTION_BYPASS;\
0276
0277 struct dce_opp_shift {
0278     OPP_REG_FIELD_LIST(uint8_t)
0279 };
0280
0281 struct dce_opp_mask {
0282     OPP_REG_FIELD_LIST(uint32_t)
0283 };
0284
0285 struct dce_opp_registers {
0286     uint32_t FMT_DYNAMIC_EXP_CNTL;
0287     uint32_t FMT_BIT_DEPTH_CONTROL;
0288     uint32_t FMT_CONTROL;
0289     uint32_t FMT_DITHER_RAND_R_SEED;
0290     uint32_t FMT_DITHER_RAND_G_SEED;
0291     uint32_t FMT_DITHER_RAND_B_SEED;
0292     uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL;
0293     uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX;
0294     uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX;
0295     uint32_t CONTROL;
0296     uint32_t FMT_CLAMP_CNTL;
0297     uint32_t FMT_CLAMP_COMPONENT_R;
0298     uint32_t FMT_CLAMP_COMPONENT_G;
0299     uint32_t FMT_CLAMP_COMPONENT_B;
0300 };
0301
0302 /* OPP RELATED */
0303 #define TO_DCE110_OPP(opp)\
0304     container_of(opp, struct dce110_opp, base)
0305
0306 struct dce110_opp {
0307     struct output_pixel_processor base;
0308     const struct dce_opp_registers *regs;
0309     const struct dce_opp_shift *opp_shift;
0310     const struct dce_opp_mask *opp_mask;
0311 };
0312
0313 void dce110_opp_construct(struct dce110_opp *opp110,
0314     struct dc_context *ctx,
0315     uint32_t inst,
0316     const struct dce_opp_registers *regs,
0317     const struct dce_opp_shift *opp_shift,
0318     const struct dce_opp_mask *opp_mask);
0319
0320 #if defined(CONFIG_DRM_AMD_DC_SI)
0321 void dce60_opp_construct(struct dce110_opp *opp110,
0322     struct dc_context *ctx,
0323     uint32_t inst,
0324     const struct dce_opp_registers *regs,
0325     const struct dce_opp_shift *opp_shift,
0326     const struct dce_opp_mask *opp_mask);
0327 #endif
0328
0329 void dce110_opp_destroy(struct output_pixel_processor **opp);
0330
0331
0332
0333 /* FORMATTER RELATED */
0334 void dce110_opp_program_bit_depth_reduction(
0335     struct output_pixel_processor *opp,
0336     const struct bit_depth_reduction_params *params);
0337
0338 void dce110_opp_program_clamping_and_pixel_encoding(
0339     struct output_pixel_processor *opp,
0340     const struct clamping_and_pixel_encoding_params *params);
0341
0342 void dce110_opp_set_dyn_expansion(
0343     struct output_pixel_processor *opp,
0344     enum dc_color_space color_sp,
0345     enum dc_color_depth color_dpth,
0346     enum signal_type signal);
0347
0348 void dce110_opp_program_fmt(
0349     struct output_pixel_processor *opp,
0350     struct bit_depth_reduction_params *fmt_bit_depth,
0351     struct clamping_and_pixel_encoding_params *clamping);
0352
0353 void dce110_opp_set_clamping(
0354     struct dce110_opp *opp110,
0355     const struct clamping_and_pixel_encoding_params *params);
0356
0357 #endif