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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #ifndef __DCE_MEM_INPUT_H__
0026 #define __DCE_MEM_INPUT_H__
0027 
0028 #include "dc_hw_types.h"
0029 #include "mem_input.h"
0030 
0031 #define TO_DCE_MEM_INPUT(mem_input)\
0032     container_of(mem_input, struct dce_mem_input, base)
0033 
0034 #define MI_DCE_BASE_REG_LIST(id)\
0035     SRI(GRPH_ENABLE, DCP, id),\
0036     SRI(GRPH_CONTROL, DCP, id),\
0037     SRI(GRPH_X_START, DCP, id),\
0038     SRI(GRPH_Y_START, DCP, id),\
0039     SRI(GRPH_X_END, DCP, id),\
0040     SRI(GRPH_Y_END, DCP, id),\
0041     SRI(GRPH_PITCH, DCP, id),\
0042     SRI(HW_ROTATION, DCP, id),\
0043     SRI(GRPH_SWAP_CNTL, DCP, id),\
0044     SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
0045     SRI(GRPH_UPDATE, DCP, id),\
0046     SRI(GRPH_FLIP_CONTROL, DCP, id),\
0047     SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
0048     SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
0049     SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
0050     SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
0051     SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
0052     SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\
0053     SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
0054     SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
0055     SRI(DMIF_BUFFER_CONTROL, PIPE, id)
0056 
0057 #define MI_DCE_PTE_REG_LIST(id)\
0058     SRI(DVMM_PTE_CONTROL, DCP, id),\
0059     SRI(DVMM_PTE_ARB_CONTROL, DCP, id)
0060 
0061 #if defined(CONFIG_DRM_AMD_DC_SI)
0062 #define MI_DCE6_REG_LIST(id)\
0063     SRI(GRPH_ENABLE, DCP, id),\
0064     SRI(GRPH_CONTROL, DCP, id),\
0065     SRI(GRPH_X_START, DCP, id),\
0066     SRI(GRPH_Y_START, DCP, id),\
0067     SRI(GRPH_X_END, DCP, id),\
0068     SRI(GRPH_Y_END, DCP, id),\
0069     SRI(GRPH_PITCH, DCP, id),\
0070     SRI(GRPH_SWAP_CNTL, DCP, id),\
0071     SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
0072     SRI(GRPH_UPDATE, DCP, id),\
0073     SRI(GRPH_FLIP_CONTROL, DCP, id),\
0074     SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\
0075     SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\
0076     SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\
0077     SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\
0078     SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\
0079     SRI(DPG_PIPE_ARBITRATION_CONTROL3, DMIF_PG, id),\
0080     SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id),\
0081     SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
0082     SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\
0083     SRI(DMIF_BUFFER_CONTROL, PIPE, id)
0084 #endif
0085 
0086 #define MI_DCE8_REG_LIST(id)\
0087     MI_DCE_BASE_REG_LIST(id),\
0088     SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id)
0089 
0090 #define MI_DCE11_2_REG_LIST(id)\
0091     MI_DCE8_REG_LIST(id),\
0092     SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id)
0093 
0094 #define MI_DCE11_REG_LIST(id)\
0095     MI_DCE11_2_REG_LIST(id),\
0096     MI_DCE_PTE_REG_LIST(id)
0097 
0098 #define MI_DCE12_REG_LIST(id)\
0099     MI_DCE_BASE_REG_LIST(id),\
0100     MI_DCE_PTE_REG_LIST(id),\
0101     SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\
0102     SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\
0103     SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\
0104     SR(DCHUB_FB_LOCATION),\
0105     SR(DCHUB_AGP_BASE),\
0106     SR(DCHUB_AGP_BOT),\
0107     SR(DCHUB_AGP_TOP)
0108 
0109 struct dce_mem_input_registers {
0110     /* DCP */
0111     uint32_t GRPH_ENABLE;
0112     uint32_t GRPH_CONTROL;
0113     uint32_t GRPH_X_START;
0114     uint32_t GRPH_Y_START;
0115     uint32_t GRPH_X_END;
0116     uint32_t GRPH_Y_END;
0117     uint32_t GRPH_PITCH;
0118     uint32_t HW_ROTATION;
0119     uint32_t GRPH_SWAP_CNTL;
0120     uint32_t PRESCALE_GRPH_CONTROL;
0121     uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;
0122     uint32_t DVMM_PTE_CONTROL;
0123     uint32_t DVMM_PTE_ARB_CONTROL;
0124     uint32_t GRPH_UPDATE;
0125     uint32_t GRPH_FLIP_CONTROL;
0126     uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;
0127     uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
0128     uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;
0129     uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;
0130     /* DMIF_PG */
0131     uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
0132 #if defined(CONFIG_DRM_AMD_DC_SI)
0133     uint32_t DPG_PIPE_ARBITRATION_CONTROL3;
0134 #endif
0135     uint32_t DPG_WATERMARK_MASK_CONTROL;
0136     uint32_t DPG_PIPE_URGENCY_CONTROL;
0137     uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
0138     uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
0139     uint32_t DPG_PIPE_LOW_POWER_CONTROL;
0140     uint32_t DPG_PIPE_STUTTER_CONTROL;
0141     uint32_t DPG_PIPE_STUTTER_CONTROL2;
0142     /* DCI */
0143     uint32_t DMIF_BUFFER_CONTROL;
0144     /* MC_HUB */
0145     uint32_t MC_HUB_RDREQ_DMIF_LIMIT;
0146     /*DCHUB*/
0147     uint32_t DCHUB_FB_LOCATION;
0148     uint32_t DCHUB_AGP_BASE;
0149     uint32_t DCHUB_AGP_BOT;
0150     uint32_t DCHUB_AGP_TOP;
0151 };
0152 
0153 /* Set_Filed_for_Block */
0154 #define SFB(blk_name, reg_name, field_name, post_fix)\
0155     .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
0156 
0157 #if defined(CONFIG_DRM_AMD_DC_SI)
0158 #define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk)\
0159     SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
0160     SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
0161     SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
0162     SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
0163     SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
0164     SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
0165     SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
0166     SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
0167 #endif
0168 
0169 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
0170     SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
0171     SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
0172     SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
0173     SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
0174     SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
0175     SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
0176     SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
0177     SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
0178     SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
0179 
0180 #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
0181     SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
0182     SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
0183     SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
0184     SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
0185     SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
0186     SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
0187     SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
0188     SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
0189     SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
0190     SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
0191     SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
0192     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
0193     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
0194     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
0195     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
0196     SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0197     SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
0198     SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0199     SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
0200     SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
0201     SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
0202     SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
0203 
0204 #if defined(CONFIG_DRM_AMD_DC_SI)
0205 #define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk)\
0206     SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
0207     SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
0208     SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
0209     SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
0210     SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
0211     SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
0212     SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
0213     SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
0214     SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
0215     SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
0216     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
0217     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
0218     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
0219     SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\
0220     SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0221     SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\
0222     SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
0223     SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\
0224     SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\
0225     SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\
0226     SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)
0227 #endif
0228 
0229 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\
0230     SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)
0231 
0232 #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
0233     SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\
0234     SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\
0235     SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\
0236     SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\
0237     SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh)
0238 
0239 #if defined(CONFIG_DRM_AMD_DC_SI)
0240 #define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk)\
0241     SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
0242     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
0243     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
0244     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
0245     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
0246     SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
0247     SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
0248 
0249 #define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk)\
0250     SFB(blk, DPG_PIPE_ARBITRATION_CONTROL3, URGENCY_WATERMARK_MASK, mask_sh),\
0251     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
0252     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
0253     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
0254     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
0255     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
0256     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
0257     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
0258 
0259 #define MI_DCE6_MASK_SH_LIST(mask_sh)\
0260     MI_DCP_MASK_SH_LIST_DCE6(mask_sh, ),\
0261     MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, ),\
0262     MI_DMIF_PG_MASK_SH_DCE6(mask_sh, ),\
0263     MI_GFX6_TILE_MASK_SH_LIST(mask_sh, )
0264 #endif
0265 
0266 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
0267     SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\
0268     SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\
0269     SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\
0270     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
0271     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
0272     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\
0273     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\
0274     SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
0275     SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
0276 
0277 #define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\
0278     SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
0279     SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
0280     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\
0281     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
0282     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
0283     SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh)
0284 
0285 #define MI_DCE8_MASK_SH_LIST(mask_sh)\
0286     MI_DCP_MASK_SH_LIST(mask_sh, ),\
0287     MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\
0288     MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\
0289     MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
0290 
0291 #define MI_DCE11_2_MASK_SH_LIST(mask_sh)\
0292     MI_DCE8_MASK_SH_LIST(mask_sh),\
0293     MI_DCP_DCE11_MASK_SH_LIST(mask_sh, )
0294 
0295 #define MI_DCE11_MASK_SH_LIST(mask_sh)\
0296     MI_DCE11_2_MASK_SH_LIST(mask_sh),\
0297     MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
0298 
0299 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
0300     SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
0301     SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
0302     SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
0303     SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
0304     SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\
0305     SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
0306 
0307 #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
0308     SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
0309     SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
0310     SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
0311     SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
0312     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
0313     SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
0314     SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
0315     SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
0316     SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
0317     SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\
0318     SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)
0319 
0320 #define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
0321     SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
0322     SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
0323     SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
0324     SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
0325     SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
0326 
0327 #define MI_DCE12_MASK_SH_LIST(mask_sh)\
0328     MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\
0329     SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\
0330     MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\
0331     MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\
0332     MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
0333     MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\
0334     MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\
0335     MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
0336 
0337 #define MI_REG_FIELD_LIST(type) \
0338     type GRPH_ENABLE; \
0339     type GRPH_X_START; \
0340     type GRPH_Y_START; \
0341     type GRPH_X_END; \
0342     type GRPH_Y_END; \
0343     type GRPH_PITCH; \
0344     type GRPH_ROTATION_ANGLE; \
0345     type GRPH_RED_CROSSBAR; \
0346     type GRPH_BLUE_CROSSBAR; \
0347     type GRPH_PRESCALE_SELECT; \
0348     type GRPH_PRESCALE_R_SIGN; \
0349     type GRPH_PRESCALE_G_SIGN; \
0350     type GRPH_PRESCALE_B_SIGN; \
0351     type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \
0352     type DVMM_PAGE_WIDTH; \
0353     type DVMM_PAGE_HEIGHT; \
0354     type DVMM_MIN_PTE_BEFORE_FLIP; \
0355     type DVMM_PTE_REQ_PER_CHUNK; \
0356     type DVMM_MAX_PTE_REQ_OUTSTANDING; \
0357     type GRPH_DEPTH; \
0358     type GRPH_FORMAT; \
0359     type GRPH_NUM_BANKS; \
0360     type GRPH_BANK_WIDTH;\
0361     type GRPH_BANK_HEIGHT;\
0362     type GRPH_MACRO_TILE_ASPECT;\
0363     type GRPH_TILE_SPLIT;\
0364     type GRPH_MICRO_TILE_MODE;\
0365     type GRPH_PIPE_CONFIG;\
0366     type GRPH_ARRAY_MODE;\
0367     type GRPH_COLOR_EXPANSION_MODE;\
0368     type GRPH_SW_MODE; \
0369     type GRPH_SE_ENABLE; \
0370     type GRPH_NUM_SHADER_ENGINES; \
0371     type GRPH_NUM_PIPES; \
0372     type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \
0373     type GRPH_SECONDARY_SURFACE_ADDRESS; \
0374     type GRPH_SECONDARY_DFQ_ENABLE; \
0375     type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \
0376     type GRPH_PRIMARY_SURFACE_ADDRESS; \
0377     type GRPH_SURFACE_UPDATE_PENDING; \
0378     type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \
0379     type GRPH_UPDATE_LOCK; \
0380     type PIXEL_DURATION; \
0381     type URGENCY_WATERMARK_MASK; \
0382     type PSTATE_CHANGE_WATERMARK_MASK; \
0383     type NB_PSTATE_CHANGE_WATERMARK_MASK; \
0384     type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
0385     type URGENCY_LOW_WATERMARK; \
0386     type URGENCY_HIGH_WATERMARK; \
0387     type URGENT_LEVEL_LOW_WATERMARK;\
0388     type URGENT_LEVEL_HIGH_WATERMARK;\
0389     type NB_PSTATE_CHANGE_ENABLE; \
0390     type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
0391     type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
0392     type NB_PSTATE_CHANGE_WATERMARK; \
0393     type PSTATE_CHANGE_ENABLE; \
0394     type PSTATE_CHANGE_URGENT_DURING_REQUEST; \
0395     type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
0396     type PSTATE_CHANGE_WATERMARK; \
0397     type STUTTER_ENABLE; \
0398     type STUTTER_IGNORE_FBC; \
0399     type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
0400     type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \
0401     type DMIF_BUFFERS_ALLOCATED; \
0402     type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
0403     type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
0404     type FB_BASE; \
0405     type FB_TOP; \
0406     type AGP_BASE; \
0407     type AGP_TOP; \
0408     type AGP_BOT; \
0409 
0410 struct dce_mem_input_shift {
0411     MI_REG_FIELD_LIST(uint8_t)
0412 };
0413 
0414 struct dce_mem_input_mask {
0415     MI_REG_FIELD_LIST(uint32_t)
0416 };
0417 
0418 struct dce_mem_input_wa {
0419     uint8_t single_head_rdreq_dmif_limit;
0420 };
0421 
0422 struct dce_mem_input {
0423     struct mem_input base;
0424 
0425     const struct dce_mem_input_registers *regs;
0426     const struct dce_mem_input_shift *shifts;
0427     const struct dce_mem_input_mask *masks;
0428 
0429     struct dce_mem_input_wa wa;
0430 };
0431 
0432 void dce_mem_input_construct(
0433     struct dce_mem_input *dce_mi,
0434     struct dc_context *ctx,
0435     int inst,
0436     const struct dce_mem_input_registers *regs,
0437     const struct dce_mem_input_shift *mi_shift,
0438     const struct dce_mem_input_mask *mi_mask);
0439 
0440 #if defined(CONFIG_DRM_AMD_DC_SI)
0441 void dce60_mem_input_construct(
0442     struct dce_mem_input *dce_mi,
0443     struct dc_context *ctx,
0444     int inst,
0445     const struct dce_mem_input_registers *regs,
0446     const struct dce_mem_input_shift *mi_shift,
0447     const struct dce_mem_input_mask *mi_mask);
0448 #endif
0449 
0450 void dce112_mem_input_construct(
0451     struct dce_mem_input *dce_mi,
0452     struct dc_context *ctx,
0453     int inst,
0454     const struct dce_mem_input_registers *regs,
0455     const struct dce_mem_input_shift *mi_shift,
0456     const struct dce_mem_input_mask *mi_mask);
0457 
0458 void dce120_mem_input_construct(
0459     struct dce_mem_input *dce_mi,
0460     struct dc_context *ctx,
0461     int inst,
0462     const struct dce_mem_input_registers *regs,
0463     const struct dce_mem_input_shift *mi_shift,
0464     const struct dce_mem_input_mask *mi_mask);
0465 
0466 #endif /*__DCE_MEM_INPUT_H__*/
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