dc/dce/dce_link_encoder.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  *  and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DC_LINK_ENCODER__DCE110_H__
0027 #define __DC_LINK_ENCODER__DCE110_H__
0028
0029 #include "link_encoder.h"
0030
0031 #define TO_DCE110_LINK_ENC(link_encoder)\
0032     container_of(link_encoder, struct dce110_link_encoder, base)
0033
0034 /* Not found regs in dce120 spec
0035  * BIOS_SCRATCH_2
0036  * DP_DPHY_INTERNAL_CTRL
0037  */
0038
0039 #define AUX_REG_LIST(id)\
0040     SRI(AUX_CONTROL, DP_AUX, id), \
0041     SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
0042     SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
0043
0044 #define HPD_REG_LIST(id)\
0045     SRI(DC_HPD_CONTROL, HPD, id)
0046
0047 #define LE_COMMON_REG_LIST_BASE(id) \
0048     SR(DMCU_RAM_ACCESS_CTRL), \
0049     SR(DMCU_IRAM_RD_CTRL), \
0050     SR(DMCU_IRAM_RD_DATA), \
0051     SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
0052     SRI(DIG_BE_CNTL, DIG, id), \
0053     SRI(DIG_BE_EN_CNTL, DIG, id), \
0054     SRI(DP_CONFIG, DP, id), \
0055     SRI(DP_DPHY_CNTL, DP, id), \
0056     SRI(DP_DPHY_PRBS_CNTL, DP, id), \
0057     SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
0058     SRI(DP_DPHY_SYM0, DP, id), \
0059     SRI(DP_DPHY_SYM1, DP, id), \
0060     SRI(DP_DPHY_SYM2, DP, id), \
0061     SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
0062     SRI(DP_LINK_CNTL, DP, id), \
0063     SRI(DP_LINK_FRAMING_CNTL, DP, id), \
0064     SRI(DP_MSE_SAT0, DP, id), \
0065     SRI(DP_MSE_SAT1, DP, id), \
0066     SRI(DP_MSE_SAT2, DP, id), \
0067     SRI(DP_MSE_SAT_UPDATE, DP, id), \
0068     SRI(DP_SEC_CNTL, DP, id), \
0069     SRI(DP_VID_STREAM_CNTL, DP, id), \
0070     SRI(DP_DPHY_FAST_TRAINING, DP, id), \
0071     SRI(DP_SEC_CNTL1, DP, id)
0072
0073 #define LE_COMMON_REG_LIST(id)\
0074     LE_COMMON_REG_LIST_BASE(id), \
0075     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0076     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0077     SR(DCI_MEM_PWR_STATUS)
0078
0079 #if defined(CONFIG_DRM_AMD_DC_SI)
0080 #define LE_DCE60_REG_LIST(id)\
0081     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0082     SR(DMCU_RAM_ACCESS_CTRL), \
0083     SR(DMCU_IRAM_RD_CTRL), \
0084     SR(DMCU_IRAM_RD_DATA), \
0085     SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
0086     SRI(DIG_BE_CNTL, DIG, id), \
0087     SRI(DIG_BE_EN_CNTL, DIG, id), \
0088     SRI(DP_CONFIG, DP, id), \
0089     SRI(DP_DPHY_CNTL, DP, id), \
0090     SRI(DP_DPHY_PRBS_CNTL, DP, id), \
0091     SRI(DP_DPHY_SYM0, DP, id), \
0092     SRI(DP_DPHY_SYM1, DP, id), \
0093     SRI(DP_DPHY_SYM2, DP, id), \
0094     SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
0095     SRI(DP_LINK_CNTL, DP, id), \
0096     SRI(DP_LINK_FRAMING_CNTL, DP, id), \
0097     SRI(DP_MSE_SAT0, DP, id), \
0098     SRI(DP_MSE_SAT1, DP, id), \
0099     SRI(DP_MSE_SAT2, DP, id), \
0100     SRI(DP_MSE_SAT_UPDATE, DP, id), \
0101     SRI(DP_SEC_CNTL, DP, id), \
0102     SRI(DP_VID_STREAM_CNTL, DP, id), \
0103     SRI(DP_DPHY_FAST_TRAINING, DP, id), \
0104     SRI(DP_SEC_CNTL1, DP, id)
0105 #endif
0106
0107 #define LE_DCE80_REG_LIST(id)\
0108     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0109     LE_COMMON_REG_LIST_BASE(id)
0110
0111 #define LE_DCE100_REG_LIST(id)\
0112     LE_COMMON_REG_LIST_BASE(id), \
0113     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0114     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0115     SR(DCI_MEM_PWR_STATUS)
0116
0117 #define LE_DCE110_REG_LIST(id)\
0118     LE_COMMON_REG_LIST_BASE(id), \
0119     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0120     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0121     SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
0122     SR(DCI_MEM_PWR_STATUS)
0123
0124 #define LE_DCE120_REG_LIST(id)\
0125     LE_COMMON_REG_LIST_BASE(id), \
0126     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0127     SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \
0128     SR(DCI_MEM_PWR_STATUS)
0129
0130 #define LE_DCN10_REG_LIST(id)\
0131     LE_COMMON_REG_LIST_BASE(id), \
0132     SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
0133     SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
0134     SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
0135
0136 struct dce110_link_enc_aux_registers {
0137     uint32_t AUX_CONTROL;
0138     uint32_t AUX_DPHY_RX_CONTROL0;
0139     uint32_t AUX_DPHY_RX_CONTROL1;
0140 };
0141
0142 struct dce110_link_enc_hpd_registers {
0143     uint32_t DC_HPD_CONTROL;
0144 };
0145
0146 struct dce110_link_enc_registers {
0147     /* DMCU registers */
0148     uint32_t MASTER_COMM_DATA_REG1;
0149     uint32_t MASTER_COMM_DATA_REG2;
0150     uint32_t MASTER_COMM_DATA_REG3;
0151     uint32_t MASTER_COMM_CMD_REG;
0152     uint32_t MASTER_COMM_CNTL_REG;
0153     uint32_t DMCU_RAM_ACCESS_CTRL;
0154     uint32_t DCI_MEM_PWR_STATUS;
0155     uint32_t DMU_MEM_PWR_CNTL;
0156     uint32_t DMCU_IRAM_RD_CTRL;
0157     uint32_t DMCU_IRAM_RD_DATA;
0158     uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
0159
0160     /* Common DP registers */
0161     uint32_t DIG_BE_CNTL;
0162     uint32_t DIG_BE_EN_CNTL;
0163     uint32_t DP_CONFIG;
0164     uint32_t DP_DPHY_CNTL;
0165     uint32_t DP_DPHY_INTERNAL_CTRL;
0166     uint32_t DP_DPHY_PRBS_CNTL;
0167     uint32_t DP_DPHY_SCRAM_CNTL;
0168     uint32_t DP_DPHY_SYM0;
0169     uint32_t DP_DPHY_SYM1;
0170     uint32_t DP_DPHY_SYM2;
0171     uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
0172     uint32_t DP_LINK_CNTL;
0173     uint32_t DP_LINK_FRAMING_CNTL;
0174     uint32_t DP_MSE_SAT0;
0175     uint32_t DP_MSE_SAT1;
0176     uint32_t DP_MSE_SAT2;
0177     uint32_t DP_MSE_SAT_UPDATE;
0178     uint32_t DP_SEC_CNTL;
0179     uint32_t DP_VID_STREAM_CNTL;
0180     uint32_t DP_DPHY_FAST_TRAINING;
0181     uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
0182     uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
0183     uint32_t DP_SEC_CNTL1;
0184 };
0185
0186 struct dce110_link_encoder {
0187     struct link_encoder base;
0188     const struct dce110_link_enc_registers *link_regs;
0189     const struct dce110_link_enc_aux_registers *aux_regs;
0190     const struct dce110_link_enc_hpd_registers *hpd_regs;
0191 };
0192
0193
0194 void dce110_link_encoder_construct(
0195     struct dce110_link_encoder *enc110,
0196     const struct encoder_init_data *init_data,
0197     const struct encoder_feature_support *enc_features,
0198     const struct dce110_link_enc_registers *link_regs,
0199     const struct dce110_link_enc_aux_registers *aux_regs,
0200     const struct dce110_link_enc_hpd_registers *hpd_regs);
0201
0202 #if defined(CONFIG_DRM_AMD_DC_SI)
0203 void dce60_link_encoder_construct(
0204     struct dce110_link_encoder *enc110,
0205     const struct encoder_init_data *init_data,
0206     const struct encoder_feature_support *enc_features,
0207     const struct dce110_link_enc_registers *link_regs,
0208     const struct dce110_link_enc_aux_registers *aux_regs,
0209     const struct dce110_link_enc_hpd_registers *hpd_regs);
0210 #endif
0211
0212 bool dce110_link_encoder_validate_dvi_output(
0213     const struct dce110_link_encoder *enc110,
0214     enum signal_type connector_signal,
0215     enum signal_type signal,
0216     const struct dc_crtc_timing *crtc_timing);
0217
0218 bool dce110_link_encoder_validate_rgb_output(
0219     const struct dce110_link_encoder *enc110,
0220     const struct dc_crtc_timing *crtc_timing);
0221
0222 bool dce110_link_encoder_validate_dp_output(
0223     const struct dce110_link_encoder *enc110,
0224     const struct dc_crtc_timing *crtc_timing);
0225
0226 bool dce110_link_encoder_validate_wireless_output(
0227     const struct dce110_link_encoder *enc110,
0228     const struct dc_crtc_timing *crtc_timing);
0229
0230 bool dce110_link_encoder_validate_output_with_stream(
0231     struct link_encoder *enc,
0232     const struct dc_stream_state *stream);
0233
0234 /****************** HW programming ************************/
0235
0236 /* initialize HW */  /* why do we initialze aux in here? */
0237 void dce110_link_encoder_hw_init(struct link_encoder *enc);
0238
0239 void dce110_link_encoder_destroy(struct link_encoder **enc);
0240
0241 /* program DIG_MODE in DIG_BE */
0242 /* TODO can this be combined with enable_output? */
0243 void dce110_link_encoder_setup(
0244     struct link_encoder *enc,
0245     enum signal_type signal);
0246
0247 /* enables TMDS PHY output */
0248 /* TODO: still need depth or just pass in adjusted pixel clock? */
0249 void dce110_link_encoder_enable_tmds_output(
0250     struct link_encoder *enc,
0251     enum clock_source_id clock_source,
0252     enum dc_color_depth color_depth,
0253     enum signal_type signal,
0254     uint32_t pixel_clock);
0255
0256 /* enables DP PHY output */
0257 void dce110_link_encoder_enable_dp_output(
0258     struct link_encoder *enc,
0259     const struct dc_link_settings *link_settings,
0260     enum clock_source_id clock_source);
0261
0262 /* enables DP PHY output in MST mode */
0263 void dce110_link_encoder_enable_dp_mst_output(
0264     struct link_encoder *enc,
0265     const struct dc_link_settings *link_settings,
0266     enum clock_source_id clock_source);
0267
0268 /* enables LVDS PHY output */
0269 void dce110_link_encoder_enable_lvds_output(
0270     struct link_encoder *enc,
0271     enum clock_source_id clock_source,
0272     uint32_t pixel_clock);
0273
0274 /* disable PHY output */
0275 void dce110_link_encoder_disable_output(
0276     struct link_encoder *enc,
0277     enum signal_type signal);
0278
0279 /* set DP lane settings */
0280 void dce110_link_encoder_dp_set_lane_settings(
0281     struct link_encoder *enc,
0282     const struct dc_link_settings *link_settings,
0283     const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
0284
0285 void dce110_link_encoder_dp_set_phy_pattern(
0286     struct link_encoder *enc,
0287     const struct encoder_set_dp_phy_pattern_param *param);
0288
0289 /* programs DP MST VC payload allocation */
0290 void dce110_link_encoder_update_mst_stream_allocation_table(
0291     struct link_encoder *enc,
0292     const struct link_mst_stream_allocation_table *table);
0293
0294 void dce110_link_encoder_connect_dig_be_to_fe(
0295     struct link_encoder *enc,
0296     enum engine_id engine,
0297     bool connect);
0298
0299 unsigned int dce110_get_dig_frontend(struct link_encoder *enc);
0300
0301 void dce110_link_encoder_set_dp_phy_pattern_training_pattern(
0302     struct link_encoder *enc,
0303     uint32_t index);
0304
0305 void dce110_link_encoder_enable_hpd(struct link_encoder *enc);
0306
0307 void dce110_link_encoder_disable_hpd(struct link_encoder *enc);
0308
0309 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
0310             bool exit_link_training_required);
0311
0312 void dce110_psr_program_secondary_packet(struct link_encoder *enc,
0313             unsigned int sdp_transmit_line_num_deadline);
0314
0315 bool dce110_is_dig_enabled(struct link_encoder *enc);
0316
0317 void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc,
0318     struct dc_link_settings *link_settings);
0319
0320 #endif /* __DC_LINK_ENCODER__DCE110_H__ */