dc/dce/dce_ipp.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef _DCE_IPP_H_
0027 #define _DCE_IPP_H_
0028
0029 #include "ipp.h"
0030
0031 #define TO_DCE_IPP(ipp)\
0032     container_of(ipp, struct dce_ipp, base)
0033
0034 #define IPP_COMMON_REG_LIST_DCE_BASE(id) \
0035     SRI(CUR_UPDATE, DCP, id), \
0036     SRI(CUR_CONTROL, DCP, id), \
0037     SRI(CUR_POSITION, DCP, id), \
0038     SRI(CUR_HOT_SPOT, DCP, id), \
0039     SRI(CUR_COLOR1, DCP, id), \
0040     SRI(CUR_COLOR2, DCP, id), \
0041     SRI(CUR_SIZE, DCP, id), \
0042     SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
0043     SRI(CUR_SURFACE_ADDRESS, DCP, id), \
0044     SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
0045     SRI(PRESCALE_VALUES_GRPH_R, DCP, id), \
0046     SRI(PRESCALE_VALUES_GRPH_G, DCP, id), \
0047     SRI(PRESCALE_VALUES_GRPH_B, DCP, id), \
0048     SRI(INPUT_GAMMA_CONTROL, DCP, id), \
0049     SRI(DC_LUT_WRITE_EN_MASK, DCP, id), \
0050     SRI(DC_LUT_RW_MODE, DCP, id), \
0051     SRI(DC_LUT_CONTROL, DCP, id), \
0052     SRI(DC_LUT_RW_INDEX, DCP, id), \
0053     SRI(DC_LUT_SEQ_COLOR, DCP, id), \
0054     SRI(DEGAMMA_CONTROL, DCP, id)
0055
0056 #define IPP_DCE100_REG_LIST_DCE_BASE(id) \
0057     IPP_COMMON_REG_LIST_DCE_BASE(id), \
0058     SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
0059
0060 #define IPP_DCE110_REG_LIST_DCE_BASE(id) \
0061     IPP_COMMON_REG_LIST_DCE_BASE(id), \
0062     SRI(DCFE_MEM_PWR_CTRL, DCFE, id)
0063
0064 #define IPP_SF(reg_name, field_name, post_fix)\
0065     .field_name = reg_name ## __ ## field_name ## post_fix
0066
0067 #define IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0068     IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
0069     IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
0070     IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
0071     IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
0072     IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
0073     IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
0074     IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
0075     IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
0076     IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
0077     IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
0078     IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
0079     IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
0080     IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
0081     IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
0082     IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
0083     IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
0084     IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
0085     IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
0086     IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
0087     IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
0088     IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
0089     IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
0090     IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
0091     IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
0092     IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
0093     IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
0094     IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
0095     IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
0096     IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
0097     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
0098     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
0099     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
0100     IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
0101     IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
0102     IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
0103     IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
0104     IPP_SF(DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
0105
0106 #define IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0107     IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0108     IPP_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh)
0109
0110 #define IPP_DCE120_MASK_SH_LIST_SOC_BASE(mask_sh) \
0111     IPP_SF(DCP0_CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
0112     IPP_SF(DCP0_CUR_CONTROL, CURSOR_EN, mask_sh), \
0113     IPP_SF(DCP0_CUR_CONTROL, CURSOR_MODE, mask_sh), \
0114     IPP_SF(DCP0_CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
0115     IPP_SF(DCP0_CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
0116     IPP_SF(DCP0_CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
0117     IPP_SF(DCP0_CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
0118     IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
0119     IPP_SF(DCP0_CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
0120     IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
0121     IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
0122     IPP_SF(DCP0_CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
0123     IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
0124     IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
0125     IPP_SF(DCP0_CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
0126     IPP_SF(DCP0_CUR_SIZE, CURSOR_WIDTH, mask_sh), \
0127     IPP_SF(DCP0_CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
0128     IPP_SF(DCP0_CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
0129     IPP_SF(DCP0_CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
0130     IPP_SF(DCP0_PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
0131     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
0132     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
0133     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
0134     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
0135     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
0136     IPP_SF(DCP0_PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
0137     IPP_SF(DCP0_INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
0138     IPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh), \
0139     IPP_SF(DCP0_DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
0140     IPP_SF(DCP0_DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
0141     IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
0142     IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
0143     IPP_SF(DCP0_DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
0144     IPP_SF(DCP0_DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
0145     IPP_SF(DCP0_DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
0146     IPP_SF(DCP0_DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
0147     IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
0148     IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
0149
0150 #if defined(CONFIG_DRM_AMD_DC_SI)
0151 #define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0152     IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
0153     IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
0154     IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
0155     IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
0156     IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
0157     IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
0158     IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
0159     IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
0160     IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
0161     IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
0162     IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
0163     IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
0164     IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
0165     IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
0166     IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
0167     IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
0168     IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
0169     IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
0170     IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
0171     IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
0172     IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
0173     IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
0174     IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
0175     IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
0176     IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
0177     IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
0178     IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
0179     IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
0180     IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
0181     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
0182     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
0183     IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
0184     IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
0185     IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
0186     IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
0187     IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh)
0188 #endif
0189
0190 #define IPP_REG_FIELD_LIST(type) \
0191     type CURSOR_UPDATE_LOCK; \
0192     type CURSOR_EN; \
0193     type CURSOR_X_POSITION; \
0194     type CURSOR_Y_POSITION; \
0195     type CURSOR_HOT_SPOT_X; \
0196     type CURSOR_HOT_SPOT_Y; \
0197     type CURSOR_MODE; \
0198     type CURSOR_2X_MAGNIFY; \
0199     type CUR_INV_TRANS_CLAMP; \
0200     type CUR_COLOR1_BLUE; \
0201     type CUR_COLOR1_GREEN; \
0202     type CUR_COLOR1_RED; \
0203     type CUR_COLOR2_BLUE; \
0204     type CUR_COLOR2_GREEN; \
0205     type CUR_COLOR2_RED; \
0206     type CURSOR_WIDTH; \
0207     type CURSOR_HEIGHT; \
0208     type CURSOR_SURFACE_ADDRESS_HIGH; \
0209     type CURSOR_SURFACE_ADDRESS; \
0210     type GRPH_PRESCALE_BYPASS; \
0211     type GRPH_PRESCALE_SCALE_R; \
0212     type GRPH_PRESCALE_BIAS_R; \
0213     type GRPH_PRESCALE_SCALE_G; \
0214     type GRPH_PRESCALE_BIAS_G; \
0215     type GRPH_PRESCALE_SCALE_B; \
0216     type GRPH_PRESCALE_BIAS_B; \
0217     type GRPH_INPUT_GAMMA_MODE; \
0218     type DCP_LUT_MEM_PWR_DIS; \
0219     type DC_LUT_WRITE_EN_MASK; \
0220     type DC_LUT_RW_MODE; \
0221     type DC_LUT_DATA_R_FORMAT; \
0222     type DC_LUT_DATA_G_FORMAT; \
0223     type DC_LUT_DATA_B_FORMAT; \
0224     type DC_LUT_RW_INDEX; \
0225     type DC_LUT_SEQ_COLOR; \
0226     type GRPH_DEGAMMA_MODE; \
0227     type CURSOR_DEGAMMA_MODE; \
0228     type CURSOR2_DEGAMMA_MODE
0229
0230 struct dce_ipp_shift {
0231     IPP_REG_FIELD_LIST(uint8_t);
0232 };
0233
0234 struct dce_ipp_mask {
0235     IPP_REG_FIELD_LIST(uint32_t);
0236 };
0237
0238 struct dce_ipp_registers {
0239     uint32_t CUR_UPDATE;
0240     uint32_t CUR_CONTROL;
0241     uint32_t CUR_POSITION;
0242     uint32_t CUR_HOT_SPOT;
0243     uint32_t CUR_COLOR1;
0244     uint32_t CUR_COLOR2;
0245     uint32_t CUR_SIZE;
0246     uint32_t CUR_SURFACE_ADDRESS_HIGH;
0247     uint32_t CUR_SURFACE_ADDRESS;
0248     uint32_t PRESCALE_GRPH_CONTROL;
0249     uint32_t PRESCALE_VALUES_GRPH_R;
0250     uint32_t PRESCALE_VALUES_GRPH_G;
0251     uint32_t PRESCALE_VALUES_GRPH_B;
0252     uint32_t INPUT_GAMMA_CONTROL;
0253     uint32_t DCFE_MEM_PWR_CTRL;
0254     uint32_t DC_LUT_WRITE_EN_MASK;
0255     uint32_t DC_LUT_RW_MODE;
0256     uint32_t DC_LUT_CONTROL;
0257     uint32_t DC_LUT_RW_INDEX;
0258     uint32_t DC_LUT_SEQ_COLOR;
0259     uint32_t DEGAMMA_CONTROL;
0260 };
0261
0262 struct dce_ipp {
0263     struct input_pixel_processor base;
0264     const struct dce_ipp_registers *regs;
0265     const struct dce_ipp_shift *ipp_shift;
0266     const struct dce_ipp_mask *ipp_mask;
0267 };
0268
0269 void dce_ipp_construct(struct dce_ipp *ipp_dce,
0270     struct dc_context *ctx,
0271     int inst,
0272     const struct dce_ipp_registers *regs,
0273     const struct dce_ipp_shift *ipp_shift,
0274     const struct dce_ipp_mask *ipp_mask);
0275
0276 #if defined(CONFIG_DRM_AMD_DC_SI)
0277 void dce60_ipp_construct(struct dce_ipp *ipp_dce,
0278     struct dc_context *ctx,
0279     int inst,
0280     const struct dce_ipp_registers *regs,
0281     const struct dce_ipp_shift *ipp_shift,
0282     const struct dce_ipp_mask *ipp_mask);
0283 #endif
0284
0285 void dce_ipp_destroy(struct input_pixel_processor **ipp);
0286
0287 #endif /* _DCE_IPP_H_ */