dc/dce/dce_i2c_hw.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DCE_I2C_HW_H__
0027 #define __DCE_I2C_HW_H__
0028
0029 enum dc_i2c_status {
0030     DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
0031     DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
0032     DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW,
0033     DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY = 2,
0034 };
0035
0036 enum dc_i2c_arbitration {
0037     DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
0038     DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
0039 };
0040
0041 enum i2c_channel_operation_result {
0042     I2C_CHANNEL_OPERATION_SUCCEEDED,
0043     I2C_CHANNEL_OPERATION_FAILED,
0044     I2C_CHANNEL_OPERATION_NOT_GRANTED,
0045     I2C_CHANNEL_OPERATION_IS_BUSY,
0046     I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
0047     I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
0048     I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
0049     I2C_CHANNEL_OPERATION_ENGINE_BUSY,
0050     I2C_CHANNEL_OPERATION_TIMEOUT,
0051     I2C_CHANNEL_OPERATION_NO_RESPONSE,
0052     I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
0053     I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
0054     I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
0055     I2C_CHANNEL_OPERATION_NOT_STARTED
0056 };
0057
0058
0059 enum dce_i2c_transaction_action {
0060     DCE_I2C_TRANSACTION_ACTION_I2C_WRITE = 0x00,
0061     DCE_I2C_TRANSACTION_ACTION_I2C_READ = 0x10,
0062     DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
0063
0064     DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
0065     DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
0066     DCE_I2C_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
0067
0068     DCE_I2C_TRANSACTION_ACTION_DP_WRITE = 0x80,
0069     DCE_I2C_TRANSACTION_ACTION_DP_READ = 0x90
0070 };
0071
0072 enum {
0073     I2C_SETUP_TIME_LIMIT_DCE = 255,
0074     I2C_SETUP_TIME_LIMIT_DCN = 3,
0075     I2C_HW_BUFFER_SIZE_DCE100 = 538,
0076     I2C_HW_BUFFER_SIZE_DCE = 144,
0077     I2C_SEND_RESET_LENGTH_9 = 9,
0078     I2C_SEND_RESET_LENGTH_10 = 10,
0079     DEFAULT_I2C_HW_SPEED = 50,
0080     DEFAULT_I2C_HW_SPEED_100KHZ = 100,
0081     TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32,
0082 };
0083
0084 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
0085     SRI(SETUP, DC_I2C_DDC, id),\
0086     SRI(SPEED, DC_I2C_DDC, id),\
0087     SRI(HW_STATUS, DC_I2C_DDC, id),\
0088     SR(DC_I2C_ARBITRATION),\
0089     SR(DC_I2C_CONTROL),\
0090     SR(DC_I2C_SW_STATUS),\
0091     SR(DC_I2C_TRANSACTION0),\
0092     SR(DC_I2C_TRANSACTION1),\
0093     SR(DC_I2C_TRANSACTION2),\
0094     SR(DC_I2C_TRANSACTION3),\
0095     SR(DC_I2C_DATA),\
0096     SR(MICROSECOND_TIME_BASE_DIV)
0097
0098 #define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\
0099     I2C_HW_ENGINE_COMMON_REG_LIST(id),\
0100     SR(DIO_MEM_PWR_CTRL),\
0101     SR(DIO_MEM_PWR_STATUS)
0102
0103 #define I2C_SF(reg_name, field_name, post_fix)\
0104     .field_name = reg_name ## __ ## field_name ## post_fix
0105
0106 #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
0107     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
0108     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
0109     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
0110     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
0111     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
0112     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
0113     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
0114     I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\
0115     I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\
0116     I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
0117     I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
0118     I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
0119     I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
0120     I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
0121     I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
0122     I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
0123     I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
0124     I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
0125     I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
0126     I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
0127     I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
0128     I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
0129     I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
0130     I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
0131     I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
0132     I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
0133     I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
0134     I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
0135     I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
0136     I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
0137     I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
0138     I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
0139     I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
0140     I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
0141     I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh),\
0142     I2C_SF(MICROSECOND_TIME_BASE_DIV, MICROSECOND_TIME_BASE_DIV, mask_sh),\
0143     I2C_SF(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, mask_sh)
0144
0145 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
0146     I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
0147     I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
0148
0149 struct dce_i2c_shift {
0150     uint8_t DC_I2C_DDC1_ENABLE;
0151     uint8_t DC_I2C_DDC1_TIME_LIMIT;
0152     uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
0153     uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
0154     uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
0155     uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
0156     uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
0157     uint8_t DC_I2C_DDC1_HW_STATUS;
0158     uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
0159     uint8_t DC_I2C_SW_USE_I2C_REG_REQ;
0160     uint8_t DC_I2C_NO_QUEUED_SW_GO;
0161     uint8_t DC_I2C_SW_PRIORITY;
0162     uint8_t DC_I2C_SOFT_RESET;
0163     uint8_t DC_I2C_SW_STATUS_RESET;
0164     uint8_t DC_I2C_GO;
0165     uint8_t DC_I2C_SEND_RESET;
0166     uint8_t DC_I2C_TRANSACTION_COUNT;
0167     uint8_t DC_I2C_DDC_SELECT;
0168     uint8_t DC_I2C_DDC1_PRESCALE;
0169     uint8_t DC_I2C_DDC1_THRESHOLD;
0170     uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
0171     uint8_t DC_I2C_SW_STOPPED_ON_NACK;
0172     uint8_t DC_I2C_SW_TIMEOUT;
0173     uint8_t DC_I2C_SW_ABORTED;
0174     uint8_t DC_I2C_SW_DONE;
0175     uint8_t DC_I2C_SW_STATUS;
0176     uint8_t DC_I2C_STOP_ON_NACK0;
0177     uint8_t DC_I2C_START0;
0178     uint8_t DC_I2C_RW0;
0179     uint8_t DC_I2C_STOP0;
0180     uint8_t DC_I2C_COUNT0;
0181     uint8_t DC_I2C_DATA_RW;
0182     uint8_t DC_I2C_DATA;
0183     uint8_t DC_I2C_INDEX;
0184     uint8_t DC_I2C_INDEX_WRITE;
0185     uint8_t XTAL_REF_DIV;
0186     uint8_t MICROSECOND_TIME_BASE_DIV;
0187     uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
0188     uint8_t DC_I2C_REG_RW_CNTL_STATUS;
0189     uint8_t I2C_LIGHT_SLEEP_FORCE;
0190     uint8_t I2C_MEM_PWR_STATE;
0191 };
0192
0193 struct dce_i2c_mask {
0194     uint32_t DC_I2C_DDC1_ENABLE;
0195     uint32_t DC_I2C_DDC1_TIME_LIMIT;
0196     uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
0197     uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
0198     uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
0199     uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
0200     uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
0201     uint32_t DC_I2C_DDC1_HW_STATUS;
0202     uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
0203     uint32_t DC_I2C_SW_USE_I2C_REG_REQ;
0204     uint32_t DC_I2C_NO_QUEUED_SW_GO;
0205     uint32_t DC_I2C_SW_PRIORITY;
0206     uint32_t DC_I2C_SOFT_RESET;
0207     uint32_t DC_I2C_SW_STATUS_RESET;
0208     uint32_t DC_I2C_GO;
0209     uint32_t DC_I2C_SEND_RESET;
0210     uint32_t DC_I2C_TRANSACTION_COUNT;
0211     uint32_t DC_I2C_DDC_SELECT;
0212     uint32_t DC_I2C_DDC1_PRESCALE;
0213     uint32_t DC_I2C_DDC1_THRESHOLD;
0214     uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
0215     uint32_t DC_I2C_SW_STOPPED_ON_NACK;
0216     uint32_t DC_I2C_SW_TIMEOUT;
0217     uint32_t DC_I2C_SW_ABORTED;
0218     uint32_t DC_I2C_SW_DONE;
0219     uint32_t DC_I2C_SW_STATUS;
0220     uint32_t DC_I2C_STOP_ON_NACK0;
0221     uint32_t DC_I2C_START0;
0222     uint32_t DC_I2C_RW0;
0223     uint32_t DC_I2C_STOP0;
0224     uint32_t DC_I2C_COUNT0;
0225     uint32_t DC_I2C_DATA_RW;
0226     uint32_t DC_I2C_DATA;
0227     uint32_t DC_I2C_INDEX;
0228     uint32_t DC_I2C_INDEX_WRITE;
0229     uint32_t XTAL_REF_DIV;
0230     uint32_t MICROSECOND_TIME_BASE_DIV;
0231     uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
0232     uint32_t DC_I2C_REG_RW_CNTL_STATUS;
0233     uint32_t I2C_LIGHT_SLEEP_FORCE;
0234     uint32_t I2C_MEM_PWR_STATE;
0235 };
0236
0237 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
0238     I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
0239     I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
0240
0241 #define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
0242     I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\
0243     I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
0244     I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
0245
0246 struct dce_i2c_registers {
0247     uint32_t SETUP;
0248     uint32_t SPEED;
0249     uint32_t HW_STATUS;
0250     uint32_t DC_I2C_ARBITRATION;
0251     uint32_t DC_I2C_CONTROL;
0252     uint32_t DC_I2C_SW_STATUS;
0253     uint32_t DC_I2C_TRANSACTION0;
0254     uint32_t DC_I2C_TRANSACTION1;
0255     uint32_t DC_I2C_TRANSACTION2;
0256     uint32_t DC_I2C_TRANSACTION3;
0257     uint32_t DC_I2C_DATA;
0258     uint32_t MICROSECOND_TIME_BASE_DIV;
0259     uint32_t DIO_MEM_PWR_CTRL;
0260     uint32_t DIO_MEM_PWR_STATUS;
0261 };
0262
0263 enum dce_i2c_transaction_address_space {
0264     DCE_I2C_TRANSACTION_ADDRESS_SPACE_I2C = 1,
0265     DCE_I2C_TRANSACTION_ADDRESS_SPACE_DPCD
0266 };
0267
0268 struct i2c_request_transaction_data {
0269     enum dce_i2c_transaction_action action;
0270     enum i2c_channel_operation_result status;
0271     uint8_t address;
0272     uint32_t length;
0273     uint8_t *data;
0274 };
0275
0276 struct dce_i2c_hw {
0277     struct ddc *ddc;
0278     uint32_t engine_keep_power_up_count;
0279     uint32_t transaction_count;
0280     uint32_t buffer_used_bytes;
0281     uint32_t buffer_used_write;
0282     uint32_t reference_frequency;
0283     uint32_t default_speed;
0284     uint32_t engine_id;
0285     uint32_t setup_limit;
0286     uint32_t send_reset_length;
0287     uint32_t buffer_size;
0288     struct dc_context *ctx;
0289
0290     const struct dce_i2c_registers *regs;
0291     const struct dce_i2c_shift *shifts;
0292     const struct dce_i2c_mask *masks;
0293 };
0294
0295 void dce_i2c_hw_construct(
0296     struct dce_i2c_hw *dce_i2c_hw,
0297     struct dc_context *ctx,
0298     uint32_t engine_id,
0299     const struct dce_i2c_registers *regs,
0300     const struct dce_i2c_shift *shifts,
0301     const struct dce_i2c_mask *masks);
0302
0303 void dce100_i2c_hw_construct(
0304     struct dce_i2c_hw *dce_i2c_hw,
0305     struct dc_context *ctx,
0306     uint32_t engine_id,
0307     const struct dce_i2c_registers *regs,
0308     const struct dce_i2c_shift *shifts,
0309     const struct dce_i2c_mask *masks);
0310
0311 void dce112_i2c_hw_construct(
0312     struct dce_i2c_hw *dce_i2c_hw,
0313     struct dc_context *ctx,
0314     uint32_t engine_id,
0315     const struct dce_i2c_registers *regs,
0316     const struct dce_i2c_shift *shifts,
0317     const struct dce_i2c_mask *masks);
0318
0319 void dcn1_i2c_hw_construct(
0320     struct dce_i2c_hw *dce_i2c_hw,
0321     struct dc_context *ctx,
0322     uint32_t engine_id,
0323     const struct dce_i2c_registers *regs,
0324     const struct dce_i2c_shift *shifts,
0325     const struct dce_i2c_mask *masks);
0326
0327 void dcn2_i2c_hw_construct(
0328     struct dce_i2c_hw *dce_i2c_hw,
0329     struct dc_context *ctx,
0330     uint32_t engine_id,
0331     const struct dce_i2c_registers *regs,
0332     const struct dce_i2c_shift *shifts,
0333     const struct dce_i2c_mask *masks);
0334
0335 bool dce_i2c_submit_command_hw(
0336     struct resource_pool *pool,
0337     struct ddc *ddc,
0338     struct i2c_command *cmd,
0339     struct dce_i2c_hw *dce_i2c_hw);
0340
0341 struct dce_i2c_hw *acquire_i2c_hw_engine(
0342     struct resource_pool *pool,
0343     struct ddc *ddc);
0344
0345 #endif