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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #ifndef __DCE_HWSEQ_H__
0026 #define __DCE_HWSEQ_H__
0027 
0028 #include "dc_types.h"
0029 
0030 #define HWSEQ_DCEF_REG_LIST_DCE8() \
0031     .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \
0032     .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
0033     .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \
0034     .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \
0035     .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \
0036     .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL
0037 
0038 #define HWSEQ_DCEF_REG_LIST() \
0039     SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
0040     SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
0041     SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
0042     SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
0043     SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
0044     SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
0045     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
0046 
0047 #define HWSEQ_BLND_REG_LIST() \
0048     SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
0049     SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
0050     SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
0051     SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
0052     SRII(BLND_V_UPDATE_LOCK, BLND, 4), \
0053     SRII(BLND_V_UPDATE_LOCK, BLND, 5), \
0054     SRII(BLND_CONTROL, BLND, 0), \
0055     SRII(BLND_CONTROL, BLND, 1), \
0056     SRII(BLND_CONTROL, BLND, 2), \
0057     SRII(BLND_CONTROL, BLND, 3), \
0058     SRII(BLND_CONTROL, BLND, 4), \
0059     SRII(BLND_CONTROL, BLND, 5)
0060 
0061 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
0062     SRII(PIXEL_RATE_CNTL, blk, inst), \
0063     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
0064 
0065 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
0066     SRII(PIXEL_RATE_CNTL, blk, 0), \
0067     SRII(PIXEL_RATE_CNTL, blk, 1), \
0068     SRII(PIXEL_RATE_CNTL, blk, 2), \
0069     SRII(PIXEL_RATE_CNTL, blk, 3), \
0070     SRII(PIXEL_RATE_CNTL, blk, 4), \
0071     SRII(PIXEL_RATE_CNTL, blk, 5)
0072 
0073 #define HWSEQ_PIXEL_RATE_REG_LIST_201(blk) \
0074     SRII(PIXEL_RATE_CNTL, blk, 0), \
0075     SRII(PIXEL_RATE_CNTL, blk, 1)
0076 
0077 #define HWSEQ_PHYPLL_REG_LIST(blk) \
0078     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
0079     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
0080     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
0081     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
0082     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
0083     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
0084 
0085 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \
0086     SRII(PIXEL_RATE_CNTL, blk, 0), \
0087     SRII(PIXEL_RATE_CNTL, blk, 1),\
0088     SRII(PIXEL_RATE_CNTL, blk, 2),\
0089     SRII(PIXEL_RATE_CNTL, blk, 3), \
0090     SRII(PIXEL_RATE_CNTL, blk, 4), \
0091     SRII(PIXEL_RATE_CNTL, blk, 5)
0092 
0093 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \
0094     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
0095     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
0096     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
0097     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
0098     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
0099     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
0100 
0101 #define HWSEQ_PHYPLL_REG_LIST_201(blk) \
0102     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
0103     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
0104 
0105 #define HWSEQ_DCE11_REG_LIST_BASE() \
0106     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
0107     SR(DCFEV_CLOCK_CONTROL), \
0108     SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
0109     SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
0110     SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
0111     SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
0112     SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
0113     SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
0114     SRII(BLND_CONTROL, BLND, 0),\
0115     SRII(BLND_CONTROL, BLND, 1),\
0116     SR(BLNDV_CONTROL),\
0117     HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
0118 
0119 #if defined(CONFIG_DRM_AMD_DC_SI)
0120 #define HWSEQ_DCE6_REG_LIST() \
0121     HWSEQ_DCEF_REG_LIST_DCE8(), \
0122     HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
0123 #endif
0124 
0125 #define HWSEQ_DCE8_REG_LIST() \
0126     HWSEQ_DCEF_REG_LIST_DCE8(), \
0127     HWSEQ_BLND_REG_LIST(), \
0128     HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
0129 
0130 #define HWSEQ_DCE10_REG_LIST() \
0131     HWSEQ_DCEF_REG_LIST(), \
0132     HWSEQ_BLND_REG_LIST(), \
0133     HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
0134 
0135 #define HWSEQ_ST_REG_LIST() \
0136     HWSEQ_DCE11_REG_LIST_BASE(), \
0137     .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \
0138     .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \
0139     .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \
0140     .BLND_CONTROL[2] = mmBLNDV_CONTROL
0141 
0142 #define HWSEQ_CZ_REG_LIST() \
0143     HWSEQ_DCE11_REG_LIST_BASE(), \
0144     SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
0145     SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
0146     SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
0147     SRII(BLND_CONTROL, BLND, 2), \
0148     .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \
0149     .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \
0150     .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
0151     .BLND_CONTROL[3] = mmBLNDV_CONTROL
0152 
0153 #define HWSEQ_DCE120_REG_LIST() \
0154     HWSEQ_DCE10_REG_LIST(), \
0155     HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
0156     HWSEQ_PHYPLL_REG_LIST(CRTC), \
0157     SR(DCHUB_FB_LOCATION),\
0158     SR(DCHUB_AGP_BASE),\
0159     SR(DCHUB_AGP_BOT),\
0160     SR(DCHUB_AGP_TOP)
0161 
0162 #define HWSEQ_VG20_REG_LIST() \
0163     HWSEQ_DCE120_REG_LIST(),\
0164     MMHUB_SR(MC_VM_XGMI_LFB_CNTL)
0165 
0166 #define HWSEQ_DCE112_REG_LIST() \
0167     HWSEQ_DCE10_REG_LIST(), \
0168     HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
0169     HWSEQ_PHYPLL_REG_LIST(CRTC)
0170 
0171 #define HWSEQ_DCN_REG_LIST()\
0172     SR(REFCLK_CNTL), \
0173     SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
0174     SR(DIO_MEM_PWR_CTRL), \
0175     SR(DCCG_GATE_DISABLE_CNTL), \
0176     SR(DCCG_GATE_DISABLE_CNTL2), \
0177     SR(DCFCLK_CNTL),\
0178     SR(DCFCLK_CNTL), \
0179     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
0180 
0181 
0182 #define MMHUB_DCN_REG_LIST()\
0183     /* todo:  get these from GVM instead of reading registers ourselves */\
0184     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
0185     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
0186     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\
0187     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\
0188     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\
0189     MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\
0190     MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\
0191     MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\
0192     MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
0193     MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\
0194     MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
0195     MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
0196 
0197 
0198 #define HWSEQ_DCN1_REG_LIST()\
0199     HWSEQ_DCN_REG_LIST(), \
0200     MMHUB_DCN_REG_LIST(), \
0201     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
0202     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
0203     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
0204     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
0205     SR(DCHUBBUB_SDPIF_FB_BASE),\
0206     SR(DCHUBBUB_SDPIF_FB_OFFSET),\
0207     SR(DCHUBBUB_SDPIF_AGP_BASE),\
0208     SR(DCHUBBUB_SDPIF_AGP_BOT),\
0209     SR(DCHUBBUB_SDPIF_AGP_TOP),\
0210     SR(DOMAIN0_PG_CONFIG), \
0211     SR(DOMAIN1_PG_CONFIG), \
0212     SR(DOMAIN2_PG_CONFIG), \
0213     SR(DOMAIN3_PG_CONFIG), \
0214     SR(DOMAIN4_PG_CONFIG), \
0215     SR(DOMAIN5_PG_CONFIG), \
0216     SR(DOMAIN6_PG_CONFIG), \
0217     SR(DOMAIN7_PG_CONFIG), \
0218     SR(DOMAIN0_PG_STATUS), \
0219     SR(DOMAIN1_PG_STATUS), \
0220     SR(DOMAIN2_PG_STATUS), \
0221     SR(DOMAIN3_PG_STATUS), \
0222     SR(DOMAIN4_PG_STATUS), \
0223     SR(DOMAIN5_PG_STATUS), \
0224     SR(DOMAIN6_PG_STATUS), \
0225     SR(DOMAIN7_PG_STATUS), \
0226     SR(D1VGA_CONTROL), \
0227     SR(D2VGA_CONTROL), \
0228     SR(D3VGA_CONTROL), \
0229     SR(D4VGA_CONTROL), \
0230     SR(VGA_TEST_CONTROL), \
0231     SR(DC_IP_REQUEST_CNTL)
0232 
0233 #define HWSEQ_DCN2_REG_LIST()\
0234     HWSEQ_DCN_REG_LIST(), \
0235     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
0236     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
0237     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
0238     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
0239     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
0240     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
0241     SR(MICROSECOND_TIME_BASE_DIV), \
0242     SR(MILLISECOND_TIME_BASE_DIV), \
0243     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0244     SR(RBBMIF_TIMEOUT_DIS), \
0245     SR(RBBMIF_TIMEOUT_DIS_2), \
0246     SR(DCHUBBUB_CRC_CTRL), \
0247     SR(DPP_TOP0_DPP_CRC_CTRL), \
0248     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0249     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0250     SR(MPC_CRC_CTRL), \
0251     SR(MPC_CRC_RESULT_GB), \
0252     SR(MPC_CRC_RESULT_C), \
0253     SR(MPC_CRC_RESULT_AR), \
0254     SR(DOMAIN0_PG_CONFIG), \
0255     SR(DOMAIN1_PG_CONFIG), \
0256     SR(DOMAIN2_PG_CONFIG), \
0257     SR(DOMAIN3_PG_CONFIG), \
0258     SR(DOMAIN4_PG_CONFIG), \
0259     SR(DOMAIN5_PG_CONFIG), \
0260     SR(DOMAIN6_PG_CONFIG), \
0261     SR(DOMAIN7_PG_CONFIG), \
0262     SR(DOMAIN8_PG_CONFIG), \
0263     SR(DOMAIN9_PG_CONFIG), \
0264 /*  SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\
0265 /*  SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\
0266     SR(DOMAIN16_PG_CONFIG), \
0267     SR(DOMAIN17_PG_CONFIG), \
0268     SR(DOMAIN18_PG_CONFIG), \
0269     SR(DOMAIN19_PG_CONFIG), \
0270     SR(DOMAIN20_PG_CONFIG), \
0271     SR(DOMAIN21_PG_CONFIG), \
0272     SR(DOMAIN0_PG_STATUS), \
0273     SR(DOMAIN1_PG_STATUS), \
0274     SR(DOMAIN2_PG_STATUS), \
0275     SR(DOMAIN3_PG_STATUS), \
0276     SR(DOMAIN4_PG_STATUS), \
0277     SR(DOMAIN5_PG_STATUS), \
0278     SR(DOMAIN6_PG_STATUS), \
0279     SR(DOMAIN7_PG_STATUS), \
0280     SR(DOMAIN8_PG_STATUS), \
0281     SR(DOMAIN9_PG_STATUS), \
0282     SR(DOMAIN10_PG_STATUS), \
0283     SR(DOMAIN11_PG_STATUS), \
0284     SR(DOMAIN16_PG_STATUS), \
0285     SR(DOMAIN17_PG_STATUS), \
0286     SR(DOMAIN18_PG_STATUS), \
0287     SR(DOMAIN19_PG_STATUS), \
0288     SR(DOMAIN20_PG_STATUS), \
0289     SR(DOMAIN21_PG_STATUS), \
0290     SR(D1VGA_CONTROL), \
0291     SR(D2VGA_CONTROL), \
0292     SR(D3VGA_CONTROL), \
0293     SR(D4VGA_CONTROL), \
0294     SR(D5VGA_CONTROL), \
0295     SR(D6VGA_CONTROL), \
0296     SR(DC_IP_REQUEST_CNTL)
0297 
0298 #define HWSEQ_DCN21_REG_LIST()\
0299     HWSEQ_DCN_REG_LIST(), \
0300     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
0301     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
0302     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
0303     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
0304     MMHUB_DCN_REG_LIST(), \
0305     SR(MICROSECOND_TIME_BASE_DIV), \
0306     SR(MILLISECOND_TIME_BASE_DIV), \
0307     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0308     SR(RBBMIF_TIMEOUT_DIS), \
0309     SR(RBBMIF_TIMEOUT_DIS_2), \
0310     SR(DCHUBBUB_CRC_CTRL), \
0311     SR(DPP_TOP0_DPP_CRC_CTRL), \
0312     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0313     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0314     SR(MPC_CRC_CTRL), \
0315     SR(MPC_CRC_RESULT_GB), \
0316     SR(MPC_CRC_RESULT_C), \
0317     SR(MPC_CRC_RESULT_AR), \
0318     SR(DOMAIN0_PG_CONFIG), \
0319     SR(DOMAIN1_PG_CONFIG), \
0320     SR(DOMAIN2_PG_CONFIG), \
0321     SR(DOMAIN3_PG_CONFIG), \
0322     SR(DOMAIN4_PG_CONFIG), \
0323     SR(DOMAIN5_PG_CONFIG), \
0324     SR(DOMAIN6_PG_CONFIG), \
0325     SR(DOMAIN7_PG_CONFIG), \
0326     SR(DOMAIN16_PG_CONFIG), \
0327     SR(DOMAIN17_PG_CONFIG), \
0328     SR(DOMAIN18_PG_CONFIG), \
0329     SR(DOMAIN0_PG_STATUS), \
0330     SR(DOMAIN1_PG_STATUS), \
0331     SR(DOMAIN2_PG_STATUS), \
0332     SR(DOMAIN3_PG_STATUS), \
0333     SR(DOMAIN4_PG_STATUS), \
0334     SR(DOMAIN5_PG_STATUS), \
0335     SR(DOMAIN6_PG_STATUS), \
0336     SR(DOMAIN7_PG_STATUS), \
0337     SR(DOMAIN16_PG_STATUS), \
0338     SR(DOMAIN17_PG_STATUS), \
0339     SR(DOMAIN18_PG_STATUS), \
0340     SR(D1VGA_CONTROL), \
0341     SR(D2VGA_CONTROL), \
0342     SR(D3VGA_CONTROL), \
0343     SR(D4VGA_CONTROL), \
0344     SR(D5VGA_CONTROL), \
0345     SR(D6VGA_CONTROL), \
0346     SR(DC_IP_REQUEST_CNTL)
0347 
0348 #define HWSEQ_DCN201_REG_LIST()\
0349     HWSEQ_DCN_REG_LIST(), \
0350     HWSEQ_PIXEL_RATE_REG_LIST_201(OTG), \
0351     HWSEQ_PHYPLL_REG_LIST_201(OTG), \
0352     SR(MICROSECOND_TIME_BASE_DIV), \
0353     SR(MILLISECOND_TIME_BASE_DIV), \
0354     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0355     SR(RBBMIF_TIMEOUT_DIS), \
0356     SR(RBBMIF_TIMEOUT_DIS_2), \
0357     SR(DCHUBBUB_CRC_CTRL), \
0358     SR(DPP_TOP0_DPP_CRC_CTRL), \
0359     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0360     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0361     SR(MPC_CRC_CTRL), \
0362     SR(MPC_CRC_RESULT_GB), \
0363     SR(MPC_CRC_RESULT_C), \
0364     SR(MPC_CRC_RESULT_AR), \
0365     SR(AZALIA_AUDIO_DTO), \
0366     SR(AZALIA_CONTROLLER_CLOCK_GATING), \
0367     MMHUB_SR(MC_VM_FB_LOCATION_BASE), \
0368     MMHUB_SR(MC_VM_FB_LOCATION_TOP), \
0369     MMHUB_SR(MC_VM_FB_OFFSET)
0370 
0371 #define HWSEQ_DCN30_REG_LIST()\
0372     HWSEQ_DCN2_REG_LIST(),\
0373     HWSEQ_DCN_REG_LIST(), \
0374     HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \
0375     HWSEQ_PHYPLL_REG_LIST_3(OTG), \
0376     SR(MICROSECOND_TIME_BASE_DIV), \
0377     SR(MILLISECOND_TIME_BASE_DIV), \
0378     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0379     SR(RBBMIF_TIMEOUT_DIS), \
0380     SR(RBBMIF_TIMEOUT_DIS_2), \
0381     SR(DCHUBBUB_CRC_CTRL), \
0382     SR(DPP_TOP0_DPP_CRC_CTRL), \
0383     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0384     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0385     SR(MPC_CRC_CTRL), \
0386     SR(MPC_CRC_RESULT_GB), \
0387     SR(MPC_CRC_RESULT_C), \
0388     SR(MPC_CRC_RESULT_AR), \
0389     SR(AZALIA_AUDIO_DTO), \
0390     SR(AZALIA_CONTROLLER_CLOCK_GATING)
0391 
0392 #define HWSEQ_DCN301_REG_LIST()\
0393     SR(REFCLK_CNTL), \
0394     SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
0395     SR(DIO_MEM_PWR_CTRL), \
0396     SR(DCCG_GATE_DISABLE_CNTL), \
0397     SR(DCCG_GATE_DISABLE_CNTL2), \
0398     SR(DCFCLK_CNTL),\
0399     SR(DCFCLK_CNTL), \
0400     SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
0401     SRII(PIXEL_RATE_CNTL, OTG, 0), \
0402     SRII(PIXEL_RATE_CNTL, OTG, 1),\
0403     SRII(PIXEL_RATE_CNTL, OTG, 2),\
0404     SRII(PIXEL_RATE_CNTL, OTG, 3),\
0405     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
0406     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
0407     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
0408     SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
0409     SR(MICROSECOND_TIME_BASE_DIV), \
0410     SR(MILLISECOND_TIME_BASE_DIV), \
0411     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0412     SR(RBBMIF_TIMEOUT_DIS), \
0413     SR(RBBMIF_TIMEOUT_DIS_2), \
0414     SR(DCHUBBUB_CRC_CTRL), \
0415     SR(DPP_TOP0_DPP_CRC_CTRL), \
0416     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0417     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0418     SR(MPC_CRC_CTRL), \
0419     SR(MPC_CRC_RESULT_GB), \
0420     SR(MPC_CRC_RESULT_C), \
0421     SR(MPC_CRC_RESULT_AR), \
0422     SR(DOMAIN0_PG_CONFIG), \
0423     SR(DOMAIN1_PG_CONFIG), \
0424     SR(DOMAIN2_PG_CONFIG), \
0425     SR(DOMAIN3_PG_CONFIG), \
0426     SR(DOMAIN4_PG_CONFIG), \
0427     SR(DOMAIN5_PG_CONFIG), \
0428     SR(DOMAIN6_PG_CONFIG), \
0429     SR(DOMAIN7_PG_CONFIG), \
0430     SR(DOMAIN16_PG_CONFIG), \
0431     SR(DOMAIN17_PG_CONFIG), \
0432     SR(DOMAIN18_PG_CONFIG), \
0433     SR(DOMAIN0_PG_STATUS), \
0434     SR(DOMAIN1_PG_STATUS), \
0435     SR(DOMAIN2_PG_STATUS), \
0436     SR(DOMAIN3_PG_STATUS), \
0437     SR(DOMAIN4_PG_STATUS), \
0438     SR(DOMAIN5_PG_STATUS), \
0439     SR(DOMAIN6_PG_STATUS), \
0440     SR(DOMAIN7_PG_STATUS), \
0441     SR(DOMAIN16_PG_STATUS), \
0442     SR(DOMAIN17_PG_STATUS), \
0443     SR(DOMAIN18_PG_STATUS), \
0444     SR(D1VGA_CONTROL), \
0445     SR(D2VGA_CONTROL), \
0446     SR(D3VGA_CONTROL), \
0447     SR(D4VGA_CONTROL), \
0448     SR(D5VGA_CONTROL), \
0449     SR(D6VGA_CONTROL), \
0450     SR(DC_IP_REQUEST_CNTL), \
0451     SR(AZALIA_AUDIO_DTO), \
0452     SR(AZALIA_CONTROLLER_CLOCK_GATING)
0453 
0454 #define HWSEQ_DCN302_REG_LIST()\
0455     HWSEQ_DCN_REG_LIST(), \
0456     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
0457     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
0458     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
0459     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
0460     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
0461     SR(MICROSECOND_TIME_BASE_DIV), \
0462     SR(MILLISECOND_TIME_BASE_DIV), \
0463     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0464     SR(RBBMIF_TIMEOUT_DIS), \
0465     SR(RBBMIF_TIMEOUT_DIS_2), \
0466     SR(DCHUBBUB_CRC_CTRL), \
0467     SR(DPP_TOP0_DPP_CRC_CTRL), \
0468     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0469     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0470     SR(MPC_CRC_CTRL), \
0471     SR(MPC_CRC_RESULT_GB), \
0472     SR(MPC_CRC_RESULT_C), \
0473     SR(MPC_CRC_RESULT_AR), \
0474     SR(DOMAIN0_PG_CONFIG), \
0475     SR(DOMAIN1_PG_CONFIG), \
0476     SR(DOMAIN2_PG_CONFIG), \
0477     SR(DOMAIN3_PG_CONFIG), \
0478     SR(DOMAIN4_PG_CONFIG), \
0479     SR(DOMAIN5_PG_CONFIG), \
0480     SR(DOMAIN6_PG_CONFIG), \
0481     SR(DOMAIN7_PG_CONFIG), \
0482     SR(DOMAIN8_PG_CONFIG), \
0483     SR(DOMAIN9_PG_CONFIG), \
0484     SR(DOMAIN16_PG_CONFIG), \
0485     SR(DOMAIN17_PG_CONFIG), \
0486     SR(DOMAIN18_PG_CONFIG), \
0487     SR(DOMAIN19_PG_CONFIG), \
0488     SR(DOMAIN20_PG_CONFIG), \
0489     SR(DOMAIN0_PG_STATUS), \
0490     SR(DOMAIN1_PG_STATUS), \
0491     SR(DOMAIN2_PG_STATUS), \
0492     SR(DOMAIN3_PG_STATUS), \
0493     SR(DOMAIN4_PG_STATUS), \
0494     SR(DOMAIN5_PG_STATUS), \
0495     SR(DOMAIN6_PG_STATUS), \
0496     SR(DOMAIN7_PG_STATUS), \
0497     SR(DOMAIN8_PG_STATUS), \
0498     SR(DOMAIN9_PG_STATUS), \
0499     SR(DOMAIN16_PG_STATUS), \
0500     SR(DOMAIN17_PG_STATUS), \
0501     SR(DOMAIN18_PG_STATUS), \
0502     SR(DOMAIN19_PG_STATUS), \
0503     SR(DOMAIN20_PG_STATUS), \
0504     SR(D1VGA_CONTROL), \
0505     SR(D2VGA_CONTROL), \
0506     SR(D3VGA_CONTROL), \
0507     SR(D4VGA_CONTROL), \
0508     SR(D5VGA_CONTROL), \
0509     SR(D6VGA_CONTROL), \
0510     SR(DC_IP_REQUEST_CNTL), \
0511     SR(AZALIA_AUDIO_DTO), \
0512     SR(AZALIA_CONTROLLER_CLOCK_GATING)
0513 
0514 #define HWSEQ_DCN303_REG_LIST() \
0515     HWSEQ_DCN_REG_LIST(), \
0516     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
0517     HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
0518     SR(MICROSECOND_TIME_BASE_DIV), \
0519     SR(MILLISECOND_TIME_BASE_DIV), \
0520     SR(DISPCLK_FREQ_CHANGE_CNTL), \
0521     SR(RBBMIF_TIMEOUT_DIS), \
0522     SR(RBBMIF_TIMEOUT_DIS_2), \
0523     SR(DCHUBBUB_CRC_CTRL), \
0524     SR(DPP_TOP0_DPP_CRC_CTRL), \
0525     SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
0526     SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
0527     SR(MPC_CRC_CTRL), \
0528     SR(MPC_CRC_RESULT_GB), \
0529     SR(MPC_CRC_RESULT_C), \
0530     SR(MPC_CRC_RESULT_AR), \
0531     SR(D1VGA_CONTROL), \
0532     SR(D2VGA_CONTROL), \
0533     SR(D3VGA_CONTROL), \
0534     SR(D4VGA_CONTROL), \
0535     SR(D5VGA_CONTROL), \
0536     SR(D6VGA_CONTROL), \
0537     HWSEQ_PIXEL_RATE_REG_LIST_303(OTG), \
0538     HWSEQ_PHYPLL_REG_LIST_303(OTG), \
0539     SR(AZALIA_AUDIO_DTO), \
0540     SR(AZALIA_CONTROLLER_CLOCK_GATING), \
0541     SR(HPO_TOP_CLOCK_CONTROL)
0542 
0543 #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) \
0544     SRII(PIXEL_RATE_CNTL, blk, 0), \
0545     SRII(PIXEL_RATE_CNTL, blk, 1),\
0546     SRII(PIXEL_RATE_CNTL, blk, 2),\
0547     SRII(PIXEL_RATE_CNTL, blk, 3), \
0548     SRII(PIXEL_RATE_CNTL, blk, 4)
0549 
0550 #define HWSEQ_PHYPLL_REG_LIST_302(blk) \
0551     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
0552     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\
0553     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\
0554     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
0555     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4)
0556 
0557 #define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) \
0558     SRII(PIXEL_RATE_CNTL, blk, 0), \
0559     SRII(PIXEL_RATE_CNTL, blk, 1)
0560 
0561 #define HWSEQ_PHYPLL_REG_LIST_303(blk) \
0562     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
0563     SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1)
0564 
0565 struct dce_hwseq_registers {
0566     uint32_t DCFE_CLOCK_CONTROL[6];
0567     uint32_t DCFEV_CLOCK_CONTROL;
0568     uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
0569     uint32_t BLND_V_UPDATE_LOCK[6];
0570     uint32_t BLND_CONTROL[6];
0571     uint32_t BLNDV_CONTROL;
0572     uint32_t CRTC_H_BLANK_START_END[6];
0573     uint32_t PIXEL_RATE_CNTL[6];
0574     uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
0575     /*DCHUB*/
0576     uint32_t DCHUB_FB_LOCATION;
0577     uint32_t DCHUB_AGP_BASE;
0578     uint32_t DCHUB_AGP_BOT;
0579     uint32_t DCHUB_AGP_TOP;
0580 
0581     uint32_t REFCLK_CNTL;
0582 
0583     uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
0584     uint32_t DCHUBBUB_SDPIF_FB_BASE;
0585     uint32_t DCHUBBUB_SDPIF_FB_OFFSET;
0586     uint32_t DCHUBBUB_SDPIF_AGP_BASE;
0587     uint32_t DCHUBBUB_SDPIF_AGP_BOT;
0588     uint32_t DCHUBBUB_SDPIF_AGP_TOP;
0589     uint32_t DC_IP_REQUEST_CNTL;
0590     uint32_t DOMAIN0_PG_CONFIG;
0591     uint32_t DOMAIN1_PG_CONFIG;
0592     uint32_t DOMAIN2_PG_CONFIG;
0593     uint32_t DOMAIN3_PG_CONFIG;
0594     uint32_t DOMAIN4_PG_CONFIG;
0595     uint32_t DOMAIN5_PG_CONFIG;
0596     uint32_t DOMAIN6_PG_CONFIG;
0597     uint32_t DOMAIN7_PG_CONFIG;
0598     uint32_t DOMAIN8_PG_CONFIG;
0599     uint32_t DOMAIN9_PG_CONFIG;
0600     uint32_t DOMAIN10_PG_CONFIG;
0601     uint32_t DOMAIN11_PG_CONFIG;
0602     uint32_t DOMAIN16_PG_CONFIG;
0603     uint32_t DOMAIN17_PG_CONFIG;
0604     uint32_t DOMAIN18_PG_CONFIG;
0605     uint32_t DOMAIN19_PG_CONFIG;
0606     uint32_t DOMAIN20_PG_CONFIG;
0607     uint32_t DOMAIN21_PG_CONFIG;
0608     uint32_t DOMAIN0_PG_STATUS;
0609     uint32_t DOMAIN1_PG_STATUS;
0610     uint32_t DOMAIN2_PG_STATUS;
0611     uint32_t DOMAIN3_PG_STATUS;
0612     uint32_t DOMAIN4_PG_STATUS;
0613     uint32_t DOMAIN5_PG_STATUS;
0614     uint32_t DOMAIN6_PG_STATUS;
0615     uint32_t DOMAIN7_PG_STATUS;
0616     uint32_t DOMAIN8_PG_STATUS;
0617     uint32_t DOMAIN9_PG_STATUS;
0618     uint32_t DOMAIN10_PG_STATUS;
0619     uint32_t DOMAIN11_PG_STATUS;
0620     uint32_t DOMAIN16_PG_STATUS;
0621     uint32_t DOMAIN17_PG_STATUS;
0622     uint32_t DOMAIN18_PG_STATUS;
0623     uint32_t DOMAIN19_PG_STATUS;
0624     uint32_t DOMAIN20_PG_STATUS;
0625     uint32_t DOMAIN21_PG_STATUS;
0626     uint32_t DIO_MEM_PWR_CTRL;
0627     uint32_t DCCG_GATE_DISABLE_CNTL;
0628     uint32_t DCCG_GATE_DISABLE_CNTL2;
0629     uint32_t DCFCLK_CNTL;
0630     uint32_t MICROSECOND_TIME_BASE_DIV;
0631     uint32_t MILLISECOND_TIME_BASE_DIV;
0632     uint32_t DISPCLK_FREQ_CHANGE_CNTL;
0633     uint32_t RBBMIF_TIMEOUT_DIS;
0634     uint32_t RBBMIF_TIMEOUT_DIS_2;
0635     uint32_t DCHUBBUB_CRC_CTRL;
0636     uint32_t DPP_TOP0_DPP_CRC_CTRL;
0637     uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
0638     uint32_t DPP_TOP0_DPP_CRC_VAL_B_A;
0639     uint32_t MPC_CRC_CTRL;
0640     uint32_t MPC_CRC_RESULT_GB;
0641     uint32_t MPC_CRC_RESULT_C;
0642     uint32_t MPC_CRC_RESULT_AR;
0643     uint32_t D1VGA_CONTROL;
0644     uint32_t D2VGA_CONTROL;
0645     uint32_t D3VGA_CONTROL;
0646     uint32_t D4VGA_CONTROL;
0647     uint32_t D5VGA_CONTROL;
0648     uint32_t D6VGA_CONTROL;
0649     uint32_t VGA_TEST_CONTROL;
0650     /* MMHUB registers. read only. temporary hack */
0651     uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32;
0652     uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0653     uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32;
0654     uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32;
0655     uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32;
0656     uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32;
0657     uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32;
0658     uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32;
0659     uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;
0660     uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
0661     uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
0662     uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
0663     uint32_t MC_VM_XGMI_LFB_CNTL;
0664     uint32_t AZALIA_AUDIO_DTO;
0665     uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
0666     uint32_t HPO_TOP_CLOCK_CONTROL;
0667     uint32_t ODM_MEM_PWR_CTRL3;
0668     uint32_t DMU_MEM_PWR_CNTL;
0669     uint32_t MMHUBBUB_MEM_PWR_CNTL;
0670     uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
0671     uint32_t MC_VM_FB_LOCATION_BASE;
0672     uint32_t MC_VM_FB_LOCATION_TOP;
0673     uint32_t MC_VM_FB_OFFSET;
0674     uint32_t HPO_TOP_HW_CONTROL;
0675 };
0676  /* set field name */
0677 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
0678     .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
0679 
0680 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
0681     .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
0682 
0683 
0684 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
0685     HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
0686     SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
0687 
0688 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\
0689     HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
0690     HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
0691     HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
0692     HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\
0693     HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\
0694     HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\
0695     HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\
0696     HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
0697     HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
0698 
0699 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
0700     HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
0701     HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
0702 
0703 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
0704     HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
0705     HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
0706 
0707 #if defined(CONFIG_DRM_AMD_DC_SI)
0708 #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\
0709     .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
0710     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
0711 #endif
0712 
0713 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
0714     .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
0715     HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
0716     HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
0717     HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
0718     HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
0719     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
0720 
0721 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
0722     HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
0723     HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
0724     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
0725 
0726 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
0727     HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
0728     SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
0729     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
0730 
0731 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
0732     HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
0733     HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
0734 
0735 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
0736     SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
0737     SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
0738     SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
0739     SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
0740     SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
0741 
0742 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
0743     HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
0744     HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
0745     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
0746     HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
0747     HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)
0748 
0749 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
0750     HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
0751     HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\
0752     HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh)
0753 
0754 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
0755     HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
0756     HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
0757     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
0758     HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \
0759     HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
0760 
0761 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\
0762     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0763     HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \
0764     HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \
0765     HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \
0766     HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \
0767     HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \
0768     HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \
0769     /* todo:  get these from GVM instead of reading registers ourselves */\
0770     HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
0771     HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
0772     HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
0773     HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
0774     HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\
0775     HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\
0776     HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\
0777     HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\
0778     HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\
0779     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
0780     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
0781     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
0782     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
0783     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
0784     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
0785     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
0786     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
0787     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
0788     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
0789     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
0790     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
0791     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
0792     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
0793     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
0794     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
0795     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
0796     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
0797     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
0798     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
0799     HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
0800     HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
0801     HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
0802     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
0803     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
0804     HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
0805     HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\
0806     HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\
0807     HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
0808     HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
0809     HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)
0810 
0811 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
0812     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0813     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0814     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
0815     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
0816     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
0817     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
0818     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
0819     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
0820     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
0821     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
0822     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
0823     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
0824     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
0825     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
0826     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
0827     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
0828     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
0829     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
0830     HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
0831     HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
0832     HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
0833     HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
0834     HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \
0835     HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \
0836     HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \
0837     HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \
0838     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
0839     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
0840     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
0841     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
0842     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
0843     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
0844     HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
0845     HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
0846     HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
0847     HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
0848     HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \
0849     HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \
0850     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
0851     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
0852     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
0853     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
0854     HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
0855     HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
0856     HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
0857     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
0858     HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
0859     HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
0860     HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \
0861     HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \
0862     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
0863     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
0864     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
0865     HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
0866     HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
0867     HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
0868     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
0869 
0870 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
0871     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0872     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0873     HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
0874     HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
0875     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
0876     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
0877     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
0878     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
0879     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
0880     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
0881     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
0882     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
0883     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
0884     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
0885     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
0886     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
0887     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
0888     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
0889     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
0890     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
0891     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
0892     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
0893     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
0894     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
0895     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
0896     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
0897     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
0898     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
0899     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
0900     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
0901     HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
0902     HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
0903     HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
0904     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
0905     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
0906     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
0907     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
0908     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)
0909 
0910 #define HWSEQ_DCN201_MASK_SH_LIST(mask_sh)\
0911     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0912     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0913     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
0914 
0915 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\
0916     HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \
0917     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
0918     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
0919     HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
0920     HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
0921     HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
0922 
0923 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
0924     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0925     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0926     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
0927     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
0928     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
0929     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
0930     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
0931     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
0932     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
0933     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
0934     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
0935     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
0936     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
0937     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
0938     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
0939     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
0940     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
0941     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
0942     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
0943     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
0944     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
0945     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
0946     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
0947     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
0948     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
0949     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
0950     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
0951     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
0952     HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
0953     HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
0954     HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
0955     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
0956     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
0957     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
0958     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
0959     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
0960     HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_BLON, mask_sh),\
0961     HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON, mask_sh),\
0962     HWS_SF(, PANEL_PWRSEQ0_CNTL, PANEL_DIGON_OVRD, mask_sh),\
0963     HWS_SF(, PANEL_PWRSEQ0_STATE, PANEL_PWRSEQ_TARGET_STATE_R, mask_sh),\
0964     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
0965 
0966 #define HWSEQ_DCN302_MASK_SH_LIST(mask_sh)\
0967     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
0968     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
0969     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
0970     HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
0971     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
0972     HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
0973     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
0974     HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
0975     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
0976     HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
0977     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
0978     HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
0979     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
0980     HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
0981     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
0982     HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
0983     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
0984     HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
0985     HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
0986     HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
0987     HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
0988     HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
0989     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
0990     HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
0991     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
0992     HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
0993     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
0994     HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
0995     HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
0996     HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
0997     HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
0998     HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
0999     HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
1000     HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
1001     HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
1002     HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
1003     HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
1004     HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
1005     HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
1006     HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
1007     HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
1008     HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
1009     HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
1010     HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
1011     HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
1012     HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
1013     HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
1014     HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
1015     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh)
1016 
1017 #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) \
1018     HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
1019     HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
1020     HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
1021     HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_GATE_DIS, mask_sh)
1022 
1023 #define HWSEQ_REG_FIELD_LIST(type) \
1024     type DCFE_CLOCK_ENABLE; \
1025     type DCFEV_CLOCK_ENABLE; \
1026     type DC_MEM_GLOBAL_PWR_REQ_DIS; \
1027     type BLND_DCP_GRPH_V_UPDATE_LOCK; \
1028     type BLND_SCL_V_UPDATE_LOCK; \
1029     type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \
1030     type BLND_BLND_V_UPDATE_LOCK; \
1031     type BLND_V_UPDATE_LOCK_MODE; \
1032     type BLND_FEEDTHROUGH_EN; \
1033     type BLND_ALPHA_MODE; \
1034     type BLND_MODE; \
1035     type BLND_MULTIPLIED_MODE; \
1036     type DP_DTO0_ENABLE; \
1037     type PIXEL_RATE_SOURCE; \
1038     type PHYPLL_PIXEL_RATE_SOURCE; \
1039     type PIXEL_RATE_PLL_SOURCE; \
1040     /* todo:  get these from GVM instead of reading registers ourselves */\
1041     type PAGE_DIRECTORY_ENTRY_HI32;\
1042     type PAGE_DIRECTORY_ENTRY_LO32;\
1043     type LOGICAL_PAGE_NUMBER_HI4;\
1044     type LOGICAL_PAGE_NUMBER_LO32;\
1045     type PHYSICAL_PAGE_ADDR_HI4;\
1046     type PHYSICAL_PAGE_ADDR_LO32;\
1047     type PHYSICAL_PAGE_NUMBER_MSB;\
1048     type PHYSICAL_PAGE_NUMBER_LSB;\
1049     type LOGICAL_ADDR; \
1050     type PF_LFB_REGION;\
1051     type PF_MAX_REGION;\
1052     type ENABLE_L1_TLB;\
1053     type SYSTEM_ACCESS_MODE;
1054 
1055 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
1056     type HUBP_VTG_SEL; \
1057     type HUBP_CLOCK_ENABLE; \
1058     type DPP_CLOCK_ENABLE; \
1059     type SDPIF_FB_BASE;\
1060     type SDPIF_FB_OFFSET;\
1061     type SDPIF_AGP_BASE;\
1062     type SDPIF_AGP_BOT;\
1063     type SDPIF_AGP_TOP;\
1064     type FB_TOP;\
1065     type FB_BASE;\
1066     type FB_OFFSET;\
1067     type AGP_BASE;\
1068     type AGP_BOT;\
1069     type AGP_TOP;\
1070     type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
1071     type OPP_PIPE_CLOCK_EN;\
1072     type IP_REQUEST_EN; \
1073     type DOMAIN0_POWER_FORCEON; \
1074     type DOMAIN0_POWER_GATE; \
1075     type DOMAIN1_POWER_FORCEON; \
1076     type DOMAIN1_POWER_GATE; \
1077     type DOMAIN2_POWER_FORCEON; \
1078     type DOMAIN2_POWER_GATE; \
1079     type DOMAIN3_POWER_FORCEON; \
1080     type DOMAIN3_POWER_GATE; \
1081     type DOMAIN4_POWER_FORCEON; \
1082     type DOMAIN4_POWER_GATE; \
1083     type DOMAIN5_POWER_FORCEON; \
1084     type DOMAIN5_POWER_GATE; \
1085     type DOMAIN6_POWER_FORCEON; \
1086     type DOMAIN6_POWER_GATE; \
1087     type DOMAIN7_POWER_FORCEON; \
1088     type DOMAIN7_POWER_GATE; \
1089     type DOMAIN8_POWER_FORCEON; \
1090     type DOMAIN8_POWER_GATE; \
1091     type DOMAIN9_POWER_FORCEON; \
1092     type DOMAIN9_POWER_GATE; \
1093     type DOMAIN10_POWER_FORCEON; \
1094     type DOMAIN10_POWER_GATE; \
1095     type DOMAIN11_POWER_FORCEON; \
1096     type DOMAIN11_POWER_GATE; \
1097     type DOMAIN16_POWER_FORCEON; \
1098     type DOMAIN16_POWER_GATE; \
1099     type DOMAIN17_POWER_FORCEON; \
1100     type DOMAIN17_POWER_GATE; \
1101     type DOMAIN18_POWER_FORCEON; \
1102     type DOMAIN18_POWER_GATE; \
1103     type DOMAIN19_POWER_FORCEON; \
1104     type DOMAIN19_POWER_GATE; \
1105     type DOMAIN20_POWER_FORCEON; \
1106     type DOMAIN20_POWER_GATE; \
1107     type DOMAIN21_POWER_FORCEON; \
1108     type DOMAIN21_POWER_GATE; \
1109     type DOMAIN0_PGFSM_PWR_STATUS; \
1110     type DOMAIN1_PGFSM_PWR_STATUS; \
1111     type DOMAIN2_PGFSM_PWR_STATUS; \
1112     type DOMAIN3_PGFSM_PWR_STATUS; \
1113     type DOMAIN4_PGFSM_PWR_STATUS; \
1114     type DOMAIN5_PGFSM_PWR_STATUS; \
1115     type DOMAIN6_PGFSM_PWR_STATUS; \
1116     type DOMAIN7_PGFSM_PWR_STATUS; \
1117     type DOMAIN8_PGFSM_PWR_STATUS; \
1118     type DOMAIN9_PGFSM_PWR_STATUS; \
1119     type DOMAIN10_PGFSM_PWR_STATUS; \
1120     type DOMAIN11_PGFSM_PWR_STATUS; \
1121     type DOMAIN16_PGFSM_PWR_STATUS; \
1122     type DOMAIN17_PGFSM_PWR_STATUS; \
1123     type DOMAIN18_PGFSM_PWR_STATUS; \
1124     type DOMAIN19_PGFSM_PWR_STATUS; \
1125     type DOMAIN20_PGFSM_PWR_STATUS; \
1126     type DOMAIN21_PGFSM_PWR_STATUS; \
1127     type DCFCLK_GATE_DIS; \
1128     type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
1129     type VGA_TEST_ENABLE; \
1130     type VGA_TEST_RENDER_START; \
1131     type D1VGA_MODE_ENABLE; \
1132     type D2VGA_MODE_ENABLE; \
1133     type D3VGA_MODE_ENABLE; \
1134     type D4VGA_MODE_ENABLE; \
1135     type AZALIA_AUDIO_DTO_MODULE; \
1136     type ODM_MEM_UNASSIGNED_PWR_MODE; \
1137     type ODM_MEM_VBLANK_PWR_MODE; \
1138     type DMCU_ERAM_MEM_PWR_FORCE; \
1139     type VGA_MEM_PWR_FORCE;
1140 
1141 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \
1142     type HPO_HDMISTREAMCLK_GATE_DIS;
1143 
1144 #define HWSEQ_DCN301_REG_FIELD_LIST(type) \
1145     type PANEL_BLON;\
1146     type PANEL_DIGON;\
1147     type PANEL_DIGON_OVRD;\
1148     type PANEL_PWRSEQ_TARGET_STATE_R;
1149 
1150 #define HWSEQ_DCN31_REG_FIELD_LIST(type) \
1151     type DOMAIN_POWER_FORCEON;\
1152     type DOMAIN_POWER_GATE;\
1153     type DOMAIN_PGFSM_PWR_STATUS;\
1154     type HPO_HDMISTREAMCLK_G_GATE_DIS;\
1155     type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\
1156     type I2C_LIGHT_SLEEP_FORCE;\
1157     type HPO_IO_EN;
1158 
1159 struct dce_hwseq_shift {
1160     HWSEQ_REG_FIELD_LIST(uint8_t)
1161     HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
1162     HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
1163     HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
1164     HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
1165 };
1166 
1167 struct dce_hwseq_mask {
1168     HWSEQ_REG_FIELD_LIST(uint32_t)
1169     HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
1170     HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
1171     HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
1172     HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
1173 };
1174 
1175 
1176 enum blnd_mode {
1177     BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
1178     BLND_MODE_OTHER_PIPE, /* Data from other pipe only */
1179     BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
1180 };
1181 
1182 struct dce_hwseq;
1183 struct pipe_ctx;
1184 struct clock_source;
1185 
1186 void dce_enable_fe_clock(struct dce_hwseq *hwss,
1187         unsigned int inst, bool enable);
1188 
1189 void dce_pipe_control_lock(struct dc *dc,
1190         struct pipe_ctx *pipe,
1191         bool lock);
1192 
1193 void dce_set_blender_mode(struct dce_hwseq *hws,
1194     unsigned int blnd_inst, enum blnd_mode mode);
1195 
1196 #if defined(CONFIG_DRM_AMD_DC_SI)
1197 void dce60_pipe_control_lock(struct dc *dc,
1198         struct pipe_ctx *pipe,
1199         bool lock);
1200 #endif
1201 
1202 void dce_clock_gating_power_up(struct dce_hwseq *hws,
1203         bool enable);
1204 
1205 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
1206         struct clock_source *clk_src,
1207         unsigned int tg_inst);
1208 
1209 bool dce_use_lut(enum surface_pixel_format format);
1210 #endif   /*__DCE_HWSEQ_H__*/
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