dc/dce/dce_dmcu.h

0001 /*
0002  * Copyright 2012-16 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #ifndef _DCE_DMCU_H_
0028 #define _DCE_DMCU_H_
0029
0030 #include "dmcu.h"
0031
0032 #define DMCU_COMMON_REG_LIST_DCE_BASE() \
0033     SR(DMCU_CTRL), \
0034     SR(DMCU_STATUS), \
0035     SR(DMCU_RAM_ACCESS_CTRL), \
0036     SR(DMCU_IRAM_WR_CTRL), \
0037     SR(DMCU_IRAM_WR_DATA), \
0038     SR(MASTER_COMM_DATA_REG1), \
0039     SR(MASTER_COMM_DATA_REG2), \
0040     SR(MASTER_COMM_DATA_REG3), \
0041     SR(MASTER_COMM_CMD_REG), \
0042     SR(MASTER_COMM_CNTL_REG), \
0043     SR(SLAVE_COMM_DATA_REG1), \
0044     SR(SLAVE_COMM_DATA_REG2), \
0045     SR(SLAVE_COMM_DATA_REG3), \
0046     SR(SLAVE_COMM_CMD_REG), \
0047     SR(DMCU_IRAM_RD_CTRL), \
0048     SR(DMCU_IRAM_RD_DATA), \
0049     SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
0050     SR(SMU_INTERRUPT_CONTROL), \
0051     SR(DC_DMCU_SCRATCH)
0052
0053 #if defined(CONFIG_DRM_AMD_DC_SI)
0054 #define DMCU_DCE60_REG_LIST() \
0055     SR(DMCU_CTRL), \
0056     SR(DMCU_STATUS), \
0057     SR(DMCU_RAM_ACCESS_CTRL), \
0058     SR(DMCU_IRAM_WR_CTRL), \
0059     SR(DMCU_IRAM_WR_DATA), \
0060     SR(MASTER_COMM_DATA_REG1), \
0061     SR(MASTER_COMM_DATA_REG2), \
0062     SR(MASTER_COMM_DATA_REG3), \
0063     SR(MASTER_COMM_CMD_REG), \
0064     SR(MASTER_COMM_CNTL_REG), \
0065     SR(DMCU_IRAM_RD_CTRL), \
0066     SR(DMCU_IRAM_RD_DATA), \
0067     SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
0068     SR(DC_DMCU_SCRATCH)
0069 #endif
0070
0071 #define DMCU_DCE80_REG_LIST() \
0072     SR(DMCU_CTRL), \
0073     SR(DMCU_STATUS), \
0074     SR(DMCU_RAM_ACCESS_CTRL), \
0075     SR(DMCU_IRAM_WR_CTRL), \
0076     SR(DMCU_IRAM_WR_DATA), \
0077     SR(MASTER_COMM_DATA_REG1), \
0078     SR(MASTER_COMM_DATA_REG2), \
0079     SR(MASTER_COMM_DATA_REG3), \
0080     SR(MASTER_COMM_CMD_REG), \
0081     SR(MASTER_COMM_CNTL_REG), \
0082     SR(DMCU_IRAM_RD_CTRL), \
0083     SR(DMCU_IRAM_RD_DATA), \
0084     SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
0085     SR(SMU_INTERRUPT_CONTROL), \
0086     SR(DC_DMCU_SCRATCH)
0087
0088 #define DMCU_DCE110_COMMON_REG_LIST() \
0089     DMCU_COMMON_REG_LIST_DCE_BASE(), \
0090     SR(DCI_MEM_PWR_STATUS)
0091
0092 #define DMCU_DCN10_REG_LIST()\
0093     DMCU_COMMON_REG_LIST_DCE_BASE(), \
0094     SR(DMU_MEM_PWR_CNTL)
0095
0096 #define DMCU_DCN20_REG_LIST()\
0097     DMCU_DCN10_REG_LIST(), \
0098     SR(DMCUB_SCRATCH15)
0099
0100 #define DMCU_SF(reg_name, field_name, post_fix)\
0101     .field_name = reg_name ## __ ## field_name ## post_fix
0102
0103 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0104     DMCU_SF(DMCU_CTRL, \
0105             DMCU_ENABLE, mask_sh), \
0106     DMCU_SF(DMCU_STATUS, \
0107             UC_IN_STOP_MODE, mask_sh), \
0108     DMCU_SF(DMCU_STATUS, \
0109             UC_IN_RESET, mask_sh), \
0110     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0111             IRAM_HOST_ACCESS_EN, mask_sh), \
0112     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0113             IRAM_WR_ADDR_AUTO_INC, mask_sh), \
0114     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0115             IRAM_RD_ADDR_AUTO_INC, mask_sh), \
0116     DMCU_SF(MASTER_COMM_CMD_REG, \
0117             MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
0118     DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
0119     DMCU_SF(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, mask_sh), \
0120     DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
0121             STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
0122     DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
0123             STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
0124     DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
0125             STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
0126     DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
0127             STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
0128     DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
0129
0130 #if defined(CONFIG_DRM_AMD_DC_SI)
0131 #define DMCU_MASK_SH_LIST_DCE60(mask_sh) \
0132     DMCU_SF(DMCU_CTRL, \
0133             DMCU_ENABLE, mask_sh), \
0134     DMCU_SF(DMCU_STATUS, \
0135             UC_IN_STOP_MODE, mask_sh), \
0136     DMCU_SF(DMCU_STATUS, \
0137             UC_IN_RESET, mask_sh), \
0138     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0139             IRAM_HOST_ACCESS_EN, mask_sh), \
0140     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0141             IRAM_WR_ADDR_AUTO_INC, mask_sh), \
0142     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0143             IRAM_RD_ADDR_AUTO_INC, mask_sh), \
0144     DMCU_SF(MASTER_COMM_CMD_REG, \
0145             MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
0146     DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
0147 #endif
0148
0149 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
0150     DMCU_SF(DMCU_CTRL, \
0151             DMCU_ENABLE, mask_sh), \
0152     DMCU_SF(DMCU_STATUS, \
0153             UC_IN_STOP_MODE, mask_sh), \
0154     DMCU_SF(DMCU_STATUS, \
0155             UC_IN_RESET, mask_sh), \
0156     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0157             IRAM_HOST_ACCESS_EN, mask_sh), \
0158     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0159             IRAM_WR_ADDR_AUTO_INC, mask_sh), \
0160     DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
0161             IRAM_RD_ADDR_AUTO_INC, mask_sh), \
0162     DMCU_SF(MASTER_COMM_CMD_REG, \
0163             MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
0164     DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
0165     DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
0166
0167 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
0168     DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0169     DMCU_SF(DCI_MEM_PWR_STATUS, \
0170         DMCU_IRAM_MEM_PWR_STATE, mask_sh)
0171
0172 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
0173     DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0174     DMCU_SF(DMU_MEM_PWR_CNTL, \
0175             DMCU_IRAM_MEM_PWR_STATE, mask_sh)
0176
0177 #define DMCU_REG_FIELD_LIST(type) \
0178     type DMCU_IRAM_MEM_PWR_STATE; \
0179     type IRAM_HOST_ACCESS_EN; \
0180     type IRAM_WR_ADDR_AUTO_INC; \
0181     type IRAM_RD_ADDR_AUTO_INC; \
0182     type DMCU_ENABLE; \
0183     type UC_IN_STOP_MODE; \
0184     type UC_IN_RESET; \
0185     type MASTER_COMM_CMD_REG_BYTE0; \
0186     type MASTER_COMM_INTERRUPT; \
0187     type SLAVE_COMM_INTERRUPT; \
0188     type DPHY_RX_FAST_TRAINING_CAPABLE; \
0189     type DPHY_LOAD_BS_COUNT; \
0190     type STATIC_SCREEN1_INT_TO_UC_EN; \
0191     type STATIC_SCREEN2_INT_TO_UC_EN; \
0192     type STATIC_SCREEN3_INT_TO_UC_EN; \
0193     type STATIC_SCREEN4_INT_TO_UC_EN; \
0194     type DP_SEC_GSP0_LINE_NUM; \
0195     type DP_SEC_GSP0_PRIORITY; \
0196     type DC_SMU_INT_ENABLE
0197
0198 struct dce_dmcu_shift {
0199     DMCU_REG_FIELD_LIST(uint8_t);
0200 };
0201
0202 struct dce_dmcu_mask {
0203     DMCU_REG_FIELD_LIST(uint32_t);
0204 };
0205
0206 struct dce_dmcu_registers {
0207     uint32_t DMCU_CTRL;
0208     uint32_t DMCU_STATUS;
0209     uint32_t DMCU_RAM_ACCESS_CTRL;
0210     uint32_t DCI_MEM_PWR_STATUS;
0211     uint32_t DMU_MEM_PWR_CNTL;
0212     uint32_t DMCU_IRAM_WR_CTRL;
0213     uint32_t DMCU_IRAM_WR_DATA;
0214
0215     uint32_t MASTER_COMM_DATA_REG1;
0216     uint32_t MASTER_COMM_DATA_REG2;
0217     uint32_t MASTER_COMM_DATA_REG3;
0218     uint32_t MASTER_COMM_CMD_REG;
0219     uint32_t MASTER_COMM_CNTL_REG;
0220     uint32_t SLAVE_COMM_DATA_REG1;
0221     uint32_t SLAVE_COMM_DATA_REG2;
0222     uint32_t SLAVE_COMM_DATA_REG3;
0223     uint32_t SLAVE_COMM_CMD_REG;
0224     uint32_t SLAVE_COMM_CNTL_REG;
0225     uint32_t DMCU_IRAM_RD_CTRL;
0226     uint32_t DMCU_IRAM_RD_DATA;
0227     uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
0228     uint32_t SMU_INTERRUPT_CONTROL;
0229     uint32_t DC_DMCU_SCRATCH;
0230     uint32_t DMCUB_SCRATCH15;
0231 };
0232
0233 struct dce_dmcu {
0234     struct dmcu base;
0235     const struct dce_dmcu_registers *regs;
0236     const struct dce_dmcu_shift *dmcu_shift;
0237     const struct dce_dmcu_mask *dmcu_mask;
0238 };
0239
0240 /*******************************************************************
0241  *   MASTER_COMM_DATA_REG1   Bit position    Data
0242  *                           7:0                hyst_frames[7:0]
0243  *                           14:8           hyst_lines[6:0]
0244  *                           15             RFB_UPDATE_AUTO_EN
0245  *                           18:16          phy_num[2:0]
0246  *                           21:19          dcp_sel[2:0]
0247  *                           22             phy_type
0248  *                           23             frame_cap_ind
0249  *                           26:24          aux_chan[2:0]
0250  *                           30:27          aux_repeat[3:0]
0251  *                           31:31          reserved[31:31]
0252  ******************************************************************/
0253 union dce_dmcu_psr_config_data_reg1 {
0254     struct {
0255         unsigned int timehyst_frames:8;                  /*[7:0]*/
0256         unsigned int hyst_lines:7;                       /*[14:8]*/
0257         unsigned int rfb_update_auto_en:1;               /*[15:15]*/
0258         unsigned int dp_port_num:3;                      /*[18:16]*/
0259         unsigned int dcp_sel:3;                          /*[21:19]*/
0260         unsigned int phy_type:1;                         /*[22:22]*/
0261         unsigned int frame_cap_ind:1;                    /*[23:23]*/
0262         unsigned int aux_chan:3;                         /*[26:24]*/
0263         unsigned int aux_repeat:4;                       /*[30:27]*/
0264         unsigned int allow_smu_optimizations:1;         /*[31:31]*/
0265     } bits;
0266     unsigned int u32All;
0267 };
0268
0269 /*******************************************************************
0270  *   MASTER_COMM_DATA_REG2
0271  *******************************************************************/
0272 union dce_dmcu_psr_config_data_reg2 {
0273     struct {
0274         unsigned int dig_fe:3;                  /*[2:0]*/
0275         unsigned int dig_be:3;                  /*[5:3]*/
0276         unsigned int skip_wait_for_pll_lock:1;  /*[6:6]*/
0277         unsigned int reserved:9;                /*[15:7]*/
0278         unsigned int frame_delay:8;             /*[23:16]*/
0279         unsigned int smu_phy_id:4;              /*[27:24]*/
0280         unsigned int num_of_controllers:4;      /*[31:28]*/
0281     } bits;
0282     unsigned int u32All;
0283 };
0284
0285 /*******************************************************************
0286  *   MASTER_COMM_DATA_REG3
0287  *******************************************************************/
0288 union dce_dmcu_psr_config_data_reg3 {
0289     struct {
0290         unsigned int psr_level:16;      /*[15:0]*/
0291         unsigned int link_rate:4;       /*[19:16]*/
0292         unsigned int reserved:12;        /*[31:20]*/
0293     } bits;
0294     unsigned int u32All;
0295 };
0296
0297 union dce_dmcu_psr_config_data_wait_loop_reg1 {
0298     struct {
0299         unsigned int wait_loop:16; /* [15:0] */
0300         unsigned int reserved:16; /* [31:16] */
0301     } bits;
0302     unsigned int u32;
0303 };
0304
0305 struct dmcu *dce_dmcu_create(
0306     struct dc_context *ctx,
0307     const struct dce_dmcu_registers *regs,
0308     const struct dce_dmcu_shift *dmcu_shift,
0309     const struct dce_dmcu_mask *dmcu_mask);
0310
0311 struct dmcu *dcn10_dmcu_create(
0312     struct dc_context *ctx,
0313     const struct dce_dmcu_registers *regs,
0314     const struct dce_dmcu_shift *dmcu_shift,
0315     const struct dce_dmcu_mask *dmcu_mask);
0316
0317 struct dmcu *dcn20_dmcu_create(
0318     struct dc_context *ctx,
0319     const struct dce_dmcu_registers *regs,
0320     const struct dce_dmcu_shift *dmcu_shift,
0321     const struct dce_dmcu_mask *dmcu_mask);
0322
0323 struct dmcu *dcn21_dmcu_create(
0324     struct dc_context *ctx,
0325     const struct dce_dmcu_registers *regs,
0326     const struct dce_dmcu_shift *dmcu_shift,
0327     const struct dce_dmcu_mask *dmcu_mask);
0328
0329 void dce_dmcu_destroy(struct dmcu **dmcu);
0330
0331 #endif /* _DCE_ABM_H_ */