dc/dce/dce_dmcu.c

0001 /*
0002  * Copyright 2012-16 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #include "core_types.h"
0027 #include "link_encoder.h"
0028 #include "dce_dmcu.h"
0029 #include "dm_services.h"
0030 #include "reg_helper.h"
0031 #include "fixed31_32.h"
0032 #include "dc.h"
0033
0034 #define TO_DCE_DMCU(dmcu)\
0035     container_of(dmcu, struct dce_dmcu, base)
0036
0037 #define REG(reg) \
0038     (dmcu_dce->regs->reg)
0039
0040 #undef FN
0041 #define FN(reg_name, field_name) \
0042     dmcu_dce->dmcu_shift->field_name, dmcu_dce->dmcu_mask->field_name
0043
0044 #define CTX \
0045     dmcu_dce->base.ctx
0046
0047 /* PSR related commands */
0048 #define PSR_ENABLE 0x20
0049 #define PSR_EXIT 0x21
0050 #define PSR_SET 0x23
0051 #define PSR_SET_WAITLOOP 0x31
0052 #define MCP_INIT_DMCU 0x88
0053 #define MCP_INIT_IRAM 0x89
0054 #define MCP_SYNC_PHY_LOCK 0x90
0055 #define MCP_SYNC_PHY_UNLOCK 0x91
0056 #define MCP_BL_SET_PWM_FRAC 0x6A  /* Enable or disable Fractional PWM */
0057 #define CRC_WIN_NOTIFY 0x92
0058 #define CRC_STOP_UPDATE 0x93
0059 #define MCP_SEND_EDID_CEA 0xA0
0060 #define EDID_CEA_CMD_ACK 1
0061 #define EDID_CEA_CMD_NACK 2
0062 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
0063
0064 // PSP FW version
0065 #define mmMP0_SMN_C2PMSG_58             0x1607A
0066
0067 //Register access policy version
0068 #define mmMP0_SMN_C2PMSG_91             0x1609B
0069
0070 static const uint32_t abm_gain_stepsize = 0x0060;
0071
0072 static bool dce_dmcu_init(struct dmcu *dmcu)
0073 {
0074     // Do nothing
0075     return true;
0076 }
0077
0078 static bool dce_dmcu_load_iram(struct dmcu *dmcu,
0079         unsigned int start_offset,
0080         const char *src,
0081         unsigned int bytes)
0082 {
0083     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0084     unsigned int count = 0;
0085
0086     /* Enable write access to IRAM */
0087     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0088             IRAM_HOST_ACCESS_EN, 1,
0089             IRAM_WR_ADDR_AUTO_INC, 1);
0090
0091     REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
0092
0093     REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
0094
0095     for (count = 0; count < bytes; count++)
0096         REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
0097
0098     /* Disable write access to IRAM to allow dynamic sleep state */
0099     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0100             IRAM_HOST_ACCESS_EN, 0,
0101             IRAM_WR_ADDR_AUTO_INC, 0);
0102
0103     return true;
0104 }
0105
0106 static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)
0107 {
0108     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0109
0110     uint32_t psr_state_offset = 0xf0;
0111
0112     /* Enable write access to IRAM */
0113     REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
0114
0115     REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
0116
0117     /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
0118     REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
0119
0120     /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
0121     *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
0122
0123     /* Disable write access to IRAM after finished using IRAM
0124      * in order to allow dynamic sleep state
0125      */
0126     REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
0127 }
0128
0129 static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
0130 {
0131     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0132     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0133     unsigned int dmcu_wait_reg_ready_interval = 100;
0134
0135     unsigned int retryCount;
0136     enum dc_psr_state state = PSR_STATE0;
0137
0138     /* waitDMCUReadyForCmd */
0139     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0140                 dmcu_wait_reg_ready_interval,
0141                 dmcu_max_retry_on_wait_reg_ready);
0142
0143     /* setDMCUParam_Cmd */
0144     if (enable)
0145         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0146                 PSR_ENABLE);
0147     else
0148         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0149                 PSR_EXIT);
0150
0151     /* notifyDMCUMsg */
0152     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0153     if (wait == true) {
0154         for (retryCount = 0; retryCount <= 100; retryCount++) {
0155             dce_get_dmcu_psr_state(dmcu, &state);
0156             if (enable) {
0157                 if (state != PSR_STATE0)
0158                     break;
0159             } else {
0160                 if (state == PSR_STATE0)
0161                     break;
0162             }
0163             udelay(10);
0164         }
0165     }
0166 }
0167
0168 static bool dce_dmcu_setup_psr(struct dmcu *dmcu,
0169         struct dc_link *link,
0170         struct psr_context *psr_context)
0171 {
0172     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0173
0174     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0175     unsigned int dmcu_wait_reg_ready_interval = 100;
0176
0177     union dce_dmcu_psr_config_data_reg1 masterCmdData1;
0178     union dce_dmcu_psr_config_data_reg2 masterCmdData2;
0179     union dce_dmcu_psr_config_data_reg3 masterCmdData3;
0180
0181     link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
0182             psr_context->psrExitLinkTrainingRequired);
0183
0184     /* Enable static screen interrupts for PSR supported display */
0185     /* Disable the interrupt coming from other displays. */
0186     REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
0187             STATIC_SCREEN1_INT_TO_UC_EN, 0,
0188             STATIC_SCREEN2_INT_TO_UC_EN, 0,
0189             STATIC_SCREEN3_INT_TO_UC_EN, 0,
0190             STATIC_SCREEN4_INT_TO_UC_EN, 0);
0191
0192     switch (psr_context->controllerId) {
0193     /* Driver uses case 1 for unconfigured */
0194     case 1:
0195         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0196                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
0197         break;
0198     case 2:
0199         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0200                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
0201         break;
0202     case 3:
0203         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0204                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
0205         break;
0206     case 4:
0207         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0208                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
0209         break;
0210     case 5:
0211         /* CZ/NL only has 4 CRTC!!
0212          * really valid.
0213          * There is no interrupt enable mask for these instances.
0214          */
0215         break;
0216     case 6:
0217         /* CZ/NL only has 4 CRTC!!
0218          * These are here because they are defined in HW regspec,
0219          * but not really valid. There is no interrupt enable mask
0220          * for these instances.
0221          */
0222         break;
0223     default:
0224         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0225                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
0226         break;
0227     }
0228
0229     link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
0230             psr_context->sdpTransmitLineNumDeadline);
0231
0232     /* waitDMCUReadyForCmd */
0233     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0234                     dmcu_wait_reg_ready_interval,
0235                     dmcu_max_retry_on_wait_reg_ready);
0236
0237     /* setDMCUParam_PSRHostConfigData */
0238     masterCmdData1.u32All = 0;
0239     masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
0240     masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
0241     masterCmdData1.bits.rfb_update_auto_en =
0242             psr_context->rfb_update_auto_en;
0243     masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
0244     masterCmdData1.bits.dcp_sel = psr_context->controllerId;
0245     masterCmdData1.bits.phy_type  = psr_context->phyType;
0246     masterCmdData1.bits.frame_cap_ind =
0247             psr_context->psrFrameCaptureIndicationReq;
0248     masterCmdData1.bits.aux_chan = psr_context->channel;
0249     masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
0250     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
0251                     masterCmdData1.u32All);
0252
0253     masterCmdData2.u32All = 0;
0254     masterCmdData2.bits.dig_fe = psr_context->engineId;
0255     masterCmdData2.bits.dig_be = psr_context->transmitterId;
0256     masterCmdData2.bits.skip_wait_for_pll_lock =
0257             psr_context->skipPsrWaitForPllLock;
0258     masterCmdData2.bits.frame_delay = psr_context->frame_delay;
0259     masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
0260     masterCmdData2.bits.num_of_controllers =
0261             psr_context->numberOfControllers;
0262     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
0263             masterCmdData2.u32All);
0264
0265     masterCmdData3.u32All = 0;
0266     masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
0267     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
0268             masterCmdData3.u32All);
0269
0270     /* setDMCUParam_Cmd */
0271     REG_UPDATE(MASTER_COMM_CMD_REG,
0272             MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
0273
0274     /* notifyDMCUMsg */
0275     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0276
0277     return true;
0278 }
0279
0280 static bool dce_is_dmcu_initialized(struct dmcu *dmcu)
0281 {
0282     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0283     unsigned int dmcu_uc_reset;
0284
0285     /* microcontroller is not running */
0286     REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);
0287
0288     /* DMCU is not running */
0289     if (dmcu_uc_reset)
0290         return false;
0291
0292     return true;
0293 }
0294
0295 static void dce_psr_wait_loop(
0296     struct dmcu *dmcu,
0297     unsigned int wait_loop_number)
0298 {
0299     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0300     union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
0301
0302     if (dmcu->cached_wait_loop_number == wait_loop_number)
0303         return;
0304
0305     /* DMCU is not running */
0306     if (!dce_is_dmcu_initialized(dmcu))
0307         return;
0308
0309     /* waitDMCUReadyForCmd */
0310     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0311
0312     masterCmdData1.u32 = 0;
0313     masterCmdData1.bits.wait_loop = wait_loop_number;
0314     dmcu->cached_wait_loop_number = wait_loop_number;
0315     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
0316
0317     /* setDMCUParam_Cmd */
0318     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
0319
0320     /* notifyDMCUMsg */
0321     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0322 }
0323
0324 static void dce_get_psr_wait_loop(
0325         struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
0326 {
0327     *psr_wait_loop_number = dmcu->cached_wait_loop_number;
0328     return;
0329 }
0330
0331 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
0332 {
0333     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0334     uint32_t dmcu_version_offset = 0xf1;
0335
0336     /* Enable write access to IRAM */
0337     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0338             IRAM_HOST_ACCESS_EN, 1,
0339             IRAM_RD_ADDR_AUTO_INC, 1);
0340
0341     REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
0342
0343     /* Write address to IRAM_RD_ADDR and read from DATA register */
0344     REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
0345     dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
0346     dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
0347     dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
0348     dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
0349                         REG_READ(DMCU_IRAM_RD_DATA));
0350
0351     /* Disable write access to IRAM to allow dynamic sleep state */
0352     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0353             IRAM_HOST_ACCESS_EN, 0,
0354             IRAM_RD_ADDR_AUTO_INC, 0);
0355 }
0356
0357 static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,
0358         uint32_t fractional_pwm)
0359 {
0360     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0361
0362     /* Wait until microcontroller is ready to process interrupt */
0363     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0364
0365     /* Set PWM fractional enable/disable */
0366     REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
0367
0368     /* Set command to enable or disable fractional PWM microcontroller */
0369     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0370             MCP_BL_SET_PWM_FRAC);
0371
0372     /* Notify microcontroller of new command */
0373     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0374
0375     /* Ensure command has been executed before continuing */
0376     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0377 }
0378
0379 static bool dcn10_dmcu_init(struct dmcu *dmcu)
0380 {
0381     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0382     const struct dc_config *config = &dmcu->ctx->dc->config;
0383     bool status = false;
0384     struct dc_context *ctx = dmcu->ctx;
0385     unsigned int i;
0386     //  5 4 3 2 1 0
0387     //  F E D C B A - bit 0 is A, bit 5 is F
0388     unsigned int tx_interrupt_mask = 0;
0389
0390     PERF_TRACE();
0391     /*  Definition of DC_DMCU_SCRATCH
0392      *  0 : firmare not loaded
0393      *  1 : PSP load DMCU FW but not initialized
0394      *  2 : Firmware already initialized
0395      */
0396     dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
0397
0398     for (i = 0; i < ctx->dc->link_count; i++) {
0399         if (ctx->dc->links[i]->link_enc->features.flags.bits.DP_IS_USB_C) {
0400             if (ctx->dc->links[i]->link_enc->transmitter >= TRANSMITTER_UNIPHY_A &&
0401                     ctx->dc->links[i]->link_enc->transmitter <= TRANSMITTER_UNIPHY_F) {
0402                 tx_interrupt_mask |= 1 << ctx->dc->links[i]->link_enc->transmitter;
0403             }
0404         }
0405     }
0406
0407     switch (dmcu->dmcu_state) {
0408     case DMCU_UNLOADED:
0409         status = false;
0410         break;
0411     case DMCU_LOADED_UNINITIALIZED:
0412         /* Wait until microcontroller is ready to process interrupt */
0413         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0414
0415         /* Set initialized ramping boundary value */
0416         REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
0417
0418         /* Set backlight ramping stepsize */
0419         REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
0420
0421         REG_WRITE(MASTER_COMM_DATA_REG3, tx_interrupt_mask);
0422
0423         /* Set command to initialize microcontroller */
0424         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0425             MCP_INIT_DMCU);
0426
0427         /* Notify microcontroller of new command */
0428         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0429
0430         /* Ensure command has been executed before continuing */
0431         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0432
0433         // Check state is initialized
0434         dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
0435
0436         // If microcontroller is not in running state, fail
0437         if (dmcu->dmcu_state == DMCU_RUNNING) {
0438             /* Retrieve and cache the DMCU firmware version. */
0439             dcn10_get_dmcu_version(dmcu);
0440
0441             /* Initialize DMCU to use fractional PWM or not */
0442             dcn10_dmcu_enable_fractional_pwm(dmcu,
0443                 (config->disable_fractional_pwm == false) ? 1 : 0);
0444             status = true;
0445         } else {
0446             status = false;
0447         }
0448
0449         break;
0450     case DMCU_RUNNING:
0451         status = true;
0452         break;
0453     default:
0454         status = false;
0455         break;
0456     }
0457
0458     PERF_TRACE();
0459     return status;
0460 }
0461
0462 static bool dcn21_dmcu_init(struct dmcu *dmcu)
0463 {
0464     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0465     uint32_t dmcub_psp_version = REG_READ(DMCUB_SCRATCH15);
0466
0467     if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {
0468         return false;
0469     }
0470
0471     return dcn10_dmcu_init(dmcu);
0472 }
0473
0474 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
0475         unsigned int start_offset,
0476         const char *src,
0477         unsigned int bytes)
0478 {
0479     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0480     unsigned int count = 0;
0481
0482     /* If microcontroller is not running, do nothing */
0483     if (dmcu->dmcu_state != DMCU_RUNNING)
0484         return false;
0485
0486     /* Enable write access to IRAM */
0487     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0488             IRAM_HOST_ACCESS_EN, 1,
0489             IRAM_WR_ADDR_AUTO_INC, 1);
0490
0491     REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
0492
0493     REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
0494
0495     for (count = 0; count < bytes; count++)
0496         REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
0497
0498     /* Disable write access to IRAM to allow dynamic sleep state */
0499     REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
0500             IRAM_HOST_ACCESS_EN, 0,
0501             IRAM_WR_ADDR_AUTO_INC, 0);
0502
0503     /* Wait until microcontroller is ready to process interrupt */
0504     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0505
0506     /* Set command to signal IRAM is loaded and to initialize IRAM */
0507     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0508             MCP_INIT_IRAM);
0509
0510     /* Notify microcontroller of new command */
0511     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0512
0513     /* Ensure command has been executed before continuing */
0514     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
0515
0516     return true;
0517 }
0518
0519 static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)
0520 {
0521     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0522
0523     uint32_t psr_state_offset = 0xf0;
0524
0525     /* If microcontroller is not running, do nothing */
0526     if (dmcu->dmcu_state != DMCU_RUNNING)
0527         return;
0528
0529     /* Enable write access to IRAM */
0530     REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
0531
0532     REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
0533
0534     /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
0535     REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
0536
0537     /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
0538     *state = (enum dc_psr_state)REG_READ(DMCU_IRAM_RD_DATA);
0539
0540     /* Disable write access to IRAM after finished using IRAM
0541      * in order to allow dynamic sleep state
0542      */
0543     REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
0544 }
0545
0546 static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)
0547 {
0548     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0549     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0550     unsigned int dmcu_wait_reg_ready_interval = 100;
0551
0552     unsigned int retryCount;
0553     enum dc_psr_state state = PSR_STATE0;
0554
0555     /* If microcontroller is not running, do nothing */
0556     if (dmcu->dmcu_state != DMCU_RUNNING)
0557         return;
0558
0559     /* waitDMCUReadyForCmd */
0560     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0561                 dmcu_wait_reg_ready_interval,
0562                 dmcu_max_retry_on_wait_reg_ready);
0563
0564     /* setDMCUParam_Cmd */
0565     if (enable)
0566         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0567                 PSR_ENABLE);
0568     else
0569         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0570                 PSR_EXIT);
0571
0572     /* notifyDMCUMsg */
0573     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0574
0575     /* Below loops 1000 x 500us = 500 ms.
0576      *  Exit PSR may need to wait 1-2 frames to power up. Timeout after at
0577      *  least a few frames. Should never hit the max retry assert below.
0578      */
0579     if (wait == true) {
0580         for (retryCount = 0; retryCount <= 1000; retryCount++) {
0581             dcn10_get_dmcu_psr_state(dmcu, &state);
0582             if (enable) {
0583                 if (state != PSR_STATE0)
0584                     break;
0585             } else {
0586                 if (state == PSR_STATE0)
0587                     break;
0588             }
0589             udelay(500);
0590         }
0591
0592         /* assert if max retry hit */
0593         if (retryCount >= 1000)
0594             ASSERT(0);
0595     }
0596 }
0597
0598 static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,
0599         struct dc_link *link,
0600         struct psr_context *psr_context)
0601 {
0602     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0603
0604     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0605     unsigned int dmcu_wait_reg_ready_interval = 100;
0606
0607     union dce_dmcu_psr_config_data_reg1 masterCmdData1;
0608     union dce_dmcu_psr_config_data_reg2 masterCmdData2;
0609     union dce_dmcu_psr_config_data_reg3 masterCmdData3;
0610
0611     /* If microcontroller is not running, do nothing */
0612     if (dmcu->dmcu_state != DMCU_RUNNING)
0613         return false;
0614
0615     link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc,
0616             psr_context->psrExitLinkTrainingRequired);
0617
0618     /* Enable static screen interrupts for PSR supported display */
0619     /* Disable the interrupt coming from other displays. */
0620     REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK,
0621             STATIC_SCREEN1_INT_TO_UC_EN, 0,
0622             STATIC_SCREEN2_INT_TO_UC_EN, 0,
0623             STATIC_SCREEN3_INT_TO_UC_EN, 0,
0624             STATIC_SCREEN4_INT_TO_UC_EN, 0);
0625
0626     switch (psr_context->controllerId) {
0627     /* Driver uses case 1 for unconfigured */
0628     case 1:
0629         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0630                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
0631         break;
0632     case 2:
0633         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0634                 STATIC_SCREEN2_INT_TO_UC_EN, 1);
0635         break;
0636     case 3:
0637         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0638                 STATIC_SCREEN3_INT_TO_UC_EN, 1);
0639         break;
0640     case 4:
0641         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0642                 STATIC_SCREEN4_INT_TO_UC_EN, 1);
0643         break;
0644     case 5:
0645         /* CZ/NL only has 4 CRTC!!
0646          * really valid.
0647          * There is no interrupt enable mask for these instances.
0648          */
0649         break;
0650     case 6:
0651         /* CZ/NL only has 4 CRTC!!
0652          * These are here because they are defined in HW regspec,
0653          * but not really valid. There is no interrupt enable mask
0654          * for these instances.
0655          */
0656         break;
0657     default:
0658         REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK,
0659                 STATIC_SCREEN1_INT_TO_UC_EN, 1);
0660         break;
0661     }
0662
0663     link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,
0664             psr_context->sdpTransmitLineNumDeadline);
0665
0666     if (psr_context->allow_smu_optimizations)
0667         REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);
0668
0669     /* waitDMCUReadyForCmd */
0670     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0671             dmcu_wait_reg_ready_interval,
0672             dmcu_max_retry_on_wait_reg_ready);
0673
0674     /* setDMCUParam_PSRHostConfigData */
0675     masterCmdData1.u32All = 0;
0676     masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;
0677     masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;
0678     masterCmdData1.bits.rfb_update_auto_en =
0679             psr_context->rfb_update_auto_en;
0680     masterCmdData1.bits.dp_port_num = psr_context->transmitterId;
0681     masterCmdData1.bits.dcp_sel = psr_context->controllerId;
0682     masterCmdData1.bits.phy_type  = psr_context->phyType;
0683     masterCmdData1.bits.frame_cap_ind =
0684             psr_context->psrFrameCaptureIndicationReq;
0685     masterCmdData1.bits.aux_chan = psr_context->channel;
0686     masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;
0687     masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;
0688     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
0689                     masterCmdData1.u32All);
0690
0691     masterCmdData2.u32All = 0;
0692     masterCmdData2.bits.dig_fe = psr_context->engineId;
0693     masterCmdData2.bits.dig_be = psr_context->transmitterId;
0694     masterCmdData2.bits.skip_wait_for_pll_lock =
0695             psr_context->skipPsrWaitForPllLock;
0696     masterCmdData2.bits.frame_delay = psr_context->frame_delay;
0697     masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;
0698     masterCmdData2.bits.num_of_controllers =
0699             psr_context->numberOfControllers;
0700     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
0701             masterCmdData2.u32All);
0702
0703     masterCmdData3.u32All = 0;
0704     masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;
0705     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
0706             masterCmdData3.u32All);
0707
0708
0709     /* setDMCUParam_Cmd */
0710     REG_UPDATE(MASTER_COMM_CMD_REG,
0711             MASTER_COMM_CMD_REG_BYTE0, PSR_SET);
0712
0713     /* notifyDMCUMsg */
0714     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0715
0716     /* waitDMCUReadyForCmd */
0717     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0718
0719     return true;
0720 }
0721
0722 static void dcn10_psr_wait_loop(
0723     struct dmcu *dmcu,
0724     unsigned int wait_loop_number)
0725 {
0726     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0727     union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
0728
0729     /* If microcontroller is not running, do nothing */
0730     if (dmcu->dmcu_state != DMCU_RUNNING)
0731         return;
0732
0733     if (wait_loop_number != 0) {
0734     /* waitDMCUReadyForCmd */
0735     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0736
0737     masterCmdData1.u32 = 0;
0738     masterCmdData1.bits.wait_loop = wait_loop_number;
0739     dmcu->cached_wait_loop_number = wait_loop_number;
0740     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);
0741
0742     /* setDMCUParam_Cmd */
0743     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
0744
0745     /* notifyDMCUMsg */
0746     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0747     }
0748 }
0749
0750 static void dcn10_get_psr_wait_loop(
0751         struct dmcu *dmcu, unsigned int *psr_wait_loop_number)
0752 {
0753     *psr_wait_loop_number = dmcu->cached_wait_loop_number;
0754     return;
0755 }
0756
0757 static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
0758 {
0759     /* microcontroller is not running */
0760     if (dmcu->dmcu_state != DMCU_RUNNING)
0761         return false;
0762     return true;
0763 }
0764
0765
0766
0767 static bool dcn20_lock_phy(struct dmcu *dmcu)
0768 {
0769     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0770
0771     /* If microcontroller is not running, do nothing */
0772     if (dmcu->dmcu_state != DMCU_RUNNING)
0773         return false;
0774
0775     /* waitDMCUReadyForCmd */
0776     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0777
0778     /* setDMCUParam_Cmd */
0779     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
0780
0781     /* notifyDMCUMsg */
0782     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0783
0784     /* waitDMCUReadyForCmd */
0785     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0786
0787     return true;
0788 }
0789
0790 static bool dcn20_unlock_phy(struct dmcu *dmcu)
0791 {
0792     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0793
0794     /* If microcontroller is not running, do nothing */
0795     if (dmcu->dmcu_state != DMCU_RUNNING)
0796         return false;
0797
0798     /* waitDMCUReadyForCmd */
0799     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0800
0801     /* setDMCUParam_Cmd */
0802     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
0803
0804     /* notifyDMCUMsg */
0805     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0806
0807     /* waitDMCUReadyForCmd */
0808     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0809
0810     return true;
0811 }
0812
0813 static bool dcn10_send_edid_cea(struct dmcu *dmcu,
0814         int offset,
0815         int total_length,
0816         uint8_t *data,
0817         int length)
0818 {
0819     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0820     uint32_t header, data1, data2;
0821
0822     /* If microcontroller is not running, do nothing */
0823     if (dmcu->dmcu_state != DMCU_RUNNING)
0824         return false;
0825
0826     if (length > 8 || length <= 0)
0827         return false;
0828
0829     header = ((uint32_t)offset & 0xFFFF) << 16 | (total_length & 0xFFFF);
0830     data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) |
0831         (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]);
0832     data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) |
0833         (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]);
0834
0835     /* waitDMCUReadyForCmd */
0836     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0837
0838     /* setDMCUParam_Cmd */
0839     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SEND_EDID_CEA);
0840
0841     REG_WRITE(MASTER_COMM_DATA_REG1, header);
0842     REG_WRITE(MASTER_COMM_DATA_REG2, data1);
0843     REG_WRITE(MASTER_COMM_DATA_REG3, data2);
0844
0845     /* notifyDMCUMsg */
0846     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0847
0848     /* waitDMCUReadyForCmd */
0849     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
0850
0851     return true;
0852 }
0853
0854 static bool dcn10_get_scp_results(struct dmcu *dmcu,
0855         uint32_t *cmd,
0856         uint32_t *data1,
0857         uint32_t *data2,
0858         uint32_t *data3)
0859 {
0860     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0861
0862     /* If microcontroller is not running, do nothing */
0863     if (dmcu->dmcu_state != DMCU_RUNNING)
0864         return false;
0865
0866     *cmd = REG_READ(SLAVE_COMM_CMD_REG);
0867     *data1 =  REG_READ(SLAVE_COMM_DATA_REG1);
0868     *data2 =  REG_READ(SLAVE_COMM_DATA_REG2);
0869     *data3 =  REG_READ(SLAVE_COMM_DATA_REG3);
0870
0871     /* clear SCP interrupt */
0872     REG_UPDATE(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, 0);
0873
0874     return true;
0875 }
0876
0877 static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu,
0878         int *version,
0879         int *min_frame_rate,
0880         int *max_frame_rate)
0881 {
0882     uint32_t data[4];
0883     int cmd, ack, len;
0884
0885     if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3]))
0886         return false;
0887
0888     cmd = data[0] & 0x3FF;
0889     len = (data[0] >> 10) & 0x3F;
0890     ack = data[1];
0891
0892     if (cmd != MCP_SEND_EDID_CEA || ack != EDID_CEA_CMD_ACK || len != 12)
0893         return false;
0894
0895     if ((data[2] & 0xFF)) {
0896         *version = (data[2] >> 8) & 0xFF;
0897         *min_frame_rate = (data[3] >> 16) & 0xFFFF;
0898         *max_frame_rate = data[3] & 0xFFFF;
0899         return true;
0900     }
0901
0902     return false;
0903 }
0904
0905 static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)
0906 {
0907     uint32_t data[4];
0908     int cmd, ack;
0909
0910     if (!dcn10_get_scp_results(dmcu,
0911                 &data[0], &data[1], &data[2], &data[3]))
0912         return false;
0913
0914     cmd = data[0] & 0x3FF;
0915     ack = data[1];
0916
0917     if (cmd != MCP_SEND_EDID_CEA)
0918         return false;
0919
0920     if (ack == EDID_CEA_CMD_ACK)
0921         return true;
0922
0923     *offset = data[2]; /* nack */
0924     return false;
0925 }
0926
0927
0928 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
0929 static void dcn10_forward_crc_window(struct dmcu *dmcu,
0930                     struct crc_region *crc_win,
0931                     struct otg_phy_mux *mux_mapping)
0932 {
0933     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0934     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0935     unsigned int dmcu_wait_reg_ready_interval = 100;
0936     unsigned int crc_start = 0, crc_end = 0, otg_phy_mux = 0;
0937
0938     /* If microcontroller is not running, do nothing */
0939     if (dmcu->dmcu_state != DMCU_RUNNING)
0940         return;
0941
0942     if (!crc_win)
0943         return;
0944
0945     /* waitDMCUReadyForCmd */
0946     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0947                 dmcu_wait_reg_ready_interval,
0948                 dmcu_max_retry_on_wait_reg_ready);
0949
0950     /* build up nitification data */
0951     crc_start = (((unsigned int) crc_win->x_start) << 16) | crc_win->y_start;
0952     crc_end = (((unsigned int) crc_win->x_end) << 16) | crc_win->y_end;
0953     otg_phy_mux =
0954         (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num;
0955
0956     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
0957                     crc_start);
0958
0959     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),
0960             crc_end);
0961
0962     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),
0963             otg_phy_mux);
0964
0965     /* setDMCUParam_Cmd */
0966     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0967                 CRC_WIN_NOTIFY);
0968
0969     /* notifyDMCUMsg */
0970     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
0971 }
0972
0973 static void dcn10_stop_crc_win_update(struct dmcu *dmcu,
0974                     struct otg_phy_mux *mux_mapping)
0975 {
0976     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
0977     unsigned int dmcu_max_retry_on_wait_reg_ready = 801;
0978     unsigned int dmcu_wait_reg_ready_interval = 100;
0979     unsigned int otg_phy_mux = 0;
0980
0981     /* If microcontroller is not running, do nothing */
0982     if (dmcu->dmcu_state != DMCU_RUNNING)
0983         return;
0984
0985     /* waitDMCUReadyForCmd */
0986     REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
0987                 dmcu_wait_reg_ready_interval,
0988                 dmcu_max_retry_on_wait_reg_ready);
0989
0990     /* build up nitification data */
0991     otg_phy_mux =
0992         (((unsigned int) mux_mapping->otg_output_num) << 16) | mux_mapping->phy_output_num;
0993
0994     dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),
0995                     otg_phy_mux);
0996
0997     /* setDMCUParam_Cmd */
0998     REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
0999                 CRC_STOP_UPDATE);
1000
1001     /* notifyDMCUMsg */
1002     REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
1003 }
1004 #endif
1005
1006 static const struct dmcu_funcs dce_funcs = {
1007     .dmcu_init = dce_dmcu_init,
1008     .load_iram = dce_dmcu_load_iram,
1009     .set_psr_enable = dce_dmcu_set_psr_enable,
1010     .setup_psr = dce_dmcu_setup_psr,
1011     .get_psr_state = dce_get_dmcu_psr_state,
1012     .set_psr_wait_loop = dce_psr_wait_loop,
1013     .get_psr_wait_loop = dce_get_psr_wait_loop,
1014     .is_dmcu_initialized = dce_is_dmcu_initialized
1015 };
1016
1017 static const struct dmcu_funcs dcn10_funcs = {
1018     .dmcu_init = dcn10_dmcu_init,
1019     .load_iram = dcn10_dmcu_load_iram,
1020     .set_psr_enable = dcn10_dmcu_set_psr_enable,
1021     .setup_psr = dcn10_dmcu_setup_psr,
1022     .get_psr_state = dcn10_get_dmcu_psr_state,
1023     .set_psr_wait_loop = dcn10_psr_wait_loop,
1024     .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1025     .send_edid_cea = dcn10_send_edid_cea,
1026     .recv_amd_vsdb = dcn10_recv_amd_vsdb,
1027     .recv_edid_cea_ack = dcn10_recv_edid_cea_ack,
1028 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1029     .forward_crc_window = dcn10_forward_crc_window,
1030     .stop_crc_win_update = dcn10_stop_crc_win_update,
1031 #endif
1032     .is_dmcu_initialized = dcn10_is_dmcu_initialized
1033 };
1034
1035 static const struct dmcu_funcs dcn20_funcs = {
1036     .dmcu_init = dcn10_dmcu_init,
1037     .load_iram = dcn10_dmcu_load_iram,
1038     .set_psr_enable = dcn10_dmcu_set_psr_enable,
1039     .setup_psr = dcn10_dmcu_setup_psr,
1040     .get_psr_state = dcn10_get_dmcu_psr_state,
1041     .set_psr_wait_loop = dcn10_psr_wait_loop,
1042     .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1043     .is_dmcu_initialized = dcn10_is_dmcu_initialized,
1044     .lock_phy = dcn20_lock_phy,
1045     .unlock_phy = dcn20_unlock_phy
1046 };
1047
1048 static const struct dmcu_funcs dcn21_funcs = {
1049     .dmcu_init = dcn21_dmcu_init,
1050     .load_iram = dcn10_dmcu_load_iram,
1051     .set_psr_enable = dcn10_dmcu_set_psr_enable,
1052     .setup_psr = dcn10_dmcu_setup_psr,
1053     .get_psr_state = dcn10_get_dmcu_psr_state,
1054     .set_psr_wait_loop = dcn10_psr_wait_loop,
1055     .get_psr_wait_loop = dcn10_get_psr_wait_loop,
1056     .is_dmcu_initialized = dcn10_is_dmcu_initialized,
1057     .lock_phy = dcn20_lock_phy,
1058     .unlock_phy = dcn20_unlock_phy
1059 };
1060
1061 static void dce_dmcu_construct(
1062     struct dce_dmcu *dmcu_dce,
1063     struct dc_context *ctx,
1064     const struct dce_dmcu_registers *regs,
1065     const struct dce_dmcu_shift *dmcu_shift,
1066     const struct dce_dmcu_mask *dmcu_mask)
1067 {
1068     struct dmcu *base = &dmcu_dce->base;
1069
1070     base->ctx = ctx;
1071     base->funcs = &dce_funcs;
1072     base->cached_wait_loop_number = 0;
1073
1074     dmcu_dce->regs = regs;
1075     dmcu_dce->dmcu_shift = dmcu_shift;
1076     dmcu_dce->dmcu_mask = dmcu_mask;
1077 }
1078
1079 static void dcn21_dmcu_construct(
1080         struct dce_dmcu *dmcu_dce,
1081         struct dc_context *ctx,
1082         const struct dce_dmcu_registers *regs,
1083         const struct dce_dmcu_shift *dmcu_shift,
1084         const struct dce_dmcu_mask *dmcu_mask)
1085 {
1086     uint32_t psp_version = 0;
1087
1088     dce_dmcu_construct(dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1089
1090     if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
1091         psp_version = dm_read_reg(ctx, mmMP0_SMN_C2PMSG_58);
1092         dmcu_dce->base.auto_load_dmcu = ((psp_version & 0x00FF00FF) > 0x00110029);
1093         dmcu_dce->base.psp_version = psp_version;
1094     }
1095 }
1096
1097 struct dmcu *dce_dmcu_create(
1098     struct dc_context *ctx,
1099     const struct dce_dmcu_registers *regs,
1100     const struct dce_dmcu_shift *dmcu_shift,
1101     const struct dce_dmcu_mask *dmcu_mask)
1102 {
1103     struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
1104
1105     if (dmcu_dce == NULL) {
1106         BREAK_TO_DEBUGGER();
1107         return NULL;
1108     }
1109
1110     dce_dmcu_construct(
1111         dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1112
1113     dmcu_dce->base.funcs = &dce_funcs;
1114
1115     return &dmcu_dce->base;
1116 }
1117
1118 struct dmcu *dcn10_dmcu_create(
1119     struct dc_context *ctx,
1120     const struct dce_dmcu_registers *regs,
1121     const struct dce_dmcu_shift *dmcu_shift,
1122     const struct dce_dmcu_mask *dmcu_mask)
1123 {
1124     struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1125
1126     if (dmcu_dce == NULL) {
1127         BREAK_TO_DEBUGGER();
1128         return NULL;
1129     }
1130
1131     dce_dmcu_construct(
1132         dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1133
1134     dmcu_dce->base.funcs = &dcn10_funcs;
1135
1136     return &dmcu_dce->base;
1137 }
1138
1139 struct dmcu *dcn20_dmcu_create(
1140     struct dc_context *ctx,
1141     const struct dce_dmcu_registers *regs,
1142     const struct dce_dmcu_shift *dmcu_shift,
1143     const struct dce_dmcu_mask *dmcu_mask)
1144 {
1145     struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1146
1147     if (dmcu_dce == NULL) {
1148         BREAK_TO_DEBUGGER();
1149         return NULL;
1150     }
1151
1152     dce_dmcu_construct(
1153         dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1154
1155     dmcu_dce->base.funcs = &dcn20_funcs;
1156
1157     return &dmcu_dce->base;
1158 }
1159
1160 struct dmcu *dcn21_dmcu_create(
1161     struct dc_context *ctx,
1162     const struct dce_dmcu_registers *regs,
1163     const struct dce_dmcu_shift *dmcu_shift,
1164     const struct dce_dmcu_mask *dmcu_mask)
1165 {
1166     struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC);
1167
1168     if (dmcu_dce == NULL) {
1169         BREAK_TO_DEBUGGER();
1170         return NULL;
1171     }
1172
1173     dcn21_dmcu_construct(
1174         dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
1175
1176     dmcu_dce->base.funcs = &dcn21_funcs;
1177
1178     return &dmcu_dce->base;
1179 }
1180
1181 void dce_dmcu_destroy(struct dmcu **dmcu)
1182 {
1183     struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);
1184
1185     kfree(dmcu_dce);
1186     *dmcu = NULL;
1187 }