dc/dce/dce_clock_source.h

0001 /* Copyright 2012-15 Advanced Micro Devices, Inc.
0002  *
0003  * Permission is hereby granted, free of charge, to any person obtaining a
0004  * copy of this software and associated documentation files (the "Software"),
0005  * to deal in the Software without restriction, including without limitation
0006  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0007  * and/or sell copies of the Software, and to permit persons to whom the
0008  * Software is furnished to do so, subject to the following conditions:
0009  *
0010  * The above copyright notice and this permission notice shall be included in
0011  * all copies or substantial portions of the Software.
0012  *
0013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0014  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0015  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0016  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0017  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0019  * OTHER DEALINGS IN THE SOFTWARE.
0020  *
0021  * Authors: AMD
0022  *
0023  */
0024
0025 #ifndef __DC_CLOCK_SOURCE_DCE_H__
0026 #define __DC_CLOCK_SOURCE_DCE_H__
0027
0028 #include "../inc/clock_source.h"
0029
0030 #define TO_DCE110_CLK_SRC(clk_src)\
0031     container_of(clk_src, struct dce110_clk_src, base)
0032
0033 #define CS_COMMON_REG_LIST_DCE_100_110(id) \
0034         SRI(RESYNC_CNTL, PIXCLK, id), \
0035         SRI(PLL_CNTL, BPHYC_PLL, id)
0036
0037 #define CS_COMMON_REG_LIST_DCE_80(id) \
0038         SRI(RESYNC_CNTL, PIXCLK, id), \
0039         SRI(PLL_CNTL, DCCG_PLL, id)
0040
0041 #define CS_COMMON_REG_LIST_DCE_112(id) \
0042         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
0043
0044
0045 #define CS_SF(reg_name, field_name, post_fix)\
0046     .field_name = reg_name ## __ ## field_name ## post_fix
0047
0048 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
0049     CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\
0050     CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\
0051     CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\
0052     CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh)
0053
0054 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\
0055     CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
0056     CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
0057
0058 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \
0059         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0060         SRII(PHASE, DP_DTO, 0),\
0061         SRII(PHASE, DP_DTO, 1),\
0062         SRII(PHASE, DP_DTO, 2),\
0063         SRII(PHASE, DP_DTO, 3),\
0064         SRII(PHASE, DP_DTO, 4),\
0065         SRII(PHASE, DP_DTO, 5),\
0066         SRII(MODULO, DP_DTO, 0),\
0067         SRII(MODULO, DP_DTO, 1),\
0068         SRII(MODULO, DP_DTO, 2),\
0069         SRII(MODULO, DP_DTO, 3),\
0070         SRII(MODULO, DP_DTO, 4),\
0071         SRII(MODULO, DP_DTO, 5),\
0072         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0073         SRII(PIXEL_RATE_CNTL, OTG, 1),\
0074         SRII(PIXEL_RATE_CNTL, OTG, 2),\
0075         SRII(PIXEL_RATE_CNTL, OTG, 3),\
0076         SRII(PIXEL_RATE_CNTL, OTG, 4),\
0077         SRII(PIXEL_RATE_CNTL, OTG, 5)
0078
0079 #define CS_COMMON_REG_LIST_DCN201(index, pllid) \
0080         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0081         SRII(PHASE, DP_DTO, 0),\
0082         SRII(PHASE, DP_DTO, 1),\
0083         SRII(MODULO, DP_DTO, 0),\
0084         SRII(MODULO, DP_DTO, 1),\
0085         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0086         SRII(PIXEL_RATE_CNTL, OTG, 1)
0087
0088 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
0089         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0090         SRII(PHASE, DP_DTO, 0),\
0091         SRII(PHASE, DP_DTO, 1),\
0092         SRII(PHASE, DP_DTO, 2),\
0093         SRII(PHASE, DP_DTO, 3),\
0094         SRII(MODULO, DP_DTO, 0),\
0095         SRII(MODULO, DP_DTO, 1),\
0096         SRII(MODULO, DP_DTO, 2),\
0097         SRII(MODULO, DP_DTO, 3),\
0098         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0099         SRII(PIXEL_RATE_CNTL, OTG, 1),\
0100         SRII(PIXEL_RATE_CNTL, OTG, 2),\
0101         SRII(PIXEL_RATE_CNTL, OTG, 3)
0102
0103 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \
0104         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0105         SRII(PHASE, DP_DTO, 0),\
0106         SRII(PHASE, DP_DTO, 1),\
0107         SRII(PHASE, DP_DTO, 2),\
0108         SRII(PHASE, DP_DTO, 3),\
0109         SRII(MODULO, DP_DTO, 0),\
0110         SRII(MODULO, DP_DTO, 1),\
0111         SRII(MODULO, DP_DTO, 2),\
0112         SRII(MODULO, DP_DTO, 3),\
0113         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0114         SRII(PIXEL_RATE_CNTL, OTG, 1),\
0115         SRII(PIXEL_RATE_CNTL, OTG, 2),\
0116         SRII(PIXEL_RATE_CNTL, OTG, 3)
0117
0118 #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \
0119         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0120         SRII(PHASE, DP_DTO, 0),\
0121         SRII(PHASE, DP_DTO, 1),\
0122         SRII(PHASE, DP_DTO, 2),\
0123         SRII(PHASE, DP_DTO, 3),\
0124         SRII(MODULO, DP_DTO, 0),\
0125         SRII(MODULO, DP_DTO, 1),\
0126         SRII(MODULO, DP_DTO, 2),\
0127         SRII(MODULO, DP_DTO, 3),\
0128         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0129         SRII(PIXEL_RATE_CNTL, OTG, 1),\
0130         SRII(PIXEL_RATE_CNTL, OTG, 2),\
0131         SRII(PIXEL_RATE_CNTL, OTG, 3)
0132
0133 #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \
0134         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0135         SRII(PHASE, DP_DTO, 0),\
0136         SRII(PHASE, DP_DTO, 1),\
0137         SRII(PHASE, DP_DTO, 2),\
0138         SRII(PHASE, DP_DTO, 3),\
0139         SRII(PHASE, DP_DTO, 4),\
0140         SRII(MODULO, DP_DTO, 0),\
0141         SRII(MODULO, DP_DTO, 1),\
0142         SRII(MODULO, DP_DTO, 2),\
0143         SRII(MODULO, DP_DTO, 3),\
0144         SRII(MODULO, DP_DTO, 4),\
0145         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0146         SRII(PIXEL_RATE_CNTL, OTG, 1),\
0147         SRII(PIXEL_RATE_CNTL, OTG, 2),\
0148         SRII(PIXEL_RATE_CNTL, OTG, 3),\
0149         SRII(PIXEL_RATE_CNTL, OTG, 4)
0150
0151 #define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \
0152         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0153         SRII(PHASE, DP_DTO, 0),\
0154         SRII(PHASE, DP_DTO, 1),\
0155         SRII(MODULO, DP_DTO, 0),\
0156         SRII(MODULO, DP_DTO, 1),\
0157         SRII(PIXEL_RATE_CNTL, OTG, 0),\
0158         SRII(PIXEL_RATE_CNTL, OTG, 1)
0159
0160 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
0161     CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
0162     CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
0163     CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
0164     CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
0165
0166 #define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\
0167     CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
0168     CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh),
0169
0170 #define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\
0171     CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\
0172     CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh)
0173
0174 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
0175         SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
0176         SRII(PHASE, DP_DTO, 0),\
0177         SRII(PHASE, DP_DTO, 1),\
0178         SRII(PHASE, DP_DTO, 2),\
0179         SRII(PHASE, DP_DTO, 3),\
0180         SRII(MODULO, DP_DTO, 0),\
0181         SRII(MODULO, DP_DTO, 1),\
0182         SRII(MODULO, DP_DTO, 2),\
0183         SRII(MODULO, DP_DTO, 3),\
0184         SRII(PIXEL_RATE_CNTL, OTG, 0), \
0185         SRII(PIXEL_RATE_CNTL, OTG, 1), \
0186         SRII(PIXEL_RATE_CNTL, OTG, 2), \
0187         SRII(PIXEL_RATE_CNTL, OTG, 3)
0188
0189 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
0190     CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
0191     CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\
0192     CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
0193     CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
0194
0195
0196 #define CS_REG_FIELD_LIST(type) \
0197     type PLL_REF_DIV_SRC; \
0198     type DCCG_DEEP_COLOR_CNTL1; \
0199     type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \
0200     type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \
0201     type PLL_POST_DIV_PIXCLK; \
0202     type PLL_REF_DIV; \
0203     type DP_DTO0_PHASE; \
0204     type DP_DTO0_MODULO; \
0205     type DP_DTO0_ENABLE;
0206
0207 #if defined(CONFIG_DRM_AMD_DC_DCN)
0208 #define CS_REG_FIELD_LIST_DCN32(type) \
0209     type PIPE0_DTO_SRC_SEL;
0210 #endif
0211
0212 struct dce110_clk_src_shift {
0213     CS_REG_FIELD_LIST(uint8_t)
0214 #if defined(CONFIG_DRM_AMD_DC_DCN)
0215     CS_REG_FIELD_LIST_DCN32(uint8_t)
0216 #endif
0217 };
0218
0219 struct dce110_clk_src_mask{
0220     CS_REG_FIELD_LIST(uint32_t)
0221 #if defined(CONFIG_DRM_AMD_DC_DCN)
0222     CS_REG_FIELD_LIST_DCN32(uint32_t)
0223 #endif
0224 };
0225
0226 struct dce110_clk_src_regs {
0227     uint32_t RESYNC_CNTL;
0228     uint32_t PIXCLK_RESYNC_CNTL;
0229     uint32_t PLL_CNTL;
0230
0231     /* below are for DTO.
0232      * todo: should probably use different struct to not waste space
0233      */
0234     uint32_t PHASE[MAX_PIPES];
0235     uint32_t MODULO[MAX_PIPES];
0236     uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
0237 };
0238
0239 struct dce110_clk_src {
0240     struct clock_source base;
0241     const struct dce110_clk_src_regs *regs;
0242     const struct dce110_clk_src_mask *cs_mask;
0243     const struct dce110_clk_src_shift *cs_shift;
0244     struct dc_bios *bios;
0245
0246     struct spread_spectrum_data *dp_ss_params;
0247     uint32_t dp_ss_params_cnt;
0248     struct spread_spectrum_data *hdmi_ss_params;
0249     uint32_t hdmi_ss_params_cnt;
0250     struct spread_spectrum_data *dvi_ss_params;
0251     uint32_t dvi_ss_params_cnt;
0252     struct spread_spectrum_data *lvds_ss_params;
0253     uint32_t lvds_ss_params_cnt;
0254
0255     uint32_t ext_clk_khz;
0256     uint32_t ref_freq_khz;
0257
0258     struct calc_pll_clock_source calc_pll;
0259     struct calc_pll_clock_source calc_pll_hdmi;
0260 };
0261
0262 bool dce110_clk_src_construct(
0263     struct dce110_clk_src *clk_src,
0264     struct dc_context *ctx,
0265     struct dc_bios *bios,
0266     enum clock_source_id,
0267     const struct dce110_clk_src_regs *regs,
0268     const struct dce110_clk_src_shift *cs_shift,
0269     const struct dce110_clk_src_mask *cs_mask);
0270
0271 bool dce112_clk_src_construct(
0272     struct dce110_clk_src *clk_src,
0273     struct dc_context *ctx,
0274     struct dc_bios *bios,
0275     enum clock_source_id id,
0276     const struct dce110_clk_src_regs *regs,
0277     const struct dce110_clk_src_shift *cs_shift,
0278     const struct dce110_clk_src_mask *cs_mask);
0279
0280 bool dcn20_clk_src_construct(
0281     struct dce110_clk_src *clk_src,
0282     struct dc_context *ctx,
0283     struct dc_bios *bios,
0284     enum clock_source_id id,
0285     const struct dce110_clk_src_regs *regs,
0286     const struct dce110_clk_src_shift *cs_shift,
0287     const struct dce110_clk_src_mask *cs_mask);
0288
0289 bool dcn3_clk_src_construct(
0290     struct dce110_clk_src *clk_src,
0291     struct dc_context *ctx,
0292     struct dc_bios *bios,
0293     enum clock_source_id id,
0294     const struct dce110_clk_src_regs *regs,
0295     const struct dce110_clk_src_shift *cs_shift,
0296     const struct dce110_clk_src_mask *cs_mask);
0297
0298 bool dcn301_clk_src_construct(
0299     struct dce110_clk_src *clk_src,
0300     struct dc_context *ctx,
0301     struct dc_bios *bios,
0302     enum clock_source_id id,
0303     const struct dce110_clk_src_regs *regs,
0304     const struct dce110_clk_src_shift *cs_shift,
0305     const struct dce110_clk_src_mask *cs_mask);
0306
0307 bool dcn31_clk_src_construct(
0308     struct dce110_clk_src *clk_src,
0309     struct dc_context *ctx,
0310     struct dc_bios *bios,
0311     enum clock_source_id id,
0312     const struct dce110_clk_src_regs *regs,
0313     const struct dce110_clk_src_shift *cs_shift,
0314     const struct dce110_clk_src_mask *cs_mask);
0315
0316 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
0317 struct pixel_rate_range_table_entry {
0318     unsigned int range_min_khz;
0319     unsigned int range_max_khz;
0320     unsigned int target_pixel_rate_khz;
0321     unsigned short mult_factor;
0322     unsigned short div_factor;
0323 };
0324
0325 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[];
0326 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
0327         unsigned int pixel_rate_khz);
0328
0329 #endif