dc/dce/dce_aux.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef __DAL_AUX_ENGINE_DCE110_H__
0027 #define __DAL_AUX_ENGINE_DCE110_H__
0028
0029 #include "i2caux_interface.h"
0030 #include "inc/hw/aux_engine.h"
0031
0032 enum aux_return_code_type;
0033
0034 #define AUX_COMMON_REG_LIST0(id)\
0035     SRI(AUX_CONTROL, DP_AUX, id), \
0036     SRI(AUX_ARB_CONTROL, DP_AUX, id), \
0037     SRI(AUX_SW_DATA, DP_AUX, id), \
0038     SRI(AUX_SW_CONTROL, DP_AUX, id), \
0039     SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
0040     SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
0041     SRI(AUX_SW_STATUS, DP_AUX, id)
0042
0043 #define AUX_COMMON_REG_LIST(id)\
0044     SRI(AUX_CONTROL, DP_AUX, id), \
0045     SRI(AUX_ARB_CONTROL, DP_AUX, id), \
0046     SRI(AUX_SW_DATA, DP_AUX, id), \
0047     SRI(AUX_SW_CONTROL, DP_AUX, id), \
0048     SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
0049     SRI(AUX_SW_STATUS, DP_AUX, id), \
0050     SR(AUXN_IMPCAL), \
0051     SR(AUXP_IMPCAL)
0052
0053 struct dce110_aux_registers {
0054     uint32_t AUX_CONTROL;
0055     uint32_t AUX_ARB_CONTROL;
0056     uint32_t AUX_SW_DATA;
0057     uint32_t AUX_SW_CONTROL;
0058     uint32_t AUX_INTERRUPT_CONTROL;
0059     uint32_t AUX_DPHY_RX_CONTROL1;
0060     uint32_t AUX_SW_STATUS;
0061     uint32_t AUXN_IMPCAL;
0062     uint32_t AUXP_IMPCAL;
0063
0064     uint32_t AUX_RESET_MASK;
0065 };
0066
0067 #define DCE_AUX_REG_FIELD_LIST(type)\
0068     type AUX_EN;\
0069     type AUX_RESET;\
0070     type AUX_RESET_DONE;\
0071     type AUX_REG_RW_CNTL_STATUS;\
0072     type AUX_SW_USE_AUX_REG_REQ;\
0073     type AUX_SW_DONE_USING_AUX_REG;\
0074     type AUX_SW_AUTOINCREMENT_DISABLE;\
0075     type AUX_SW_DATA_RW;\
0076     type AUX_SW_INDEX;\
0077     type AUX_SW_GO;\
0078     type AUX_SW_DATA;\
0079     type AUX_SW_REPLY_BYTE_COUNT;\
0080     type AUX_SW_DONE;\
0081     type AUX_SW_DONE_ACK;\
0082     type AUXN_IMPCAL_ENABLE;\
0083     type AUXP_IMPCAL_ENABLE;\
0084     type AUXN_IMPCAL_OVERRIDE_ENABLE;\
0085     type AUXP_IMPCAL_OVERRIDE_ENABLE;\
0086     type AUX_RX_TIMEOUT_LEN;\
0087     type AUX_RX_TIMEOUT_LEN_MUL;\
0088     type AUXN_CALOUT_ERROR_AK;\
0089     type AUXP_CALOUT_ERROR_AK;\
0090     type AUX_SW_START_DELAY;\
0091     type AUX_SW_WR_BYTES
0092
0093 #define DCE10_AUX_MASK_SH_LIST(mask_sh)\
0094     AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
0095     AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
0096     AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
0097     AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
0098     AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
0099     AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
0100     AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
0101     AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0102     AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
0103     AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
0104     AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
0105     AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
0106     AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
0107     AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
0108     AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
0109     AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
0110     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
0111     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
0112     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
0113     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
0114
0115 #define DCE_AUX_MASK_SH_LIST(mask_sh)\
0116     AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
0117     AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
0118     AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
0119     AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
0120     AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
0121     AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
0122     AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
0123     AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
0124     AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
0125     AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0126     AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
0127     AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
0128     AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
0129     AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
0130     AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
0131     AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
0132     AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
0133     AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
0134     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
0135     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
0136     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
0137     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
0138
0139 #define DCE12_AUX_MASK_SH_LIST(mask_sh)\
0140     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
0141     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
0142     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
0143     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
0144     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
0145     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
0146     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
0147     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
0148     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
0149     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0150     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
0151     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0152     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
0153     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
0154     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
0155     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
0156     AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
0157     AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
0158     AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
0159     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
0160     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
0161     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
0162     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
0163
0164 /* DCN10 MASK */
0165 #define DCN10_AUX_MASK_SH_LIST(mask_sh)\
0166     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
0167     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
0168     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
0169     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
0170     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
0171     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
0172     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
0173     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
0174     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
0175     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0176     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
0177     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0178     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
0179     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
0180     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
0181     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
0182     AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
0183     AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\
0184     AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\
0185     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\
0186     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\
0187     AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\
0188     AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)
0189
0190 /* for all other DCN */
0191 #define DCN_AUX_MASK_SH_LIST(mask_sh)\
0192     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\
0193     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\
0194     AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
0195     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
0196     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
0197     AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
0198     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
0199     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
0200     AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
0201     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0202     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
0203     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
0204     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
0205     AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\
0206     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\
0207     AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\
0208     AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\
0209     AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
0210     AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)
0211
0212 #define AUX_SF(reg_name, field_name, post_fix)\
0213     .field_name = reg_name ## __ ## field_name ## post_fix
0214
0215 enum {  /* This is the timeout as defined in DP 1.2a,
0216      * 2.3.4 "Detailed uPacket TX AUX CH State Description".
0217      */
0218     AUX_TIMEOUT_PERIOD = 400,
0219
0220     /* Ideally, the SW timeout should be just above 550usec
0221      * which is programmed in HW.
0222      * But the SW timeout of 600usec is not reliable,
0223      * because on some systems, delay_in_microseconds()
0224      * returns faster than it should.
0225      * EPR #379763: by trial-and-error on different systems,
0226      * 700usec is the minimum reliable SW timeout for polling
0227      * the AUX_SW_STATUS.AUX_SW_DONE bit.
0228      * This timeout expires *only* when there is
0229      * AUX Error or AUX Timeout conditions - not during normal operation.
0230      * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
0231      * at most within ~240usec. That means,
0232      * increasing this timeout will not affect normal operation,
0233      * and we'll timeout after
0234      * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec.
0235      * This timeout is especially important for
0236      * converters, resume from S3, and CTS.
0237      */
0238     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6
0239 };
0240
0241 struct dce_aux {
0242     uint32_t inst;
0243     struct ddc *ddc;
0244     struct dc_context *ctx;
0245     /* following values are expressed in milliseconds */
0246     uint32_t delay;
0247     uint32_t max_defer_write_retry;
0248
0249     bool acquire_reset;
0250     struct dce_aux_funcs *funcs;
0251 };
0252
0253 struct dce110_aux_registers_mask {
0254     DCE_AUX_REG_FIELD_LIST(uint32_t);
0255 };
0256
0257 struct dce110_aux_registers_shift {
0258     DCE_AUX_REG_FIELD_LIST(uint8_t);
0259 };
0260
0261
0262 struct aux_engine_dce110 {
0263     struct dce_aux base;
0264     const struct dce110_aux_registers *regs;
0265     const struct dce110_aux_registers_mask *mask;
0266     const struct dce110_aux_registers_shift *shift;
0267     struct {
0268         uint32_t aux_control;
0269         uint32_t aux_arb_control;
0270         uint32_t aux_sw_data;
0271         uint32_t aux_sw_control;
0272         uint32_t aux_interrupt_control;
0273         uint32_t aux_dphy_rx_control1;
0274         uint32_t aux_dphy_rx_control0;
0275         uint32_t aux_sw_status;
0276     } addr;
0277     uint32_t polling_timeout_period;
0278 };
0279
0280 struct aux_engine_dce110_init_data {
0281     uint32_t engine_id;
0282     uint32_t timeout_period;
0283     struct dc_context *ctx;
0284     const struct dce110_aux_registers *regs;
0285 };
0286
0287 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
0288         struct dc_context *ctx,
0289         uint32_t inst,
0290         uint32_t timeout_period,
0291         const struct dce110_aux_registers *regs,
0292
0293         const struct dce110_aux_registers_mask *mask,
0294         const struct dce110_aux_registers_shift *shift,
0295         bool is_ext_aux_timeout_configurable);
0296
0297 void dce110_engine_destroy(struct dce_aux **engine);
0298
0299 bool dce110_aux_engine_acquire(
0300     struct dce_aux *aux_engine,
0301     struct ddc *ddc);
0302
0303 int dce_aux_transfer_raw(struct ddc_service *ddc,
0304         struct aux_payload *cmd,
0305         enum aux_return_code_type *operation_result);
0306
0307 int dce_aux_transfer_dmub_raw(struct ddc_service *ddc,
0308         struct aux_payload *payload,
0309         enum aux_return_code_type *operation_result);
0310 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
0311         struct aux_payload *cmd);
0312
0313 struct dce_aux_funcs {
0314     uint32_t (*configure_timeout)
0315         (struct ddc_service *ddc,
0316          uint32_t timeout);
0317     void (*destroy)
0318         (struct aux_engine **ptr);
0319 };
0320
0321 #endif