dc/dce/dce_audio.h

0001 /*
0002  * Copyright 2012-15 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 #ifndef __DAL_AUDIO_DCE_110_H__
0026 #define __DAL_AUDIO_DCE_110_H__
0027
0028 #include "audio.h"
0029
0030 #define AUD_COMMON_REG_LIST(id)\
0031     SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
0032     SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
0033     SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
0034     SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
0035     SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
0036     SR(DCCG_AUDIO_DTO_SOURCE),\
0037     SR(DCCG_AUDIO_DTO0_MODULE),\
0038     SR(DCCG_AUDIO_DTO0_PHASE),\
0039     SR(DCCG_AUDIO_DTO1_MODULE),\
0040     SR(DCCG_AUDIO_DTO1_PHASE)
0041
0042
0043  /* set field name */
0044 #define SF(reg_name, field_name, post_fix)\
0045     .field_name = reg_name ## __ ## field_name ## post_fix
0046
0047
0048 #define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
0049         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
0050         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
0051         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
0052         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
0053         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
0054         SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
0055         SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
0056         SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
0057         SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
0058         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
0059         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
0060         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
0061
0062 #define AUD_COMMON_MASK_SH_LIST(mask_sh)\
0063         AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\
0064         SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0065         SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
0066
0067 #if defined(CONFIG_DRM_AMD_DC_SI)
0068 #define AUD_DCE60_MASK_SH_LIST(mask_sh)\
0069         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
0070         SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
0071         SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
0072         SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
0073         SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
0074         SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
0075         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
0076         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
0077         SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh), \
0078         SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
0079         SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
0080 #endif
0081
0082 struct dce_audio_registers {
0083     uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
0084     uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;
0085
0086     uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;
0087     uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
0088     uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
0089
0090     uint32_t DCCG_AUDIO_DTO_SOURCE;
0091     uint32_t DCCG_AUDIO_DTO0_MODULE;
0092     uint32_t DCCG_AUDIO_DTO0_PHASE;
0093     uint32_t DCCG_AUDIO_DTO1_MODULE;
0094     uint32_t DCCG_AUDIO_DTO1_PHASE;
0095
0096     uint32_t AUDIO_RATE_CAPABILITIES;
0097 };
0098
0099 struct dce_audio_shift {
0100     uint8_t AZALIA_ENDPOINT_REG_INDEX;
0101     uint8_t AZALIA_ENDPOINT_REG_DATA;
0102
0103     uint8_t AUDIO_RATE_CAPABILITIES;
0104     uint8_t CLKSTOP;
0105     uint8_t EPSS;
0106
0107     uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;
0108     uint8_t DCCG_AUDIO_DTO_SEL;
0109     uint8_t DCCG_AUDIO_DTO0_MODULE;
0110     uint8_t DCCG_AUDIO_DTO0_PHASE;
0111     uint8_t DCCG_AUDIO_DTO1_MODULE;
0112     uint8_t DCCG_AUDIO_DTO1_PHASE;
0113     uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
0114     uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
0115     uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
0116     uint32_t CLOCK_GATING_DISABLE;
0117 };
0118
0119 struct dce_audio_mask {
0120     uint32_t AZALIA_ENDPOINT_REG_INDEX;
0121     uint32_t AZALIA_ENDPOINT_REG_DATA;
0122
0123     uint32_t AUDIO_RATE_CAPABILITIES;
0124     uint32_t CLKSTOP;
0125     uint32_t EPSS;
0126
0127     uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;
0128     uint32_t DCCG_AUDIO_DTO_SEL;
0129     uint32_t DCCG_AUDIO_DTO0_MODULE;
0130     uint32_t DCCG_AUDIO_DTO0_PHASE;
0131     uint32_t DCCG_AUDIO_DTO1_MODULE;
0132     uint32_t DCCG_AUDIO_DTO1_PHASE;
0133     uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
0134     uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
0135     uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
0136     uint32_t CLOCK_GATING_DISABLE;
0137
0138 };
0139
0140 struct dce_audio {
0141     struct audio base;
0142     const struct dce_audio_registers *regs;
0143     const struct dce_audio_shift *shifts;
0144     const struct dce_audio_mask *masks;
0145 };
0146
0147 struct audio *dce_audio_create(
0148         struct dc_context *ctx,
0149         unsigned int inst,
0150         const struct dce_audio_registers *reg,
0151         const struct dce_audio_shift *shifts,
0152         const struct dce_audio_mask *masks);
0153
0154 #if defined(CONFIG_DRM_AMD_DC_SI)
0155 struct audio *dce60_audio_create(
0156         struct dc_context *ctx,
0157         unsigned int inst,
0158         const struct dce_audio_registers *reg,
0159         const struct dce_audio_shift *shifts,
0160         const struct dce_audio_mask *masks);
0161 #endif
0162
0163 void dce_aud_destroy(struct audio **audio);
0164
0165 void dce_aud_hw_init(struct audio *audio);
0166
0167 void dce_aud_az_enable(struct audio *audio);
0168 void dce_aud_az_disable(struct audio *audio);
0169
0170 void dce_aud_az_configure(struct audio *audio,
0171     enum signal_type signal,
0172     const struct audio_crtc_info *crtc_info,
0173     const struct audio_info *audio_info);
0174
0175 void dce_aud_wall_dto_setup(struct audio *audio,
0176     enum signal_type signal,
0177     const struct audio_crtc_info *crtc_info,
0178     const struct audio_pll_info *pll_info);
0179
0180 #endif   /*__DAL_AUDIO_DCE_110_H__*/