dc/dce/dce_abm.h

0001 /*
0002  * Copyright 2012-16 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026
0027 #ifndef _DCE_ABM_H_
0028 #define _DCE_ABM_H_
0029
0030 #include "abm.h"
0031
0032 #define ABM_COMMON_REG_LIST_DCE_BASE() \
0033     SR(MASTER_COMM_CNTL_REG), \
0034     SR(MASTER_COMM_CMD_REG), \
0035     SR(MASTER_COMM_DATA_REG1)
0036
0037 #define ABM_DCE110_COMMON_REG_LIST() \
0038     ABM_COMMON_REG_LIST_DCE_BASE(), \
0039     SR(DC_ABM1_HG_SAMPLE_RATE), \
0040     SR(DC_ABM1_LS_SAMPLE_RATE), \
0041     SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
0042     SR(DC_ABM1_HG_MISC_CTRL), \
0043     SR(DC_ABM1_IPCSC_COEFF_SEL), \
0044     SR(BL1_PWM_CURRENT_ABM_LEVEL), \
0045     SR(BL1_PWM_TARGET_ABM_LEVEL), \
0046     SR(BL1_PWM_USER_LEVEL), \
0047     SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
0048     SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
0049     SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
0050     SR(DC_ABM1_ACE_THRES_12), \
0051     SR(BIOS_SCRATCH_2)
0052
0053 #define ABM_DCN10_REG_LIST(id)\
0054     ABM_COMMON_REG_LIST_DCE_BASE(), \
0055     SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
0056     SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
0057     SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
0058     SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
0059     SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
0060     SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
0061     SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
0062     SRI(BL1_PWM_USER_LEVEL, ABM, id), \
0063     SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
0064     SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
0065     SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
0066     SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
0067     NBIO_SR(BIOS_SCRATCH_2)
0068
0069 #define ABM_DCN20_REG_LIST() \
0070     ABM_COMMON_REG_LIST_DCE_BASE(), \
0071     SR(DC_ABM1_HG_SAMPLE_RATE), \
0072     SR(DC_ABM1_LS_SAMPLE_RATE), \
0073     SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
0074     SR(DC_ABM1_HG_MISC_CTRL), \
0075     SR(DC_ABM1_IPCSC_COEFF_SEL), \
0076     SR(BL1_PWM_CURRENT_ABM_LEVEL), \
0077     SR(BL1_PWM_TARGET_ABM_LEVEL), \
0078     SR(BL1_PWM_USER_LEVEL), \
0079     SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
0080     SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
0081     SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
0082     SR(DC_ABM1_ACE_THRES_12), \
0083     NBIO_SR(BIOS_SCRATCH_2)
0084
0085 #define ABM_DCN301_REG_LIST(id)\
0086     ABM_COMMON_REG_LIST_DCE_BASE(), \
0087     SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
0088     SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
0089     SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
0090     SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
0091     SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
0092     SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
0093     SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
0094     SRI(BL1_PWM_USER_LEVEL, ABM, id), \
0095     SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
0096     SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
0097     NBIO_SR(BIOS_SCRATCH_2)
0098
0099 #define ABM_DCN302_REG_LIST(id)\
0100     ABM_COMMON_REG_LIST_DCE_BASE(), \
0101     SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
0102     SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
0103     SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
0104     SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
0105     SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
0106     SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
0107     SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
0108     SRI(BL1_PWM_USER_LEVEL, ABM, id), \
0109     SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
0110     SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
0111     SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
0112     SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
0113     NBIO_SR(BIOS_SCRATCH_2)
0114
0115 #define ABM_DCN30_REG_LIST(id)\
0116     ABM_COMMON_REG_LIST_DCE_BASE(), \
0117     SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
0118     SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
0119     SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
0120     SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
0121     SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
0122     SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
0123     SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
0124     SRI(BL1_PWM_USER_LEVEL, ABM, id), \
0125     SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
0126     SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
0127     SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
0128     SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
0129     NBIO_SR(BIOS_SCRATCH_2)
0130
0131 #define ABM_DCN32_REG_LIST(id)\
0132     SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
0133     SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
0134     SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
0135     SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
0136     SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
0137     SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
0138     SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
0139     SRI(BL1_PWM_USER_LEVEL, ABM, id), \
0140     SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
0141     SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
0142     SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
0143     SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
0144     NBIO_SR(BIOS_SCRATCH_2)
0145
0146 #define ABM_SF(reg_name, field_name, post_fix)\
0147     .field_name = reg_name ## __ ## field_name ## post_fix
0148
0149 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
0150     ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
0151     ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
0152     ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
0153     ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
0154
0155 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \
0156     ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0157     ABM_SF(DC_ABM1_HG_MISC_CTRL, \
0158             ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
0159     ABM_SF(DC_ABM1_HG_MISC_CTRL, \
0160             ABM1_HG_VMAX_SEL, mask_sh), \
0161     ABM_SF(DC_ABM1_HG_MISC_CTRL, \
0162             ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
0163     ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
0164             ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
0165     ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
0166             ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
0167     ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
0168             ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
0169     ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
0170             BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
0171     ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
0172             BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
0173     ABM_SF(BL1_PWM_USER_LEVEL, \
0174             BL1_PWM_USER_LEVEL, mask_sh), \
0175     ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0176             ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
0177     ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0178             ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
0179     ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
0180             ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0181     ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
0182             ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0183     ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
0184             ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
0185
0186 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \
0187     ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
0188     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0189             ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
0190     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0191             ABM1_HG_VMAX_SEL, mask_sh), \
0192     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0193             ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
0194     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0195             ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
0196     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0197             ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
0198     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0199             ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
0200     ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
0201             BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
0202     ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
0203             BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
0204     ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
0205             BL1_PWM_USER_LEVEL, mask_sh), \
0206     ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0207             ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
0208     ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0209             ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
0210     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0211             ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0212     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0213             ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0214     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0215             ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
0216
0217 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
0218
0219 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
0220
0221 #define ABM_MASK_SH_LIST_DCN32(mask_sh) \
0222     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0223             ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
0224     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0225             ABM1_HG_VMAX_SEL, mask_sh), \
0226     ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
0227             ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
0228     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0229             ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
0230     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0231             ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
0232     ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
0233             ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
0234     ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
0235             BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
0236     ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
0237             BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
0238     ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
0239             BL1_PWM_USER_LEVEL, mask_sh), \
0240     ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0241             ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
0242     ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
0243             ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
0244     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0245             ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0246     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0247             ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
0248     ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
0249             ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
0250
0251 #define ABM_REG_FIELD_LIST(type) \
0252     type ABM1_HG_NUM_OF_BINS_SEL; \
0253     type ABM1_HG_VMAX_SEL; \
0254     type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
0255     type ABM1_IPCSC_COEFF_SEL_R; \
0256     type ABM1_IPCSC_COEFF_SEL_G; \
0257     type ABM1_IPCSC_COEFF_SEL_B; \
0258     type BL1_PWM_CURRENT_ABM_LEVEL; \
0259     type BL1_PWM_TARGET_ABM_LEVEL; \
0260     type BL1_PWM_USER_LEVEL; \
0261     type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
0262     type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
0263     type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
0264     type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
0265     type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
0266     type MASTER_COMM_INTERRUPT; \
0267     type MASTER_COMM_CMD_REG_BYTE0; \
0268     type MASTER_COMM_CMD_REG_BYTE1; \
0269     type MASTER_COMM_CMD_REG_BYTE2
0270
0271 struct dce_abm_shift {
0272     ABM_REG_FIELD_LIST(uint8_t);
0273 };
0274
0275 struct dce_abm_mask {
0276     ABM_REG_FIELD_LIST(uint32_t);
0277 };
0278
0279 struct dce_abm_registers {
0280     uint32_t DC_ABM1_HG_SAMPLE_RATE;
0281     uint32_t DC_ABM1_LS_SAMPLE_RATE;
0282     uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
0283     uint32_t DC_ABM1_HG_MISC_CTRL;
0284     uint32_t DC_ABM1_IPCSC_COEFF_SEL;
0285     uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
0286     uint32_t BL1_PWM_TARGET_ABM_LEVEL;
0287     uint32_t BL1_PWM_USER_LEVEL;
0288     uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
0289     uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
0290     uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
0291     uint32_t DC_ABM1_ACE_THRES_12;
0292     uint32_t MASTER_COMM_CNTL_REG;
0293     uint32_t MASTER_COMM_CMD_REG;
0294     uint32_t MASTER_COMM_DATA_REG1;
0295     uint32_t BIOS_SCRATCH_2;
0296 };
0297
0298 struct dce_abm {
0299     struct abm base;
0300     const struct dce_abm_registers *regs;
0301     const struct dce_abm_shift *abm_shift;
0302     const struct dce_abm_mask *abm_mask;
0303 };
0304
0305 struct abm *dce_abm_create(
0306     struct dc_context *ctx,
0307     const struct dce_abm_registers *regs,
0308     const struct dce_abm_shift *abm_shift,
0309     const struct dce_abm_mask *abm_mask);
0310
0311 void dce_abm_destroy(struct abm **abm);
0312
0313 #endif /* _DCE_ABM_H_ */