display/dc/dc_stream.h

0001 /*
0002  * Copyright 2012-14 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DC_STREAM_H_
0027 #define DC_STREAM_H_
0028
0029 #include "dc_types.h"
0030 #include "grph_object_defs.h"
0031
0032 /*******************************************************************************
0033  * Stream Interfaces
0034  ******************************************************************************/
0035 struct timing_sync_info {
0036     int group_id;
0037     int group_size;
0038     bool master;
0039 };
0040
0041 struct dc_stream_status {
0042     int primary_otg_inst;
0043     int stream_enc_inst;
0044     int plane_count;
0045     int audio_inst;
0046     struct timing_sync_info timing_sync_info;
0047     struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
0048     bool is_abm_supported;
0049 };
0050
0051 enum hubp_dmdata_mode {
0052     DMDATA_SW_MODE,
0053     DMDATA_HW_MODE
0054 };
0055
0056 struct dc_dmdata_attributes {
0057     /* Specifies whether dynamic meta data will be updated by software
0058      * or has to be fetched by hardware (DMA mode)
0059      */
0060     enum hubp_dmdata_mode dmdata_mode;
0061     /* Specifies if current dynamic meta data is to be used only for the current frame */
0062     bool dmdata_repeat;
0063     /* Specifies the size of Dynamic Metadata surface in byte.  Size of 0 means no Dynamic metadata is fetched */
0064     uint32_t dmdata_size;
0065     /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
0066     bool dmdata_updated;
0067     /* If hardware mode is used, the base address where DMDATA surface is located */
0068     PHYSICAL_ADDRESS_LOC address;
0069     /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
0070     bool dmdata_qos_mode;
0071     /* If qos_mode = 1, this is the QOS value to be used: */
0072     uint32_t dmdata_qos_level;
0073     /* Specifies the value in unit of REFCLK cycles to be added to the
0074      * current time to produce the Amortized deadline for Dynamic Metadata chunk request
0075      */
0076     uint32_t dmdata_dl_delta;
0077     /* An unbounded array of uint32s, represents software dmdata to be loaded */
0078     uint32_t *dmdata_sw_data;
0079 };
0080
0081 struct dc_writeback_info {
0082     bool wb_enabled;
0083     int dwb_pipe_inst;
0084     struct dc_dwb_params dwb_params;
0085     struct mcif_buf_params mcif_buf_params;
0086     struct mcif_warmup_params mcif_warmup_params;
0087     /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
0088     struct dc_plane_state *writeback_source_plane;
0089     /* source MPCC instance.  for use by internally by dc */
0090     int mpcc_inst;
0091 };
0092
0093 struct dc_writeback_update {
0094     unsigned int num_wb_info;
0095     struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
0096 };
0097
0098 enum vertical_interrupt_ref_point {
0099     START_V_UPDATE = 0,
0100     START_V_SYNC,
0101     INVALID_POINT
0102
0103     //For now, only v_update interrupt is used.
0104     //START_V_BLANK,
0105     //START_V_ACTIVE
0106 };
0107
0108 struct periodic_interrupt_config {
0109     enum vertical_interrupt_ref_point ref_point;
0110     int lines_offset;
0111 };
0112
0113 struct dc_mst_stream_bw_update {
0114     bool is_increase; // is bandwidth reduced or increased
0115     uint32_t mst_stream_bw; // new mst bandwidth in kbps
0116 };
0117
0118 union stream_update_flags {
0119     struct {
0120         uint32_t scaling:1;
0121         uint32_t out_tf:1;
0122         uint32_t out_csc:1;
0123         uint32_t abm_level:1;
0124         uint32_t dpms_off:1;
0125         uint32_t gamut_remap:1;
0126         uint32_t wb_update:1;
0127         uint32_t dsc_changed : 1;
0128         uint32_t mst_bw : 1;
0129         uint32_t crtc_timing_adjust : 1;
0130     } bits;
0131
0132     uint32_t raw;
0133 };
0134
0135 struct test_pattern {
0136     enum dp_test_pattern type;
0137     enum dp_test_pattern_color_space color_space;
0138     struct link_training_settings const *p_link_settings;
0139     unsigned char const *p_custom_pattern;
0140     unsigned int cust_pattern_size;
0141 };
0142
0143 #define SUBVP_DRR_MARGIN_US 500 // 500us for DRR margin (SubVP + DRR)
0144
0145 enum mall_stream_type {
0146     SUBVP_NONE, // subvp not in use
0147     SUBVP_MAIN, // subvp in use, this stream is main stream
0148     SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream
0149 };
0150
0151 struct mall_stream_config {
0152     /* MALL stream config to indicate if the stream is phantom or not.
0153      * We will use a phantom stream to indicate that the pipe is phantom.
0154      */
0155     enum mall_stream_type type;
0156     struct dc_stream_state *paired_stream;  // master / slave stream
0157 };
0158
0159 struct dc_stream_state {
0160     // sink is deprecated, new code should not reference
0161     // this pointer
0162     struct dc_sink *sink;
0163
0164     struct dc_link *link;
0165     /* For dynamic link encoder assignment, update the link encoder assigned to
0166      * a stream via the volatile dc_state rather than the static dc_link.
0167      */
0168     struct link_encoder *link_enc;
0169     struct dc_panel_patch sink_patches;
0170     union display_content_support content_support;
0171     struct dc_crtc_timing timing;
0172     struct dc_crtc_timing_adjust adjust;
0173     struct dc_info_packet vrr_infopacket;
0174     struct dc_info_packet vsc_infopacket;
0175     struct dc_info_packet vsp_infopacket;
0176     struct dc_info_packet hfvsif_infopacket;
0177     struct dc_info_packet vtem_infopacket;
0178     uint8_t dsc_packed_pps[128];
0179     struct rect src; /* composition area */
0180     struct rect dst; /* stream addressable area */
0181
0182     struct audio_info audio_info;
0183
0184     struct dc_info_packet hdr_static_metadata;
0185     PHYSICAL_ADDRESS_LOC dmdata_address;
0186     bool   use_dynamic_meta;
0187
0188     struct dc_transfer_func *out_transfer_func;
0189     struct colorspace_transform gamut_remap_matrix;
0190     struct dc_csc_transform csc_color_matrix;
0191
0192     enum dc_color_space output_color_space;
0193     enum dc_dither_option dither_option;
0194
0195     enum view_3d_format view_format;
0196
0197     bool use_vsc_sdp_for_colorimetry;
0198     bool ignore_msa_timing_param;
0199
0200     bool allow_freesync;
0201     bool vrr_active_variable;
0202     bool freesync_on_desktop;
0203
0204     bool converter_disable_audio;
0205     uint8_t qs_bit;
0206     uint8_t qy_bit;
0207
0208     /* TODO: custom INFO packets */
0209     /* TODO: ABM info (DMCU) */
0210     /* TODO: CEA VIC */
0211
0212     /* DMCU info */
0213     unsigned int abm_level;
0214
0215     struct periodic_interrupt_config periodic_interrupt0;
0216     struct periodic_interrupt_config periodic_interrupt1;
0217
0218     /* from core_stream struct */
0219     struct dc_context *ctx;
0220
0221     /* used by DCP and FMT */
0222     struct bit_depth_reduction_params bit_depth_params;
0223     struct clamping_and_pixel_encoding_params clamping;
0224
0225     int phy_pix_clk;
0226     enum signal_type signal;
0227     bool dpms_off;
0228
0229     void *dm_stream_context;
0230
0231     struct dc_cursor_attributes cursor_attributes;
0232     struct dc_cursor_position cursor_position;
0233     uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
0234
0235     /* from stream struct */
0236     struct kref refcount;
0237
0238     struct crtc_trigger_info triggered_crtc_reset;
0239
0240     /* writeback */
0241     unsigned int num_wb_info;
0242     struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
0243     const struct dc_transfer_func *func_shaper;
0244     const struct dc_3dlut *lut3d_func;
0245     /* Computed state bits */
0246     bool mode_changed : 1;
0247
0248     /* Output from DC when stream state is committed or altered
0249      * DC may only access these values during:
0250      * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
0251      * values may not change outside of those calls
0252      */
0253     struct {
0254         // For interrupt management, some hardware instance
0255         // offsets need to be exposed to DM
0256         uint8_t otg_offset;
0257     } out;
0258
0259     bool apply_edp_fast_boot_optimization;
0260     bool apply_seamless_boot_optimization;
0261     uint32_t apply_boot_odm_mode;
0262
0263     uint32_t stream_id;
0264
0265     struct test_pattern test_pattern;
0266     union stream_update_flags update_flags;
0267
0268     bool has_non_synchronizable_pclk;
0269     bool vblank_synchronized;
0270     struct mall_stream_config mall_stream_config;
0271
0272     bool odm_2to1_policy_applied;
0273 };
0274
0275 #define ABM_LEVEL_IMMEDIATE_DISABLE 255
0276
0277 struct dc_stream_update {
0278     struct dc_stream_state *stream;
0279
0280     struct rect src;
0281     struct rect dst;
0282     struct dc_transfer_func *out_transfer_func;
0283     struct dc_info_packet *hdr_static_metadata;
0284     unsigned int *abm_level;
0285
0286     struct periodic_interrupt_config *periodic_interrupt0;
0287     struct periodic_interrupt_config *periodic_interrupt1;
0288
0289     struct dc_info_packet *vrr_infopacket;
0290     struct dc_info_packet *vsc_infopacket;
0291     struct dc_info_packet *vsp_infopacket;
0292     struct dc_info_packet *hfvsif_infopacket;
0293     struct dc_info_packet *vtem_infopacket;
0294     bool *dpms_off;
0295     bool integer_scaling_update;
0296     bool *allow_freesync;
0297     bool *vrr_active_variable;
0298
0299     struct colorspace_transform *gamut_remap;
0300     enum dc_color_space *output_color_space;
0301     enum dc_dither_option *dither_option;
0302
0303     struct dc_csc_transform *output_csc_transform;
0304
0305     struct dc_writeback_update *wb_update;
0306     struct dc_dsc_config *dsc_config;
0307     struct dc_mst_stream_bw_update *mst_bw_update;
0308     struct dc_transfer_func *func_shaper;
0309     struct dc_3dlut *lut3d_func;
0310
0311     struct test_pattern *pending_test_pattern;
0312     struct dc_crtc_timing_adjust *crtc_timing_adjust;
0313 };
0314
0315 bool dc_is_stream_unchanged(
0316     struct dc_stream_state *old_stream, struct dc_stream_state *stream);
0317 bool dc_is_stream_scaling_unchanged(
0318     struct dc_stream_state *old_stream, struct dc_stream_state *stream);
0319
0320 /*
0321  * Setup stream attributes if no stream updates are provided
0322  * there will be no impact on the stream parameters
0323  *
0324  * Set up surface attributes and associate to a stream
0325  * The surfaces parameter is an absolute set of all surface active for the stream.
0326  * If no surfaces are provided, the stream will be blanked; no memory read.
0327  * Any flip related attribute changes must be done through this interface.
0328  *
0329  * After this call:
0330  *   Surfaces attributes are programmed and configured to be composed into stream.
0331  *   This does not trigger a flip.  No surface address is programmed.
0332  *
0333  */
0334 bool dc_update_planes_and_stream(struct dc *dc,
0335         struct dc_surface_update *surface_updates, int surface_count,
0336         struct dc_stream_state *dc_stream,
0337         struct dc_stream_update *stream_update);
0338
0339 /*
0340  * Set up surface attributes and associate to a stream
0341  * The surfaces parameter is an absolute set of all surface active for the stream.
0342  * If no surfaces are provided, the stream will be blanked; no memory read.
0343  * Any flip related attribute changes must be done through this interface.
0344  *
0345  * After this call:
0346  *   Surfaces attributes are programmed and configured to be composed into stream.
0347  *   This does not trigger a flip.  No surface address is programmed.
0348  */
0349 void dc_commit_updates_for_stream(struct dc *dc,
0350         struct dc_surface_update *srf_updates,
0351         int surface_count,
0352         struct dc_stream_state *stream,
0353         struct dc_stream_update *stream_update,
0354         struct dc_state *state);
0355 /*
0356  * Log the current stream state.
0357  */
0358 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
0359
0360 uint8_t dc_get_current_stream_count(struct dc *dc);
0361 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
0362
0363 /*
0364  * Return the current frame counter.
0365  */
0366 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
0367
0368 /*
0369  * Send dp sdp message.
0370  */
0371 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
0372         const uint8_t *custom_sdp_message,
0373         unsigned int sdp_message_size);
0374
0375 /* TODO: Return parsed values rather than direct register read
0376  * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
0377  * being refactored properly to be dce-specific
0378  */
0379 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
0380                   uint32_t *v_blank_start,
0381                   uint32_t *v_blank_end,
0382                   uint32_t *h_position,
0383                   uint32_t *v_position);
0384
0385 enum dc_status dc_add_stream_to_ctx(
0386             struct dc *dc,
0387         struct dc_state *new_ctx,
0388         struct dc_stream_state *stream);
0389
0390 enum dc_status dc_remove_stream_from_ctx(
0391         struct dc *dc,
0392             struct dc_state *new_ctx,
0393             struct dc_stream_state *stream);
0394
0395
0396 bool dc_add_plane_to_context(
0397         const struct dc *dc,
0398         struct dc_stream_state *stream,
0399         struct dc_plane_state *plane_state,
0400         struct dc_state *context);
0401
0402 bool dc_remove_plane_from_context(
0403         const struct dc *dc,
0404         struct dc_stream_state *stream,
0405         struct dc_plane_state *plane_state,
0406         struct dc_state *context);
0407
0408 bool dc_rem_all_planes_for_stream(
0409         const struct dc *dc,
0410         struct dc_stream_state *stream,
0411         struct dc_state *context);
0412
0413 bool dc_add_all_planes_for_stream(
0414         const struct dc *dc,
0415         struct dc_stream_state *stream,
0416         struct dc_plane_state * const *plane_states,
0417         int plane_count,
0418         struct dc_state *context);
0419
0420 bool dc_stream_add_writeback(struct dc *dc,
0421         struct dc_stream_state *stream,
0422         struct dc_writeback_info *wb_info);
0423
0424 bool dc_stream_remove_writeback(struct dc *dc,
0425         struct dc_stream_state *stream,
0426         uint32_t dwb_pipe_inst);
0427
0428 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc,
0429         struct dc_state *state,
0430         struct dc_stream_state *stream);
0431
0432 bool dc_stream_warmup_writeback(struct dc *dc,
0433         int num_dwb,
0434         struct dc_writeback_info *wb_info);
0435
0436 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
0437
0438 bool dc_stream_set_dynamic_metadata(struct dc *dc,
0439         struct dc_stream_state *stream,
0440         struct dc_dmdata_attributes *dmdata_attr);
0441
0442 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
0443
0444 /*
0445  * Set up streams and links associated to drive sinks
0446  * The streams parameter is an absolute set of all active streams.
0447  *
0448  * After this call:
0449  *   Phy, Encoder, Timing Generator are programmed and enabled.
0450  *   New streams are enabled with blank stream; no memory read.
0451  */
0452 /*
0453  * Enable stereo when commit_streams is not required,
0454  * for example, frame alternate.
0455  */
0456 void dc_enable_stereo(
0457     struct dc *dc,
0458     struct dc_state *context,
0459     struct dc_stream_state *streams[],
0460     uint8_t stream_count);
0461
0462 /* Triggers multi-stream synchronization. */
0463 void dc_trigger_sync(struct dc *dc, struct dc_state *context);
0464
0465 enum surface_update_type dc_check_update_surfaces_for_stream(
0466         struct dc *dc,
0467         struct dc_surface_update *updates,
0468         int surface_count,
0469         struct dc_stream_update *stream_update,
0470         const struct dc_stream_status *stream_status);
0471
0472 /**
0473  * Create a new default stream for the requested sink
0474  */
0475 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
0476
0477 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
0478
0479 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
0480
0481 void dc_stream_retain(struct dc_stream_state *dc_stream);
0482 void dc_stream_release(struct dc_stream_state *dc_stream);
0483
0484 struct dc_stream_status *dc_stream_get_status_from_state(
0485     struct dc_state *state,
0486     struct dc_stream_state *stream);
0487 struct dc_stream_status *dc_stream_get_status(
0488     struct dc_stream_state *dc_stream);
0489
0490 #ifndef TRIM_FSFT
0491 bool dc_optimize_timing_for_fsft(
0492     struct dc_stream_state *pStream,
0493     unsigned int max_input_rate_in_khz);
0494 #endif
0495
0496 /*******************************************************************************
0497  * Cursor interfaces - To manages the cursor within a stream
0498  ******************************************************************************/
0499 /* TODO: Deprecated once we switch to dc_set_cursor_position */
0500 bool dc_stream_set_cursor_attributes(
0501     struct dc_stream_state *stream,
0502     const struct dc_cursor_attributes *attributes);
0503
0504 bool dc_stream_set_cursor_position(
0505     struct dc_stream_state *stream,
0506     const struct dc_cursor_position *position);
0507
0508
0509 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
0510                 struct dc_stream_state *stream,
0511                 struct dc_crtc_timing_adjust *adjust);
0512
0513 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
0514         struct dc_stream_state *stream,
0515         uint32_t *refresh_rate);
0516
0517 bool dc_stream_get_crtc_position(struct dc *dc,
0518                  struct dc_stream_state **stream,
0519                  int num_streams,
0520                  unsigned int *v_pos,
0521                  unsigned int *nom_v_pos);
0522
0523 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
0524 bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream,
0525                  struct crc_params *crc_window);
0526 bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc,
0527                  struct dc_stream_state *stream);
0528 #endif
0529
0530 bool dc_stream_configure_crc(struct dc *dc,
0531                  struct dc_stream_state *stream,
0532                  struct crc_params *crc_window,
0533                  bool enable,
0534                  bool continuous);
0535
0536 bool dc_stream_get_crc(struct dc *dc,
0537                struct dc_stream_state *stream,
0538                uint32_t *r_cr,
0539                uint32_t *g_y,
0540                uint32_t *b_cb);
0541
0542 void dc_stream_set_static_screen_params(struct dc *dc,
0543                     struct dc_stream_state **stream,
0544                     int num_streams,
0545                     const struct dc_static_screen_params *params);
0546
0547 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
0548         enum dc_dynamic_expansion option);
0549
0550 void dc_stream_set_dither_option(struct dc_stream_state *stream,
0551                  enum dc_dither_option option);
0552
0553 bool dc_stream_set_gamut_remap(struct dc *dc,
0554                    const struct dc_stream_state *stream);
0555
0556 bool dc_stream_program_csc_matrix(struct dc *dc,
0557                   struct dc_stream_state *stream);
0558
0559 bool dc_stream_get_crtc_position(struct dc *dc,
0560                  struct dc_stream_state **stream,
0561                  int num_streams,
0562                  unsigned int *v_pos,
0563                  unsigned int *nom_v_pos);
0564
0565 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream);
0566
0567 void dc_dmub_update_dirty_rect(struct dc *dc,
0568                    int surface_count,
0569                    struct dc_stream_state *stream,
0570                    struct dc_surface_update *srf_updates,
0571                    struct dc_state *context);
0572 #endif /* DC_STREAM_H_ */