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0001 /*
0002  * Copyright 2012-14 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025 
0026 #ifndef DC_INTERFACE_H_
0027 #define DC_INTERFACE_H_
0028 
0029 #include "dc_types.h"
0030 #include "grph_object_defs.h"
0031 #include "logger_types.h"
0032 #if defined(CONFIG_DRM_AMD_DC_HDCP)
0033 #include "hdcp_types.h"
0034 #endif
0035 #include "gpio_types.h"
0036 #include "link_service_types.h"
0037 #include "grph_object_ctrl_defs.h"
0038 #include <inc/hw/opp.h>
0039 
0040 #include "inc/hw_sequencer.h"
0041 #include "inc/compressor.h"
0042 #include "inc/hw/dmcu.h"
0043 #include "dml/display_mode_lib.h"
0044 
0045 /* forward declaration */
0046 struct aux_payload;
0047 struct set_config_cmd_payload;
0048 struct dmub_notification;
0049 
0050 #define DC_VER "3.2.198"
0051 
0052 #define MAX_SURFACES 3
0053 #define MAX_PLANES 6
0054 #define MAX_STREAMS 6
0055 #define MAX_SINKS_PER_LINK 4
0056 #define MIN_VIEWPORT_SIZE 12
0057 #define MAX_NUM_EDP 2
0058 
0059 /*******************************************************************************
0060  * Display Core Interfaces
0061  ******************************************************************************/
0062 struct dc_versions {
0063     const char *dc_ver;
0064     struct dmcu_version dmcu_version;
0065 };
0066 
0067 enum dp_protocol_version {
0068     DP_VERSION_1_4,
0069 };
0070 
0071 enum dc_plane_type {
0072     DC_PLANE_TYPE_INVALID,
0073     DC_PLANE_TYPE_DCE_RGB,
0074     DC_PLANE_TYPE_DCE_UNDERLAY,
0075     DC_PLANE_TYPE_DCN_UNIVERSAL,
0076 };
0077 
0078 // Sizes defined as multiples of 64KB
0079 enum det_size {
0080     DET_SIZE_DEFAULT = 0,
0081     DET_SIZE_192KB = 3,
0082     DET_SIZE_256KB = 4,
0083     DET_SIZE_320KB = 5,
0084     DET_SIZE_384KB = 6
0085 };
0086 
0087 
0088 struct dc_plane_cap {
0089     enum dc_plane_type type;
0090     uint32_t blends_with_above : 1;
0091     uint32_t blends_with_below : 1;
0092     uint32_t per_pixel_alpha : 1;
0093     struct {
0094         uint32_t argb8888 : 1;
0095         uint32_t nv12 : 1;
0096         uint32_t fp16 : 1;
0097         uint32_t p010 : 1;
0098         uint32_t ayuv : 1;
0099     } pixel_format_support;
0100     // max upscaling factor x1000
0101     // upscaling factors are always >= 1
0102     // for example, 1080p -> 8K is 4.0, or 4000 raw value
0103     struct {
0104         uint32_t argb8888;
0105         uint32_t nv12;
0106         uint32_t fp16;
0107     } max_upscale_factor;
0108     // max downscale factor x1000
0109     // downscale factors are always <= 1
0110     // for example, 8K -> 1080p is 0.25, or 250 raw value
0111     struct {
0112         uint32_t argb8888;
0113         uint32_t nv12;
0114         uint32_t fp16;
0115     } max_downscale_factor;
0116     // minimal width/height
0117     uint32_t min_width;
0118     uint32_t min_height;
0119 };
0120 
0121 // Color management caps (DPP and MPC)
0122 struct rom_curve_caps {
0123     uint16_t srgb : 1;
0124     uint16_t bt2020 : 1;
0125     uint16_t gamma2_2 : 1;
0126     uint16_t pq : 1;
0127     uint16_t hlg : 1;
0128 };
0129 
0130 struct dpp_color_caps {
0131     uint16_t dcn_arch : 1; // all DCE generations treated the same
0132     // input lut is different than most LUTs, just plain 256-entry lookup
0133     uint16_t input_lut_shared : 1; // shared with DGAM
0134     uint16_t icsc : 1;
0135     uint16_t dgam_ram : 1;
0136     uint16_t post_csc : 1; // before gamut remap
0137     uint16_t gamma_corr : 1;
0138 
0139     // hdr_mult and gamut remap always available in DPP (in that order)
0140     // 3d lut implies shaper LUT,
0141     // it may be shared with MPC - check MPC:shared_3d_lut flag
0142     uint16_t hw_3d_lut : 1;
0143     uint16_t ogam_ram : 1; // blnd gam
0144     uint16_t ocsc : 1;
0145     uint16_t dgam_rom_for_yuv : 1;
0146     struct rom_curve_caps dgam_rom_caps;
0147     struct rom_curve_caps ogam_rom_caps;
0148 };
0149 
0150 struct mpc_color_caps {
0151     uint16_t gamut_remap : 1;
0152     uint16_t ogam_ram : 1;
0153     uint16_t ocsc : 1;
0154     uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
0155     uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
0156 
0157     struct rom_curve_caps ogam_rom_caps;
0158 };
0159 
0160 struct dc_color_caps {
0161     struct dpp_color_caps dpp;
0162     struct mpc_color_caps mpc;
0163 };
0164 
0165 struct dc_dmub_caps {
0166     bool psr;
0167     bool mclk_sw;
0168 };
0169 
0170 struct dc_caps {
0171     uint32_t max_streams;
0172     uint32_t max_links;
0173     uint32_t max_audios;
0174     uint32_t max_slave_planes;
0175     uint32_t max_slave_yuv_planes;
0176     uint32_t max_slave_rgb_planes;
0177     uint32_t max_planes;
0178     uint32_t max_downscale_ratio;
0179     uint32_t i2c_speed_in_khz;
0180     uint32_t i2c_speed_in_khz_hdcp;
0181     uint32_t dmdata_alloc_size;
0182     unsigned int max_cursor_size;
0183     unsigned int max_video_width;
0184     unsigned int min_horizontal_blanking_period;
0185     int linear_pitch_alignment;
0186     bool dcc_const_color;
0187     bool dynamic_audio;
0188     bool is_apu;
0189     bool dual_link_dvi;
0190     bool post_blend_color_processing;
0191     bool force_dp_tps4_for_cp2520;
0192     bool disable_dp_clk_share;
0193     bool psp_setup_panel_mode;
0194     bool extended_aux_timeout_support;
0195     bool dmcub_support;
0196     bool zstate_support;
0197     uint32_t num_of_internal_disp;
0198     enum dp_protocol_version max_dp_protocol_version;
0199     unsigned int mall_size_per_mem_channel;
0200     unsigned int mall_size_total;
0201     unsigned int cursor_cache_size;
0202     struct dc_plane_cap planes[MAX_PLANES];
0203     struct dc_color_caps color;
0204     struct dc_dmub_caps dmub_caps;
0205     bool dp_hpo;
0206     bool dp_hdmi21_pcon_support;
0207     bool edp_dsc_support;
0208     bool vbios_lttpr_aware;
0209     bool vbios_lttpr_enable;
0210     uint32_t max_otg_num;
0211     uint32_t max_cab_allocation_bytes;
0212     uint32_t cache_line_size;
0213     uint32_t cache_num_ways;
0214     uint16_t subvp_fw_processing_delay_us;
0215     uint16_t subvp_prefetch_end_to_mall_start_us;
0216     uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
0217     uint16_t subvp_pstate_allow_width_us;
0218     uint16_t subvp_vertical_int_margin_us;
0219     bool seamless_odm;
0220 };
0221 
0222 struct dc_bug_wa {
0223     bool no_connect_phy_config;
0224     bool dedcn20_305_wa;
0225     bool skip_clock_update;
0226     bool lt_early_cr_pattern;
0227 };
0228 
0229 struct dc_dcc_surface_param {
0230     struct dc_size surface_size;
0231     enum surface_pixel_format format;
0232     enum swizzle_mode_values swizzle_mode;
0233     enum dc_scan_direction scan;
0234 };
0235 
0236 struct dc_dcc_setting {
0237     unsigned int max_compressed_blk_size;
0238     unsigned int max_uncompressed_blk_size;
0239     bool independent_64b_blks;
0240     //These bitfields to be used starting with DCN
0241     struct {
0242         uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
0243         uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
0244         uint32_t dcc_256_128_128 : 1;       //available starting with DCN
0245         uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
0246     } dcc_controls;
0247 };
0248 
0249 struct dc_surface_dcc_cap {
0250     union {
0251         struct {
0252             struct dc_dcc_setting rgb;
0253         } grph;
0254 
0255         struct {
0256             struct dc_dcc_setting luma;
0257             struct dc_dcc_setting chroma;
0258         } video;
0259     };
0260 
0261     bool capable;
0262     bool const_color_support;
0263 };
0264 
0265 struct dc_static_screen_params {
0266     struct {
0267         bool force_trigger;
0268         bool cursor_update;
0269         bool surface_update;
0270         bool overlay_update;
0271     } triggers;
0272     unsigned int num_frames;
0273 };
0274 
0275 
0276 /* Surface update type is used by dc_update_surfaces_and_stream
0277  * The update type is determined at the very beginning of the function based
0278  * on parameters passed in and decides how much programming (or updating) is
0279  * going to be done during the call.
0280  *
0281  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
0282  * logical calculations or hardware register programming. This update MUST be
0283  * ISR safe on windows. Currently fast update will only be used to flip surface
0284  * address.
0285  *
0286  * UPDATE_TYPE_MED is used for slower updates which require significant hw
0287  * re-programming however do not affect bandwidth consumption or clock
0288  * requirements. At present, this is the level at which front end updates
0289  * that do not require us to run bw_calcs happen. These are in/out transfer func
0290  * updates, viewport offset changes, recout size changes and pixel depth changes.
0291  * This update can be done at ISR, but we want to minimize how often this happens.
0292  *
0293  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
0294  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
0295  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
0296  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
0297  * a full update. This cannot be done at ISR level and should be a rare event.
0298  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
0299  * underscan we don't expect to see this call at all.
0300  */
0301 
0302 enum surface_update_type {
0303     UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
0304     UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
0305     UPDATE_TYPE_FULL, /* may need to shuffle resources */
0306 };
0307 
0308 /* Forward declaration*/
0309 struct dc;
0310 struct dc_plane_state;
0311 struct dc_state;
0312 
0313 
0314 struct dc_cap_funcs {
0315     bool (*get_dcc_compression_cap)(const struct dc *dc,
0316             const struct dc_dcc_surface_param *input,
0317             struct dc_surface_dcc_cap *output);
0318 };
0319 
0320 struct link_training_settings;
0321 
0322 union allow_lttpr_non_transparent_mode {
0323     struct {
0324         bool DP1_4A : 1;
0325         bool DP2_0 : 1;
0326     } bits;
0327     unsigned char raw;
0328 };
0329 
0330 /* Structure to hold configuration flags set by dm at dc creation. */
0331 struct dc_config {
0332     bool gpu_vm_support;
0333     bool disable_disp_pll_sharing;
0334     bool fbc_support;
0335     bool disable_fractional_pwm;
0336     bool allow_seamless_boot_optimization;
0337     bool seamless_boot_edp_requested;
0338     bool edp_not_connected;
0339     bool edp_no_power_sequencing;
0340     bool force_enum_edp;
0341     bool forced_clocks;
0342     union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
0343     bool multi_mon_pp_mclk_switch;
0344     bool disable_dmcu;
0345     bool enable_4to1MPC;
0346     bool enable_windowed_mpo_odm;
0347     uint32_t allow_edp_hotplug_detection;
0348     bool clamp_min_dcfclk;
0349     uint64_t vblank_alignment_dto_params;
0350     uint8_t  vblank_alignment_max_frame_time_diff;
0351     bool is_asymmetric_memory;
0352     bool is_single_rank_dimm;
0353     bool use_pipe_ctx_sync_logic;
0354     bool ignore_dpref_ss;
0355     bool enable_mipi_converter_optimization;
0356     bool use_default_clock_table;
0357 };
0358 
0359 enum visual_confirm {
0360     VISUAL_CONFIRM_DISABLE = 0,
0361     VISUAL_CONFIRM_SURFACE = 1,
0362     VISUAL_CONFIRM_HDR = 2,
0363     VISUAL_CONFIRM_MPCTREE = 4,
0364     VISUAL_CONFIRM_PSR = 5,
0365     VISUAL_CONFIRM_SWAPCHAIN = 6,
0366     VISUAL_CONFIRM_FAMS = 7,
0367     VISUAL_CONFIRM_SWIZZLE = 9,
0368 };
0369 
0370 enum dc_psr_power_opts {
0371     psr_power_opt_invalid = 0x0,
0372     psr_power_opt_smu_opt_static_screen = 0x1,
0373     psr_power_opt_z10_static_screen = 0x10,
0374     psr_power_opt_ds_disable_allow = 0x100,
0375 };
0376 
0377 enum dml_hostvm_override_opts {
0378     DML_HOSTVM_NO_OVERRIDE = 0x0,
0379     DML_HOSTVM_OVERRIDE_FALSE = 0x1,
0380     DML_HOSTVM_OVERRIDE_TRUE = 0x2,
0381 };
0382 
0383 enum dcc_option {
0384     DCC_ENABLE = 0,
0385     DCC_DISABLE = 1,
0386     DCC_HALF_REQ_DISALBE = 2,
0387 };
0388 
0389 enum pipe_split_policy {
0390     MPC_SPLIT_DYNAMIC = 0,
0391     MPC_SPLIT_AVOID = 1,
0392     MPC_SPLIT_AVOID_MULT_DISP = 2,
0393 };
0394 
0395 enum wm_report_mode {
0396     WM_REPORT_DEFAULT = 0,
0397     WM_REPORT_OVERRIDE = 1,
0398 };
0399 enum dtm_pstate{
0400     dtm_level_p0 = 0,/*highest voltage*/
0401     dtm_level_p1,
0402     dtm_level_p2,
0403     dtm_level_p3,
0404     dtm_level_p4,/*when active_display_count = 0*/
0405 };
0406 
0407 enum dcn_pwr_state {
0408     DCN_PWR_STATE_UNKNOWN = -1,
0409     DCN_PWR_STATE_MISSION_MODE = 0,
0410     DCN_PWR_STATE_LOW_POWER = 3,
0411 };
0412 
0413 enum dcn_zstate_support_state {
0414     DCN_ZSTATE_SUPPORT_UNKNOWN,
0415     DCN_ZSTATE_SUPPORT_ALLOW,
0416     DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
0417     DCN_ZSTATE_SUPPORT_DISALLOW,
0418 };
0419 /*
0420  * For any clocks that may differ per pipe
0421  * only the max is stored in this structure
0422  */
0423 struct dc_clocks {
0424     int dispclk_khz;
0425     int actual_dispclk_khz;
0426     int dppclk_khz;
0427     int actual_dppclk_khz;
0428     int disp_dpp_voltage_level_khz;
0429     int dcfclk_khz;
0430     int socclk_khz;
0431     int dcfclk_deep_sleep_khz;
0432     int fclk_khz;
0433     int phyclk_khz;
0434     int dramclk_khz;
0435     bool p_state_change_support;
0436     enum dcn_zstate_support_state zstate_support;
0437     bool dtbclk_en;
0438     int ref_dtbclk_khz;
0439     bool fclk_p_state_change_support;
0440     enum dcn_pwr_state pwr_state;
0441     /*
0442      * Elements below are not compared for the purposes of
0443      * optimization required
0444      */
0445     bool prev_p_state_change_support;
0446     bool fclk_prev_p_state_change_support;
0447     int num_ways;
0448     bool fw_based_mclk_switching;
0449     bool fw_based_mclk_switching_shut_down;
0450     int prev_num_ways;
0451     enum dtm_pstate dtm_level;
0452     int max_supported_dppclk_khz;
0453     int max_supported_dispclk_khz;
0454     int bw_dppclk_khz; /*a copy of dppclk_khz*/
0455     int bw_dispclk_khz;
0456 };
0457 
0458 struct dc_bw_validation_profile {
0459     bool enable;
0460 
0461     unsigned long long total_ticks;
0462     unsigned long long voltage_level_ticks;
0463     unsigned long long watermark_ticks;
0464     unsigned long long rq_dlg_ticks;
0465 
0466     unsigned long long total_count;
0467     unsigned long long skip_fast_count;
0468     unsigned long long skip_pass_count;
0469     unsigned long long skip_fail_count;
0470 };
0471 
0472 #define BW_VAL_TRACE_SETUP() \
0473         unsigned long long end_tick = 0; \
0474         unsigned long long voltage_level_tick = 0; \
0475         unsigned long long watermark_tick = 0; \
0476         unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
0477                 dm_get_timestamp(dc->ctx) : 0
0478 
0479 #define BW_VAL_TRACE_COUNT() \
0480         if (dc->debug.bw_val_profile.enable) \
0481             dc->debug.bw_val_profile.total_count++
0482 
0483 #define BW_VAL_TRACE_SKIP(status) \
0484         if (dc->debug.bw_val_profile.enable) { \
0485             if (!voltage_level_tick) \
0486                 voltage_level_tick = dm_get_timestamp(dc->ctx); \
0487             dc->debug.bw_val_profile.skip_ ## status ## _count++; \
0488         }
0489 
0490 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
0491         if (dc->debug.bw_val_profile.enable) \
0492             voltage_level_tick = dm_get_timestamp(dc->ctx)
0493 
0494 #define BW_VAL_TRACE_END_WATERMARKS() \
0495         if (dc->debug.bw_val_profile.enable) \
0496             watermark_tick = dm_get_timestamp(dc->ctx)
0497 
0498 #define BW_VAL_TRACE_FINISH() \
0499         if (dc->debug.bw_val_profile.enable) { \
0500             end_tick = dm_get_timestamp(dc->ctx); \
0501             dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
0502             dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
0503             if (watermark_tick) { \
0504                 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
0505                 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
0506             } \
0507         }
0508 
0509 union mem_low_power_enable_options {
0510     struct {
0511         bool vga: 1;
0512         bool i2c: 1;
0513         bool dmcu: 1;
0514         bool dscl: 1;
0515         bool cm: 1;
0516         bool mpc: 1;
0517         bool optc: 1;
0518         bool vpg: 1;
0519         bool afmt: 1;
0520     } bits;
0521     uint32_t u32All;
0522 };
0523 
0524 union root_clock_optimization_options {
0525     struct {
0526         bool dpp: 1;
0527         bool dsc: 1;
0528         bool hdmistream: 1;
0529         bool hdmichar: 1;
0530         bool dpstream: 1;
0531         bool symclk32_se: 1;
0532         bool symclk32_le: 1;
0533         bool symclk_fe: 1;
0534         bool physymclk: 1;
0535         bool dpiasymclk: 1;
0536         uint32_t reserved: 22;
0537     } bits;
0538     uint32_t u32All;
0539 };
0540 
0541 union dpia_debug_options {
0542     struct {
0543         uint32_t disable_dpia:1; /* bit 0 */
0544         uint32_t force_non_lttpr:1; /* bit 1 */
0545         uint32_t extend_aux_rd_interval:1; /* bit 2 */
0546         uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
0547         uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
0548         uint32_t reserved:27;
0549     } bits;
0550     uint32_t raw;
0551 };
0552 
0553 /* AUX wake work around options
0554  * 0: enable/disable work around
0555  * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
0556  * 15-2: reserved
0557  * 31-16: timeout in ms
0558  */
0559 union aux_wake_wa_options {
0560     struct {
0561         uint32_t enable_wa : 1;
0562         uint32_t use_default_timeout : 1;
0563         uint32_t rsvd: 14;
0564         uint32_t timeout_ms : 16;
0565     } bits;
0566     uint32_t raw;
0567 };
0568 
0569 struct dc_debug_data {
0570     uint32_t ltFailCount;
0571     uint32_t i2cErrorCount;
0572     uint32_t auxErrorCount;
0573 };
0574 
0575 struct dc_phy_addr_space_config {
0576     struct {
0577         uint64_t start_addr;
0578         uint64_t end_addr;
0579         uint64_t fb_top;
0580         uint64_t fb_offset;
0581         uint64_t fb_base;
0582         uint64_t agp_top;
0583         uint64_t agp_bot;
0584         uint64_t agp_base;
0585     } system_aperture;
0586 
0587     struct {
0588         uint64_t page_table_start_addr;
0589         uint64_t page_table_end_addr;
0590         uint64_t page_table_base_addr;
0591         bool base_addr_is_mc_addr;
0592     } gart_config;
0593 
0594     bool valid;
0595     bool is_hvm_enabled;
0596     uint64_t page_table_default_page_addr;
0597 };
0598 
0599 struct dc_virtual_addr_space_config {
0600     uint64_t    page_table_base_addr;
0601     uint64_t    page_table_start_addr;
0602     uint64_t    page_table_end_addr;
0603     uint32_t    page_table_block_size_in_bytes;
0604     uint8_t     page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
0605 };
0606 
0607 struct dc_bounding_box_overrides {
0608     int sr_exit_time_ns;
0609     int sr_enter_plus_exit_time_ns;
0610     int urgent_latency_ns;
0611     int percent_of_ideal_drambw;
0612     int dram_clock_change_latency_ns;
0613     int dummy_clock_change_latency_ns;
0614     int fclk_clock_change_latency_ns;
0615     /* This forces a hard min on the DCFCLK we use
0616      * for DML.  Unlike the debug option for forcing
0617      * DCFCLK, this override affects watermark calculations
0618      */
0619     int min_dcfclk_mhz;
0620 };
0621 
0622 struct dc_state;
0623 struct resource_pool;
0624 struct dce_hwseq;
0625 
0626 struct dc_debug_options {
0627     bool native422_support;
0628     bool disable_dsc;
0629     enum visual_confirm visual_confirm;
0630     int visual_confirm_rect_height;
0631 
0632     bool sanity_checks;
0633     bool max_disp_clk;
0634     bool surface_trace;
0635     bool timing_trace;
0636     bool clock_trace;
0637     bool validation_trace;
0638     bool bandwidth_calcs_trace;
0639     int max_downscale_src_width;
0640 
0641     /* stutter efficiency related */
0642     bool disable_stutter;
0643     bool use_max_lb;
0644     enum dcc_option disable_dcc;
0645     enum pipe_split_policy pipe_split_policy;
0646     bool force_single_disp_pipe_split;
0647     bool voltage_align_fclk;
0648     bool disable_min_fclk;
0649 
0650     bool disable_dfs_bypass;
0651     bool disable_dpp_power_gate;
0652     bool disable_hubp_power_gate;
0653     bool disable_dsc_power_gate;
0654     int dsc_min_slice_height_override;
0655     int dsc_bpp_increment_div;
0656     bool disable_pplib_wm_range;
0657     enum wm_report_mode pplib_wm_report_mode;
0658     unsigned int min_disp_clk_khz;
0659     unsigned int min_dpp_clk_khz;
0660     unsigned int min_dram_clk_khz;
0661     int sr_exit_time_dpm0_ns;
0662     int sr_enter_plus_exit_time_dpm0_ns;
0663     int sr_exit_time_ns;
0664     int sr_enter_plus_exit_time_ns;
0665     int urgent_latency_ns;
0666     uint32_t underflow_assert_delay_us;
0667     int percent_of_ideal_drambw;
0668     int dram_clock_change_latency_ns;
0669     bool optimized_watermark;
0670     int always_scale;
0671     bool disable_pplib_clock_request;
0672     bool disable_clock_gate;
0673     bool disable_mem_low_power;
0674     bool pstate_enabled;
0675     bool disable_dmcu;
0676     bool disable_psr;
0677     bool force_abm_enable;
0678     bool disable_stereo_support;
0679     bool vsr_support;
0680     bool performance_trace;
0681     bool az_endpoint_mute_only;
0682     bool always_use_regamma;
0683     bool recovery_enabled;
0684     bool avoid_vbios_exec_table;
0685     bool scl_reset_length10;
0686     bool hdmi20_disable;
0687     bool skip_detection_link_training;
0688     uint32_t edid_read_retry_times;
0689     unsigned int force_odm_combine; //bit vector based on otg inst
0690     unsigned int seamless_boot_odm_combine;
0691     unsigned int force_odm_combine_4to1; //bit vector based on otg inst
0692     bool disable_z9_mpc;
0693     unsigned int force_fclk_khz;
0694     bool enable_tri_buf;
0695     bool dmub_offload_enabled;
0696     bool dmcub_emulation;
0697     bool disable_idle_power_optimizations;
0698     unsigned int mall_size_override;
0699     unsigned int mall_additional_timer_percent;
0700     bool mall_error_as_fatal;
0701     bool dmub_command_table; /* for testing only */
0702     struct dc_bw_validation_profile bw_val_profile;
0703     bool disable_fec;
0704     bool disable_48mhz_pwrdwn;
0705     /* This forces a hard min on the DCFCLK requested to SMU/PP
0706      * watermarks are not affected.
0707      */
0708     unsigned int force_min_dcfclk_mhz;
0709     int dwb_fi_phase;
0710     bool disable_timing_sync;
0711     bool cm_in_bypass;
0712     int force_clock_mode;/*every mode change.*/
0713 
0714     bool disable_dram_clock_change_vactive_support;
0715     bool validate_dml_output;
0716     bool enable_dmcub_surface_flip;
0717     bool usbc_combo_phy_reset_wa;
0718     bool disable_dsc_edp;
0719     unsigned int  force_dsc_edp_policy;
0720     bool enable_dram_clock_change_one_display_vactive;
0721     /* TODO - remove once tested */
0722     bool legacy_dp2_lt;
0723     bool set_mst_en_for_sst;
0724     bool disable_uhbr;
0725     bool force_dp2_lt_fallback_method;
0726     bool ignore_cable_id;
0727     union mem_low_power_enable_options enable_mem_low_power;
0728     union root_clock_optimization_options root_clock_optimization;
0729     bool hpo_optimization;
0730     bool force_vblank_alignment;
0731 
0732     /* Enable dmub aux for legacy ddc */
0733     bool enable_dmub_aux_for_legacy_ddc;
0734     bool disable_fams;
0735     bool optimize_edp_link_rate; /* eDP ILR */
0736     /* FEC/PSR1 sequence enable delay in 100us */
0737     uint8_t fec_enable_delay_in100us;
0738     bool enable_driver_sequence_debug;
0739     enum det_size crb_alloc_policy;
0740     int crb_alloc_policy_min_disp_count;
0741     bool disable_z10;
0742     bool enable_z9_disable_interface;
0743     bool enable_sw_cntl_psr;
0744     union dpia_debug_options dpia_debug;
0745     bool disable_fixed_vs_aux_timeout_wa;
0746     bool force_disable_subvp;
0747     bool force_subvp_mclk_switch;
0748     bool allow_sw_cursor_fallback;
0749     bool force_usr_allow;
0750     /* uses value at boot and disables switch */
0751     bool disable_dtb_ref_clk_switch;
0752     uint32_t fixed_vs_aux_delay_config_wa;
0753     bool extended_blank_optimization;
0754     union aux_wake_wa_options aux_wake_wa;
0755     uint32_t mst_start_top_delay;
0756     uint8_t psr_power_use_phy_fsm;
0757     enum dml_hostvm_override_opts dml_hostvm_override;
0758     bool dml_disallow_alternate_prefetch_modes;
0759     bool use_legacy_soc_bb_mechanism;
0760     bool exit_idle_opt_for_cursor_updates;
0761     bool enable_single_display_2to1_odm_policy;
0762     bool enable_dp_dig_pixel_rate_div_policy;
0763 };
0764 
0765 struct gpu_info_soc_bounding_box_v1_0;
0766 struct dc {
0767     struct dc_debug_options debug;
0768     struct dc_versions versions;
0769     struct dc_caps caps;
0770     struct dc_cap_funcs cap_funcs;
0771     struct dc_config config;
0772     struct dc_bounding_box_overrides bb_overrides;
0773     struct dc_bug_wa work_arounds;
0774     struct dc_context *ctx;
0775     struct dc_phy_addr_space_config vm_pa_config;
0776 
0777     uint8_t link_count;
0778     struct dc_link *links[MAX_PIPES * 2];
0779 
0780     struct dc_state *current_state;
0781     struct resource_pool *res_pool;
0782 
0783     struct clk_mgr *clk_mgr;
0784 
0785     /* Display Engine Clock levels */
0786     struct dm_pp_clock_levels sclk_lvls;
0787 
0788     /* Inputs into BW and WM calculations. */
0789     struct bw_calcs_dceip *bw_dceip;
0790     struct bw_calcs_vbios *bw_vbios;
0791     struct dcn_soc_bounding_box *dcn_soc;
0792     struct dcn_ip_params *dcn_ip;
0793     struct display_mode_lib dml;
0794 
0795     /* HW functions */
0796     struct hw_sequencer_funcs hwss;
0797     struct dce_hwseq *hwseq;
0798 
0799     /* Require to optimize clocks and bandwidth for added/removed planes */
0800     bool optimized_required;
0801     bool wm_optimized_required;
0802     bool idle_optimizations_allowed;
0803     bool enable_c20_dtm_b0;
0804 
0805     /* Require to maintain clocks and bandwidth for UEFI enabled HW */
0806 
0807     /* FBC compressor */
0808     struct compressor *fbc_compressor;
0809 
0810     struct dc_debug_data debug_data;
0811     struct dpcd_vendor_signature vendor_signature;
0812 
0813     const char *build_id;
0814     struct vm_helper *vm_helper;
0815 
0816     uint32_t *dcn_reg_offsets;
0817     uint32_t *nbio_reg_offsets;
0818 };
0819 
0820 enum frame_buffer_mode {
0821     FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
0822     FRAME_BUFFER_MODE_ZFB_ONLY,
0823     FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
0824 } ;
0825 
0826 struct dchub_init_data {
0827     int64_t zfb_phys_addr_base;
0828     int64_t zfb_mc_base_addr;
0829     uint64_t zfb_size_in_byte;
0830     enum frame_buffer_mode fb_mode;
0831     bool dchub_initialzied;
0832     bool dchub_info_valid;
0833 };
0834 
0835 struct dc_init_data {
0836     struct hw_asic_id asic_id;
0837     void *driver; /* ctx */
0838     struct cgs_device *cgs_device;
0839     struct dc_bounding_box_overrides bb_overrides;
0840 
0841     int num_virtual_links;
0842     /*
0843      * If 'vbios_override' not NULL, it will be called instead
0844      * of the real VBIOS. Intended use is Diagnostics on FPGA.
0845      */
0846     struct dc_bios *vbios_override;
0847     enum dce_environment dce_environment;
0848 
0849     struct dmub_offload_funcs *dmub_if;
0850     struct dc_reg_helper_state *dmub_offload;
0851 
0852     struct dc_config flags;
0853     uint64_t log_mask;
0854 
0855     struct dpcd_vendor_signature vendor_signature;
0856     bool force_smu_not_present;
0857     /*
0858      * IP offset for run time initializaion of register addresses
0859      *
0860      * DCN3.5+ will fail dc_create() if these fields are null for them. They are
0861      * applicable starting with DCN32/321 and are not used for ASICs upstreamed
0862      * before them.
0863      */
0864     uint32_t *dcn_reg_offsets;
0865     uint32_t *nbio_reg_offsets;
0866 };
0867 
0868 struct dc_callback_init {
0869 #ifdef CONFIG_DRM_AMD_DC_HDCP
0870     struct cp_psp cp_psp;
0871 #else
0872     uint8_t reserved;
0873 #endif
0874 };
0875 
0876 struct dc *dc_create(const struct dc_init_data *init_params);
0877 void dc_hardware_init(struct dc *dc);
0878 
0879 int dc_get_vmid_use_vector(struct dc *dc);
0880 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
0881 /* Returns the number of vmids supported */
0882 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
0883 void dc_init_callbacks(struct dc *dc,
0884         const struct dc_callback_init *init_params);
0885 void dc_deinit_callbacks(struct dc *dc);
0886 void dc_destroy(struct dc **dc);
0887 
0888 /*******************************************************************************
0889  * Surface Interfaces
0890  ******************************************************************************/
0891 
0892 enum {
0893     TRANSFER_FUNC_POINTS = 1025
0894 };
0895 
0896 struct dc_hdr_static_metadata {
0897     /* display chromaticities and white point in units of 0.00001 */
0898     unsigned int chromaticity_green_x;
0899     unsigned int chromaticity_green_y;
0900     unsigned int chromaticity_blue_x;
0901     unsigned int chromaticity_blue_y;
0902     unsigned int chromaticity_red_x;
0903     unsigned int chromaticity_red_y;
0904     unsigned int chromaticity_white_point_x;
0905     unsigned int chromaticity_white_point_y;
0906 
0907     uint32_t min_luminance;
0908     uint32_t max_luminance;
0909     uint32_t maximum_content_light_level;
0910     uint32_t maximum_frame_average_light_level;
0911 };
0912 
0913 enum dc_transfer_func_type {
0914     TF_TYPE_PREDEFINED,
0915     TF_TYPE_DISTRIBUTED_POINTS,
0916     TF_TYPE_BYPASS,
0917     TF_TYPE_HWPWL
0918 };
0919 
0920 struct dc_transfer_func_distributed_points {
0921     struct fixed31_32 red[TRANSFER_FUNC_POINTS];
0922     struct fixed31_32 green[TRANSFER_FUNC_POINTS];
0923     struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
0924 
0925     uint16_t end_exponent;
0926     uint16_t x_point_at_y1_red;
0927     uint16_t x_point_at_y1_green;
0928     uint16_t x_point_at_y1_blue;
0929 };
0930 
0931 enum dc_transfer_func_predefined {
0932     TRANSFER_FUNCTION_SRGB,
0933     TRANSFER_FUNCTION_BT709,
0934     TRANSFER_FUNCTION_PQ,
0935     TRANSFER_FUNCTION_LINEAR,
0936     TRANSFER_FUNCTION_UNITY,
0937     TRANSFER_FUNCTION_HLG,
0938     TRANSFER_FUNCTION_HLG12,
0939     TRANSFER_FUNCTION_GAMMA22,
0940     TRANSFER_FUNCTION_GAMMA24,
0941     TRANSFER_FUNCTION_GAMMA26
0942 };
0943 
0944 
0945 struct dc_transfer_func {
0946     struct kref refcount;
0947     enum dc_transfer_func_type type;
0948     enum dc_transfer_func_predefined tf;
0949     /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
0950     uint32_t sdr_ref_white_level;
0951     union {
0952         struct pwl_params pwl;
0953         struct dc_transfer_func_distributed_points tf_pts;
0954     };
0955 };
0956 
0957 
0958 union dc_3dlut_state {
0959     struct {
0960         uint32_t initialized:1;     /*if 3dlut is went through color module for initialization */
0961         uint32_t rmu_idx_valid:1;   /*if mux settings are valid*/
0962         uint32_t rmu_mux_num:3;     /*index of mux to use*/
0963         uint32_t mpc_rmu0_mux:4;    /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
0964         uint32_t mpc_rmu1_mux:4;
0965         uint32_t mpc_rmu2_mux:4;
0966         uint32_t reserved:15;
0967     } bits;
0968     uint32_t raw;
0969 };
0970 
0971 
0972 struct dc_3dlut {
0973     struct kref refcount;
0974     struct tetrahedral_params lut_3d;
0975     struct fixed31_32 hdr_multiplier;
0976     union dc_3dlut_state state;
0977 };
0978 /*
0979  * This structure is filled in by dc_surface_get_status and contains
0980  * the last requested address and the currently active address so the called
0981  * can determine if there are any outstanding flips
0982  */
0983 struct dc_plane_status {
0984     struct dc_plane_address requested_address;
0985     struct dc_plane_address current_address;
0986     bool is_flip_pending;
0987     bool is_right_eye;
0988 };
0989 
0990 union surface_update_flags {
0991 
0992     struct {
0993         uint32_t addr_update:1;
0994         /* Medium updates */
0995         uint32_t dcc_change:1;
0996         uint32_t color_space_change:1;
0997         uint32_t horizontal_mirror_change:1;
0998         uint32_t per_pixel_alpha_change:1;
0999         uint32_t global_alpha_change:1;
1000         uint32_t hdr_mult:1;
1001         uint32_t rotation_change:1;
1002         uint32_t swizzle_change:1;
1003         uint32_t scaling_change:1;
1004         uint32_t position_change:1;
1005         uint32_t in_transfer_func_change:1;
1006         uint32_t input_csc_change:1;
1007         uint32_t coeff_reduction_change:1;
1008         uint32_t output_tf_change:1;
1009         uint32_t pixel_format_change:1;
1010         uint32_t plane_size_change:1;
1011         uint32_t gamut_remap_change:1;
1012 
1013         /* Full updates */
1014         uint32_t new_plane:1;
1015         uint32_t bpp_change:1;
1016         uint32_t gamma_change:1;
1017         uint32_t bandwidth_change:1;
1018         uint32_t clock_change:1;
1019         uint32_t stereo_format_change:1;
1020         uint32_t lut_3d:1;
1021         uint32_t full_update:1;
1022     } bits;
1023 
1024     uint32_t raw;
1025 };
1026 
1027 struct dc_plane_state {
1028     struct dc_plane_address address;
1029     struct dc_plane_flip_time time;
1030     bool triplebuffer_flips;
1031     struct scaling_taps scaling_quality;
1032     struct rect src_rect;
1033     struct rect dst_rect;
1034     struct rect clip_rect;
1035 
1036     struct plane_size plane_size;
1037     union dc_tiling_info tiling_info;
1038 
1039     struct dc_plane_dcc_param dcc;
1040 
1041     struct dc_gamma *gamma_correction;
1042     struct dc_transfer_func *in_transfer_func;
1043     struct dc_bias_and_scale *bias_and_scale;
1044     struct dc_csc_transform input_csc_color_matrix;
1045     struct fixed31_32 coeff_reduction_factor;
1046     struct fixed31_32 hdr_mult;
1047     struct colorspace_transform gamut_remap_matrix;
1048 
1049     // TODO: No longer used, remove
1050     struct dc_hdr_static_metadata hdr_static_ctx;
1051 
1052     enum dc_color_space color_space;
1053 
1054     struct dc_3dlut *lut3d_func;
1055     struct dc_transfer_func *in_shaper_func;
1056     struct dc_transfer_func *blend_tf;
1057 
1058     struct dc_transfer_func *gamcor_tf;
1059     enum surface_pixel_format format;
1060     enum dc_rotation_angle rotation;
1061     enum plane_stereo_format stereo_format;
1062 
1063     bool is_tiling_rotated;
1064     bool per_pixel_alpha;
1065     bool pre_multiplied_alpha;
1066     bool global_alpha;
1067     int  global_alpha_value;
1068     bool visible;
1069     bool flip_immediate;
1070     bool horizontal_mirror;
1071     int layer_index;
1072 
1073     union surface_update_flags update_flags;
1074     bool flip_int_enabled;
1075     bool skip_manual_trigger;
1076 
1077     /* private to DC core */
1078     struct dc_plane_status status;
1079     struct dc_context *ctx;
1080 
1081     /* HACK: Workaround for forcing full reprogramming under some conditions */
1082     bool force_full_update;
1083 
1084     bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1085 
1086     /* private to dc_surface.c */
1087     enum dc_irq_source irq_source;
1088     struct kref refcount;
1089 };
1090 
1091 struct dc_plane_info {
1092     struct plane_size plane_size;
1093     union dc_tiling_info tiling_info;
1094     struct dc_plane_dcc_param dcc;
1095     enum surface_pixel_format format;
1096     enum dc_rotation_angle rotation;
1097     enum plane_stereo_format stereo_format;
1098     enum dc_color_space color_space;
1099     bool horizontal_mirror;
1100     bool visible;
1101     bool per_pixel_alpha;
1102     bool pre_multiplied_alpha;
1103     bool global_alpha;
1104     int  global_alpha_value;
1105     bool input_csc_enabled;
1106     int layer_index;
1107 };
1108 
1109 struct dc_scaling_info {
1110     struct rect src_rect;
1111     struct rect dst_rect;
1112     struct rect clip_rect;
1113     struct scaling_taps scaling_quality;
1114 };
1115 
1116 struct dc_surface_update {
1117     struct dc_plane_state *surface;
1118 
1119     /* isr safe update parameters.  null means no updates */
1120     const struct dc_flip_addrs *flip_addr;
1121     const struct dc_plane_info *plane_info;
1122     const struct dc_scaling_info *scaling_info;
1123     struct fixed31_32 hdr_mult;
1124     /* following updates require alloc/sleep/spin that is not isr safe,
1125      * null means no updates
1126      */
1127     const struct dc_gamma *gamma;
1128     const struct dc_transfer_func *in_transfer_func;
1129 
1130     const struct dc_csc_transform *input_csc_color_matrix;
1131     const struct fixed31_32 *coeff_reduction_factor;
1132     const struct dc_transfer_func *func_shaper;
1133     const struct dc_3dlut *lut3d_func;
1134     const struct dc_transfer_func *blend_tf;
1135     const struct colorspace_transform *gamut_remap_matrix;
1136 };
1137 
1138 /*
1139  * Create a new surface with default parameters;
1140  */
1141 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1142 const struct dc_plane_status *dc_plane_get_status(
1143         const struct dc_plane_state *plane_state);
1144 
1145 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1146 void dc_plane_state_release(struct dc_plane_state *plane_state);
1147 
1148 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1149 void dc_gamma_release(struct dc_gamma **dc_gamma);
1150 struct dc_gamma *dc_create_gamma(void);
1151 
1152 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1153 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1154 struct dc_transfer_func *dc_create_transfer_func(void);
1155 
1156 struct dc_3dlut *dc_create_3dlut_func(void);
1157 void dc_3dlut_func_release(struct dc_3dlut *lut);
1158 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1159 
1160 void dc_post_update_surfaces_to_stream(
1161         struct dc *dc);
1162 
1163 #include "dc_stream.h"
1164 
1165 /*
1166  * Structure to store surface/stream associations for validation
1167  */
1168 struct dc_validation_set {
1169     struct dc_stream_state *stream;
1170     struct dc_plane_state *plane_states[MAX_SURFACES];
1171     uint8_t plane_count;
1172 };
1173 
1174 bool dc_validate_boot_timing(const struct dc *dc,
1175                 const struct dc_sink *sink,
1176                 struct dc_crtc_timing *crtc_timing);
1177 
1178 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1179 
1180 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1181 
1182 bool dc_set_generic_gpio_for_stereo(bool enable,
1183         struct gpio_service *gpio_service);
1184 
1185 /*
1186  * fast_validate: we return after determining if we can support the new state,
1187  * but before we populate the programming info
1188  */
1189 enum dc_status dc_validate_global_state(
1190         struct dc *dc,
1191         struct dc_state *new_ctx,
1192         bool fast_validate);
1193 
1194 
1195 void dc_resource_state_construct(
1196         const struct dc *dc,
1197         struct dc_state *dst_ctx);
1198 
1199 bool dc_acquire_release_mpc_3dlut(
1200         struct dc *dc, bool acquire,
1201         struct dc_stream_state *stream,
1202         struct dc_3dlut **lut,
1203         struct dc_transfer_func **shaper);
1204 
1205 void dc_resource_state_copy_construct(
1206         const struct dc_state *src_ctx,
1207         struct dc_state *dst_ctx);
1208 
1209 void dc_resource_state_copy_construct_current(
1210         const struct dc *dc,
1211         struct dc_state *dst_ctx);
1212 
1213 void dc_resource_state_destruct(struct dc_state *context);
1214 
1215 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1216 
1217 /*
1218  * TODO update to make it about validation sets
1219  * Set up streams and links associated to drive sinks
1220  * The streams parameter is an absolute set of all active streams.
1221  *
1222  * After this call:
1223  *   Phy, Encoder, Timing Generator are programmed and enabled.
1224  *   New streams are enabled with blank stream; no memory read.
1225  */
1226 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1227 
1228 struct dc_state *dc_create_state(struct dc *dc);
1229 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1230 void dc_retain_state(struct dc_state *context);
1231 void dc_release_state(struct dc_state *context);
1232 
1233 /*******************************************************************************
1234  * Link Interfaces
1235  ******************************************************************************/
1236 
1237 struct dpcd_caps {
1238     union dpcd_rev dpcd_rev;
1239     union max_lane_count max_ln_count;
1240     union max_down_spread max_down_spread;
1241     union dprx_feature dprx_feature;
1242 
1243     /* valid only for eDP v1.4 or higher*/
1244     uint8_t edp_supported_link_rates_count;
1245     enum dc_link_rate edp_supported_link_rates[8];
1246 
1247     /* dongle type (DP converter, CV smart dongle) */
1248     enum display_dongle_type dongle_type;
1249     bool is_dongle_type_one;
1250     /* branch device or sink device */
1251     bool is_branch_dev;
1252     /* Dongle's downstream count. */
1253     union sink_count sink_count;
1254     bool is_mst_capable;
1255     /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1256     indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1257     struct dc_dongle_caps dongle_caps;
1258 
1259     uint32_t sink_dev_id;
1260     int8_t sink_dev_id_str[6];
1261     int8_t sink_hw_revision;
1262     int8_t sink_fw_revision[2];
1263 
1264     uint32_t branch_dev_id;
1265     int8_t branch_dev_name[6];
1266     int8_t branch_hw_revision;
1267     int8_t branch_fw_revision[2];
1268 
1269     bool allow_invalid_MSA_timing_param;
1270     bool panel_mode_edp;
1271     bool dpcd_display_control_capable;
1272     bool ext_receiver_cap_field_present;
1273     bool set_power_state_capable_edp;
1274     bool dynamic_backlight_capable_edp;
1275     union dpcd_fec_capability fec_cap;
1276     struct dpcd_dsc_capabilities dsc_caps;
1277     struct dc_lttpr_caps lttpr_caps;
1278     struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1279 
1280     union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1281     union dp_main_line_channel_coding_cap channel_coding_cap;
1282     union dp_sink_video_fallback_formats fallback_formats;
1283     union dp_fec_capability1 fec_cap1;
1284     union dp_cable_id cable_id;
1285     uint8_t edp_rev;
1286     union edp_alpm_caps alpm_caps;
1287     struct edp_psr_info psr_info;
1288 };
1289 
1290 union dpcd_sink_ext_caps {
1291     struct {
1292         /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1293          * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1294          */
1295         uint8_t sdr_aux_backlight_control : 1;
1296         uint8_t hdr_aux_backlight_control : 1;
1297         uint8_t reserved_1 : 2;
1298         uint8_t oled : 1;
1299         uint8_t reserved : 3;
1300     } bits;
1301     uint8_t raw;
1302 };
1303 
1304 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1305 union hdcp_rx_caps {
1306     struct {
1307         uint8_t version;
1308         uint8_t reserved;
1309         struct {
1310             uint8_t repeater    : 1;
1311             uint8_t hdcp_capable    : 1;
1312             uint8_t reserved    : 6;
1313         } byte0;
1314     } fields;
1315     uint8_t raw[3];
1316 };
1317 
1318 union hdcp_bcaps {
1319     struct {
1320         uint8_t HDCP_CAPABLE:1;
1321         uint8_t REPEATER:1;
1322         uint8_t RESERVED:6;
1323     } bits;
1324     uint8_t raw;
1325 };
1326 
1327 struct hdcp_caps {
1328     union hdcp_rx_caps rx_caps;
1329     union hdcp_bcaps bcaps;
1330 };
1331 #endif
1332 
1333 #include "dc_link.h"
1334 
1335 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1336 
1337 /*******************************************************************************
1338  * Sink Interfaces - A sink corresponds to a display output device
1339  ******************************************************************************/
1340 
1341 struct dc_container_id {
1342     // 128bit GUID in binary form
1343     unsigned char  guid[16];
1344     // 8 byte port ID -> ELD.PortID
1345     unsigned int   portId[2];
1346     // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1347     unsigned short manufacturerName;
1348     // 2 byte product code -> ELD.ProductCode
1349     unsigned short productCode;
1350 };
1351 
1352 
1353 struct dc_sink_dsc_caps {
1354     // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1355     // 'false' if they are sink's DSC caps
1356     bool is_virtual_dpcd_dsc;
1357 #if defined(CONFIG_DRM_AMD_DC_DCN)
1358     // 'true' if MST topology supports DSC passthrough for sink
1359     // 'false' if MST topology does not support DSC passthrough
1360     bool is_dsc_passthrough_supported;
1361 #endif
1362     struct dsc_dec_dpcd_caps dsc_dec_caps;
1363 };
1364 
1365 struct dc_sink_fec_caps {
1366     bool is_rx_fec_supported;
1367     bool is_topology_fec_supported;
1368 };
1369 
1370 /*
1371  * The sink structure contains EDID and other display device properties
1372  */
1373 struct dc_sink {
1374     enum signal_type sink_signal;
1375     struct dc_edid dc_edid; /* raw edid */
1376     struct dc_edid_caps edid_caps; /* parse display caps */
1377     struct dc_container_id *dc_container_id;
1378     uint32_t dongle_max_pix_clk;
1379     void *priv;
1380     struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1381     bool converter_disable_audio;
1382 
1383     struct dc_sink_dsc_caps dsc_caps;
1384     struct dc_sink_fec_caps fec_caps;
1385 
1386     bool is_vsc_sdp_colorimetry_supported;
1387 
1388     /* private to DC core */
1389     struct dc_link *link;
1390     struct dc_context *ctx;
1391 
1392     uint32_t sink_id;
1393 
1394     /* private to dc_sink.c */
1395     // refcount must be the last member in dc_sink, since we want the
1396     // sink structure to be logically cloneable up to (but not including)
1397     // refcount
1398     struct kref refcount;
1399 };
1400 
1401 void dc_sink_retain(struct dc_sink *sink);
1402 void dc_sink_release(struct dc_sink *sink);
1403 
1404 struct dc_sink_init_data {
1405     enum signal_type sink_signal;
1406     struct dc_link *link;
1407     uint32_t dongle_max_pix_clk;
1408     bool converter_disable_audio;
1409 };
1410 
1411 bool dc_extended_blank_supported(struct dc *dc);
1412 
1413 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1414 
1415 /* Newer interfaces  */
1416 struct dc_cursor {
1417     struct dc_plane_address address;
1418     struct dc_cursor_attributes attributes;
1419 };
1420 
1421 
1422 /*******************************************************************************
1423  * Interrupt interfaces
1424  ******************************************************************************/
1425 enum dc_irq_source dc_interrupt_to_irq_source(
1426         struct dc *dc,
1427         uint32_t src_id,
1428         uint32_t ext_id);
1429 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1430 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1431 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1432         struct dc *dc, uint32_t link_index);
1433 
1434 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1435 
1436 /*******************************************************************************
1437  * Power Interfaces
1438  ******************************************************************************/
1439 
1440 void dc_set_power_state(
1441         struct dc *dc,
1442         enum dc_acpi_cm_power_state power_state);
1443 void dc_resume(struct dc *dc);
1444 
1445 void dc_power_down_on_boot(struct dc *dc);
1446 
1447 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1448 /*
1449  * HDCP Interfaces
1450  */
1451 enum hdcp_message_status dc_process_hdcp_msg(
1452         enum signal_type signal,
1453         struct dc_link *link,
1454         struct hdcp_protection_message *message_info);
1455 #endif
1456 bool dc_is_dmcu_initialized(struct dc *dc);
1457 
1458 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1459 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1460 
1461 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1462                 struct dc_cursor_attributes *cursor_attr);
1463 
1464 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1465 
1466 /* set min and max memory clock to lowest and highest DPM level, respectively */
1467 void dc_unlock_memory_clock_frequency(struct dc *dc);
1468 
1469 /* set min memory clock to the min required for current mode, max to maxDPM */
1470 void dc_lock_memory_clock_frequency(struct dc *dc);
1471 
1472 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
1473 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1474 
1475 /* cleanup on driver unload */
1476 void dc_hardware_release(struct dc *dc);
1477 
1478 /* disables fw based mclk switch */
1479 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
1480 
1481 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1482 void dc_z10_restore(const struct dc *dc);
1483 void dc_z10_save_init(struct dc *dc);
1484 
1485 bool dc_is_dmub_outbox_supported(struct dc *dc);
1486 bool dc_enable_dmub_notifications(struct dc *dc);
1487 
1488 void dc_enable_dmub_outbox(struct dc *dc);
1489 
1490 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1491                 uint32_t link_index,
1492                 struct aux_payload *payload);
1493 
1494 /* Get dc link index from dpia port index */
1495 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1496                 uint8_t dpia_port_index);
1497 
1498 bool dc_process_dmub_set_config_async(struct dc *dc,
1499                 uint32_t link_index,
1500                 struct set_config_cmd_payload *payload,
1501                 struct dmub_notification *notify);
1502 
1503 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1504                 uint32_t link_index,
1505                 uint8_t mst_alloc_slots,
1506                 uint8_t *mst_slots_in_use);
1507 
1508 /*******************************************************************************
1509  * DSC Interfaces
1510  ******************************************************************************/
1511 #include "dc_dsc.h"
1512 
1513 /*******************************************************************************
1514  * Disable acc mode Interfaces
1515  ******************************************************************************/
1516 void dc_disable_accelerated_mode(struct dc *dc);
1517 
1518 #endif /* DC_INTERFACE_H_ */
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