clk_mgr/dcn32/dalsmc.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026 #ifndef DALSMC_H
0027 #define DALSMC_H
0028
0029 #define DALSMC_VERSION 0x1
0030
0031 // SMU Response Codes:
0032 #define DALSMC_Result_OK                   0x1
0033 #define DALSMC_Result_Failed               0xFF
0034 #define DALSMC_Result_UnknownCmd           0xFE
0035 #define DALSMC_Result_CmdRejectedPrereq    0xFD
0036 #define DALSMC_Result_CmdRejectedBusy      0xFC
0037
0038 // Message Definitions:
0039 #define DALSMC_MSG_TestMessage                    0x1
0040 #define DALSMC_MSG_GetSmuVersion                  0x2
0041 #define DALSMC_MSG_GetDriverIfVersion             0x3
0042 #define DALSMC_MSG_GetMsgHeaderVersion            0x4
0043 #define DALSMC_MSG_SetDalDramAddrHigh             0x5
0044 #define DALSMC_MSG_SetDalDramAddrLow              0x6
0045 #define DALSMC_MSG_TransferTableSmu2Dram          0x7
0046 #define DALSMC_MSG_TransferTableDram2Smu          0x8
0047 #define DALSMC_MSG_SetHardMinByFreq               0x9
0048 #define DALSMC_MSG_SetHardMaxByFreq               0xA
0049 #define DALSMC_MSG_GetDpmFreqByIndex              0xB
0050 #define DALSMC_MSG_GetDcModeMaxDpmFreq            0xC
0051 #define DALSMC_MSG_SetMinDeepSleepDcfclk          0xD
0052 #define DALSMC_MSG_NumOfDisplays                  0xE
0053 #define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF
0054 #define DALSMC_MSG_BacoAudioD3PME                 0x10
0055 #define DALSMC_MSG_SetFclkSwitchAllow             0x11
0056 #define DALSMC_MSG_SetCabForUclkPstate            0x12
0057 #define DALSMC_MSG_SetWorstCaseUclkLatency        0x13
0058 #define DALSMC_Message_Count                      0x14
0059
0060 typedef enum {
0061     FCLK_SWITCH_DISALLOW,
0062     FCLK_SWITCH_ALLOW,
0063 } FclkSwitchAllow_e;
0064
0065 #endif