clk_mgr/dcn316/dcn316_smu.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: AMD
0023  *
0024  */
0025
0026 #ifndef DAL_DC_316_SMU_H_
0027 #define DAL_DC_316_SMU_H_
0028 #include "os_types.h"
0029
0030 #define PMFW_DRIVER_IF_VERSION 4
0031
0032 #define NUM_DCFCLK_DPM_LEVELS   8
0033 #define NUM_DISPCLK_DPM_LEVELS  8
0034 #define NUM_DPPCLK_DPM_LEVELS   8
0035 #define NUM_SOCCLK_DPM_LEVELS   8
0036 #define NUM_VCN_DPM_LEVELS      8
0037 #define NUM_SOC_VOLTAGE_LEVELS  8
0038 #define NUM_DF_PSTATE_LEVELS    4
0039
0040 typedef struct {
0041   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
0042   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
0043   uint16_t MinMclk;
0044   uint16_t MaxMclk;
0045   uint8_t  WmSetting;
0046   uint8_t  WmType;  // Used for normal pstate change or memory retraining
0047   uint8_t  Padding[2];
0048 } WatermarkRowGeneric_t;
0049
0050 #define NUM_WM_RANGES 4
0051 #define WM_PSTATE_CHG 0
0052 #define WM_RETRAINING 1
0053
0054 typedef enum {
0055   WM_SOCCLK = 0,
0056   WM_DCFCLK,
0057   WM_COUNT,
0058 } WM_CLOCK_e;
0059
0060 typedef enum{
0061   WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
0062   WCK_RATIO_1_2,
0063   WCK_RATIO_1_4,
0064   WCK_RATIO_MAX
0065 } WCK_RATIO_e;
0066
0067 typedef struct {
0068   uint32_t FClk;
0069   uint32_t MemClk;
0070   uint32_t Voltage;
0071   uint8_t  WckRatio;
0072   uint8_t  Spare[3];
0073 } DfPstateTable_t;
0074
0075 //Freq in MHz
0076 //Voltage in milli volts with 2 fractional bits
0077 typedef struct {
0078   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
0079   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
0080   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
0081   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
0082   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
0083   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
0084   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
0085   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
0086   uint8_t  NumDcfClkLevelsEnabled;
0087   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
0088   uint8_t  NumSocClkLevelsEnabled;
0089   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
0090   uint8_t  NumDfPstatesEnabled;
0091   uint8_t  spare[3];
0092   uint32_t MinGfxClk;
0093   uint32_t MaxGfxClk;
0094 } DpmClocks_316_t;
0095
0096 struct dcn316_watermarks {
0097   // Watermarks
0098   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0099   uint32_t MmHubPadding[7]; // SMU internal use
0100 };
0101
0102 struct dcn316_smu_dpm_clks {
0103     DpmClocks_316_t *dpm_clks;
0104     union large_integer mc_address;
0105 };
0106
0107 #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
0108 #define TABLE_DPMCLOCKS          4 // Called by Driver and VBIOS
0109
0110 struct display_idle_optimization {
0111     unsigned int df_request_disabled : 1;
0112     unsigned int phy_ref_clk_off     : 1;
0113     unsigned int s0i2_rdy            : 1;
0114     unsigned int reserved            : 29;
0115 };
0116
0117 union display_idle_optimization_u {
0118     struct display_idle_optimization idle_info;
0119     uint32_t data;
0120 };
0121
0122 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
0123 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
0124 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
0125 int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
0126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
0127 void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
0128 void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
0129 void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
0130 void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
0131 void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
0132 void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
0133 void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
0134 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
0135 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
0136 int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
0137 int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);
0138
0139 #endif /* DAL_DC_316_SMU_H_ */