clk_mgr/dcn314/dcn314_smu.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright 2022 Advanced Micro Devices, Inc.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0019  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0020  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0021  * OTHER DEALINGS IN THE SOFTWARE.
0022  *
0023  * Authors: AMD
0024  *
0025  */
0026
0027 #ifndef DAL_DC_314_SMU_H_
0028 #define DAL_DC_314_SMU_H_
0029
0030 #include "smu13_driver_if_v13_0_4.h"
0031
0032 typedef enum {
0033     WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
0034     WCK_RATIO_1_2,
0035     WCK_RATIO_1_4,
0036     WCK_RATIO_MAX
0037 } WCK_RATIO_e;
0038
0039 typedef struct {
0040   uint32_t FClk;
0041   uint32_t MemClk;
0042   uint32_t Voltage;
0043   uint8_t  WckRatio;
0044   uint8_t  Spare[3];
0045 } DfPstateTable314_t;
0046
0047 //Freq in MHz
0048 //Voltage in milli volts with 2 fractional bits
0049 typedef struct {
0050   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
0051   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
0052   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
0053   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
0054   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
0055   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
0056   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
0057   DfPstateTable314_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
0058
0059   uint8_t  NumDcfClkLevelsEnabled;
0060   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
0061   uint8_t  NumSocClkLevelsEnabled;
0062   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
0063   uint8_t  NumDfPstatesEnabled;
0064   uint8_t  spare[3];
0065
0066   uint32_t MinGfxClk;
0067   uint32_t MaxGfxClk;
0068 } DpmClocks314_t;
0069
0070 struct dcn314_watermarks {
0071     // Watermarks
0072     WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0073     uint32_t MmHubPadding[7]; // SMU internal use
0074 };
0075
0076 struct dcn314_smu_dpm_clks {
0077     DpmClocks314_t *dpm_clks;
0078     union large_integer mc_address;
0079 };
0080
0081 struct display_idle_optimization {
0082     unsigned int df_request_disabled : 1;
0083     unsigned int phy_ref_clk_off     : 1;
0084     unsigned int s0i2_rdy            : 1;
0085     unsigned int reserved            : 29;
0086 };
0087
0088 union display_idle_optimization_u {
0089     struct display_idle_optimization idle_info;
0090     uint32_t data;
0091 };
0092
0093 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
0094 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
0095 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
0096 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
0097 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
0098 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
0099 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
0100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
0101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
0102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
0103 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
0104 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
0105 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
0106
0107 void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);
0108 void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
0109
0110 #endif /* DAL_DC_314_SMU_H_ */